[PATCH v1 2/2] riscv: Fallback to riscv,isa

Mayuresh Chitale
2025-01-06T13:04:47Z

Update the cpu probing to fallback to "riscv,isa" property if
"riscv,isa-extensions" is not available and modify the riscv CMO code
to use the block size that was probed during cpu setup.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
---
arch/riscv/cpu/cpu.c | 71 +++++++++++++-----------------------------
arch/riscv/lib/cache.c | 26 +++-------------
2 files changed, 25 insertions(+), 72 deletions(-)

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index f3f9f9f2351..06ecd92b9bc 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -595,55 +595,7 @@ static inline bool supports_extension(char ext)
#if CONFIG_IS_ENABLED(RISCV_MMODE)
return csr_read(CSR_MISA) & (1 << (ext - 'a'));
#elif CONFIG_CPU
- char sext[2] = {ext};
- struct udevice *dev;
- const char *isa;
- int ret, i;
-
- uclass_find_first_device(UCLASS_CPU, &dev);
- if (!dev) {
- debug("unable to find the RISC-V cpu device\n");
- return false;
- }
-
- ret = dev_read_stringlist_search(dev, "riscv,isa-extensions", sext);
- if (ret >= 0)
- return true;
-
- /*
- * Only if the property is not found (ENODATA) is the fallback to
- * riscv,isa used, otherwise the extension is not present in this
- * CPU.
- */
- if (ret != -ENODATA)
- return false;
-
- isa = dev_read_string(dev, "riscv,isa");
- if (!isa)
- return false;
-
- /*
- * Skip the first 4 characters (rv32|rv64).
- */
- for (i = 4; i < sizeof(isa); i++) {
- switch (isa[i]) {
- case 's':
- case 'x':
- case 'z':
- case '_':
- case '\0':
- /*
- * Any of these characters mean the single
- * letter extensions have all been consumed.
- */
- return false;
- default:
- if (isa[i] == ext)
- return true;
- }
- }
-
- return false;
+ return __riscv_isa_extension_available(ext);
#else /* !CONFIG_CPU */
#warning "There is no way to determine the available extensions in S-mode."
#warning "Please convert your board to use the RISC-V CPU driver."
@@ -679,7 +631,26 @@ static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1)

int riscv_cpu_setup(void)
{
- int __maybe_unused ret;
+ int ret = -ENODEV, ext_count, i;
+ const char *isa, **exts;
+ struct udevice *dev;
+
+ uclass_find_first_device(UCLASS_CPU, &dev);
+ if (!dev) {
+ debug("unable to find the RISC-V cpu device\n");
+ return ret;
+ }
+
+ ext_count = dev_read_string_list(dev, "riscv,isa-extensions", &exts);
+ if (ext_count > 0) {
+ for (i = 0; i < ext_count; i++)
+ match_isa_ext(exts[i], exts[i] + strlen(exts[i]));
+ } else {
+ isa = dev_read_string(dev, "riscv,isa");
+ if (!isa)
+ return ret;
+ riscv_parse_isa_string(isa);
+ }

/* Enable FPU */
if (supports_extension('d') || supports_extension('f')) {
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index e184d5e2059..71e4937ab54 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -24,7 +24,7 @@ enum {
CBO_INVAL
} riscv_cbo_ops;
static int zicbom_block_size;
-
+extern unsigned int riscv_get_cbom_block_size(void);
static inline void do_cbo_clean(unsigned long base)
{
asm volatile ("add a0, %0, zero\n" CBO_CLEAN(%0) ::
@@ -79,25 +79,6 @@ void cbo_inval(unsigned long start, unsigned long end)
cbo_op(CBO_INVAL, start, end);
}

-static int riscv_zicbom_init(void)
-{
- struct udevice *dev;
-
- if (!CONFIG_IS_ENABLED(RISCV_ISA_ZICBOM) || zicbom_block_size)
- return 1;
-
- uclass_first_device(UCLASS_CPU, &dev);
- if (!dev) {
- log_debug("Failed to get cpu device!\n");
- return 0;
- }
-
- if (dev_read_u32(dev, "riscv,cbom-block-size", &zicbom_block_size))
- log_debug("riscv,cbom-block-size DT property not present\n");
-
- return zicbom_block_size;
-}
-
void invalidate_icache_all(void)
{
asm volatile ("fence.i" ::: "memory");
@@ -166,6 +147,7 @@ __weak int dcache_status(void)

__weak void enable_caches(void)
{
- if (!riscv_zicbom_init())
- log_info("Zicbom not initialized.\n");
+ zicbom_block_size = riscv_get_cbom_block_size();
+ if (!zicbom_block_size)
+ log_debug("Zicbom not initialized.\n");
}
--
2.34.1