[PATCH] Kconfig: Add a default cache line size for RISC-V

[Yu-Chien Peter Lin <peter.lin@sifive.com>]

Some RISC-V platforms do not define the d-cache line size
through SYS_CACHE_SHIFT_n. Set a default value of 64 bytes
for such cases.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
---
This patch resolves compilation errors that occurs when
the TEE driver is enabled:

  drivers/tee/tee-uclass.c:247:41: error: 'CONFIG_SYS_CACHELINE_SIZE' undeclared (first use in this function); did you mean 'CONFIG_SYS_CBSIZE'?
    247 |                                         CONFIG_SYS_CACHELINE_SIZE);
        |                                         ^~~~~~~~~~~~~~~~~~~~~~~~~ 
  drivers/tee/optee/core.c: In function 'flush_shm_dcache':
  drivers/tee/optee/core.c:505:50: error: 'CONFIG_SYS_CACHELINE_SIZE' undeclared (first use in this function); did you mean 'CONFIG_SYS_CBSIZE'?
    505 |         flush_dcache_range(rounddown((ulong)arg, CONFIG_SYS_CACHELINE_SIZE),
        |                                                  ^~~~~~~~~~~~~~~~~~~~~~~~~
---
 arch/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/Kconfig b/arch/Kconfig
index bb2e7bedd10..b0190b1f415 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -52,7 +52,8 @@ config SYS_CACHELINE_SIZE
 	default 64 if SYS_CACHE_SHIFT_6
 	default 32 if SYS_CACHE_SHIFT_5
 	default 16 if SYS_CACHE_SHIFT_4
-	# Fall-back for MIPS
+	# Fall-back for MIPS and RISC-V
+	default 64 if RISCV
 	default 32 if MIPS
 
 config LINKER_LIST_ALIGN
-- 
2.39.3