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[79.144.185.233]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec169b4e4sm125815155e9.20.2025.04.07.01.19.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 01:19:35 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez@oss.qualcomm.com, caleb.connolly@linaro.org, neil.armstrong@linaro.org, sumit.garg@kernel.org Cc: u-boot-qcom@groups.io, u-boot@lists.denx.de Subject: [PATCH 3/7] mmc: msm_sdhci: handle bulk clock initialization error Date: Mon, 7 Apr 2025 10:19:23 +0200 Message-Id: <20250407081927.138915-4-jorge.ramirez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250407081927.138915-1-jorge.ramirez@oss.qualcomm.com> References: <20250407081927.138915-1-jorge.ramirez@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: ny6E7N7_kVRG_oXMs5p8WLoQMu3aT4Ic X-Authority-Analysis: v=2.4 cv=QuVe3Uyd c=1 sm=1 tr=0 ts=67f38a98 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=9rMOtB7ueBl8bWGkC6audQ==:17 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=l6OA150-fj_NnAz7gf0A:9 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-GUID: ny6E7N7_kVRG_oXMs5p8WLoQMu3aT4Ic X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-07_02,2025-04-03_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 bulkscore=0 priorityscore=1501 clxscore=1015 phishscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504070058 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Some boards do not require all clocks to be available (i.e: dragonboard820c). This change provides a fallback to the core clock when the bulk cant be retrived. Signed-off-by: Jorge Ramirez-Ortiz --- drivers/mmc/msm_sdhci.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 27bb7052fca..8081330bd25 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -56,6 +57,17 @@ struct msm_sdhc_variant_info { DECLARE_GLOBAL_DATA_PTR; +static int get_core_clock(struct udevice *dev, struct clk_bulk *bulk) +{ + bulk->count = 1; + + bulk->clks = devm_kcalloc(dev, 1, sizeof(struct clk), GFP_KERNEL); + if (!bulk->clks) + return -ENOMEM; + + return clk_get_by_name(dev, "core", &bulk->clks[0]); +} + static int msm_sdc_clk_init(struct udevice *dev) { struct msm_sdhc *prv = dev_get_priv(dev); @@ -73,8 +85,15 @@ static int msm_sdc_clk_init(struct udevice *dev) ret = clk_get_bulk(dev, &prv->clks); if (ret) { - log_warning("Couldn't get mmc clocks: %d\n", ret); - return ret; + log_warning("Bulk clocks not available (%d), trying core clock\n", ret); + + /* Sometimes not all clocks are needed - chainloading uboot */ + ret = get_core_clock(dev, &prv->clks); + if (ret) { + log_warning("Core clock not available:(%d)\n", ret); + return ret; + } + n_clks = 1; } ret = clk_enable_bulk(&prv->clks); @@ -83,6 +102,9 @@ static int msm_sdc_clk_init(struct udevice *dev) return ret; } + if (n_clks == 1) + goto set_rate; + /* If clock-names is unspecified, then the first clock is the core clock */ if (!ofnode_get_property(node, "clock-names", &n_clks)) { if (!clk_set_rate(&prv->clks.clks[0], clk_rate)) { @@ -105,6 +127,7 @@ static int msm_sdc_clk_init(struct udevice *dev) return -EINVAL; } +set_rate: /* The clock is already enabled by the clk_bulk above */ clk_rate = clk_set_rate(&prv->clks.clks[i], clk_rate); /* If we get a rate of 0 then something has probably gone wrong. */ -- 2.34.1