[PATCH 3/4] mtd: nand: Add support for EDO mode 1-5 to IMX6ULL platform

[Michael Trimarchi <michael@amarulasolutions.com>]

The clock driver allow to burst the performance of the nand
controller. Make changes to let it use the new clock driver

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
---

 drivers/mtd/nand/raw/mxs_nand.c    | 12 ++++++++++++
 drivers/mtd/nand/raw/mxs_nand_dt.c |  2 +-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c
index 80d9307cdd1..2679b6ab650 100644
--- a/drivers/mtd/nand/raw/mxs_nand.c
+++ b/drivers/mtd/nand/raw/mxs_nand.c
@@ -1507,8 +1507,20 @@ static void mxs_compute_timings(struct nand_chip *chip,
 	writel(GPMI_CTRL1_CLEAR_MASK, &nand_info->gpmi_regs->hw_gpmi_ctrl1_clr);
 	writel(ctrl1n, &nand_info->gpmi_regs->hw_gpmi_ctrl1_set);
 
+	/* Clock dividers do NOT guarantee a clean clock signal on its output
+	 * during the change of the divide factor on i.MX6Q/UL/SX. On i.MX7/8,
+	 * all clock dividers provide these guarantee.
+	 */
+	if (IS_ENABLED(CONFIG_MX6ULL)) {
+		clk_disable(nand_info->gpmi_clk);
+	}
+
 	clk_set_rate(nand_info->gpmi_clk, clk_rate);
 
+	if (IS_ENABLED(CONFIG_MX6ULL)) {
+		clk_enable(nand_info->gpmi_clk);
+	}
+
 	/* Wait 64 clock cycles before using the GPMI after enabling the DLL */
 	dll_wait_time_us = USEC_PER_SEC / clk_rate * 64;
 	if (!dll_wait_time_us)
diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c b/drivers/mtd/nand/raw/mxs_nand_dt.c
index b62474bc5ab..90eefa2558d 100644
--- a/drivers/mtd/nand/raw/mxs_nand_dt.c
+++ b/drivers/mtd/nand/raw/mxs_nand_dt.c
@@ -99,7 +99,7 @@ static int mxs_nand_dt_probe(struct udevice *dev)
 	info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc");
 
 	if (IS_ENABLED(CONFIG_CLK) &&
-	    (IS_ENABLED(CONFIG_IMX8) || IS_ENABLED(CONFIG_IMX8M))) {
+	    (IS_ENABLED(CONFIG_IMX8) || IS_ENABLED(CONFIG_IMX8M) || IS_ENABLED(CONFIG_MX6ULL))) {
 		struct clk_bulk clk_bulk;
 		info->gpmi_clk = devm_clk_get(dev, "gpmi_io");
 
-- 
2.43.0

base-commit: df2ed552f0b05591090369a7fe7ddc92439dea5c