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Wed, 28 May 2025 20:31:06 -0700 (PDT) Received: from localhost.localdomain ([223.228.139.23]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-b2d9872cca0sm1847252a12.15.2025.05.28.20.31.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 20:31:06 -0700 (PDT) From: Mayuresh Chitale To: trini@konsulko.com Cc: Mayuresh Chitale , u-boot@lists.denx.de Subject: [PATCH] Revert "riscv: image: Add new image type for RV64" Date: Thu, 29 May 2025 03:30:51 +0000 Message-ID: <20250529033052.399573-3-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250529033052.399573-1-mchitale@ventanamicro.com> References: <20250529033052.399573-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This reverts commit 14a4792a71db3561bea065415ac1f2ac69ef32b5 as discussed in [1]. [1] https://lists.denx.de/pipermail/u-boot/2025-May/590841.html Signed-off-by: Mayuresh Chitale --- boot/image.c | 3 +-- include/image.h | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/boot/image.c b/boot/image.c index 45299a7dc33..139c5bd035a 100644 --- a/boot/image.c +++ b/boot/image.c @@ -92,8 +92,7 @@ static const table_entry_t uimage_arch[] = { { IH_ARCH_ARC, "arc", "ARC", }, { IH_ARCH_X86_64, "x86_64", "AMD x86_64", }, { IH_ARCH_XTENSA, "xtensa", "Xtensa", }, - { IH_ARCH_RISCV, "riscv", "RISC-V 32 Bit",}, - { IH_ARCH_RISCV64, "riscv64", "RISC-V 64 Bit",}, + { IH_ARCH_RISCV, "riscv", "RISC-V", }, { -1, "", "", }, }; diff --git a/include/image.h b/include/image.h index 4620782c069..c1db8383459 100644 --- a/include/image.h +++ b/include/image.h @@ -138,8 +138,7 @@ enum { IH_ARCH_ARC, /* Synopsys DesignWare ARC */ IH_ARCH_X86_64, /* AMD x86_64, Intel and Via */ IH_ARCH_XTENSA, /* Xtensa */ - IH_ARCH_RISCV, /* RISC-V 32 bit*/ - IH_ARCH_RISCV64, /* RISC-V 64 bit*/ + IH_ARCH_RISCV, /* RISC-V */ IH_ARCH_COUNT, }; -- 2.43.0