From: Yixun Lan <dlan@gentoo.org>
To: Yao Zi <ziyao@disroot.org>
Cc: Rick Chen <rick@andestech.com>, Leo <ycliang@andestech.com>,
Tom Rini <trini@konsulko.com>,
"Chia-Wei, Wang" <chiawei_wang@aspeedtech.com>,
Simon Glass <sjg@chromium.org>,
u-boot@lists.denx.de
Subject: Re: [PATCH 1/2] riscv: Add Kconfig options to distinguish Zaamo and Zalrsc
Date: Sun, 3 Aug 2025 09:24:22 +0800 [thread overview]
Message-ID: <20250803012422-GYA937575@gentoo> (raw)
In-Reply-To: <20250802092155.40915-2-ziyao@disroot.org>
Hi Yao,
On 09:21 Sat 02 Aug , Yao Zi wrote:
> Ratified on Apr. 2024, the original RISC-V "A" extension is now split
> into two separate extensions, "Zaamo" for atomic operations and "Zalrsc"
> for load-reserved/store-conditional instructions.
>
> For now, we've already seen real-world designs implement the Zalrsc
> extension only[2]. As U-Boot mainly runs with only one HART, we could
> easily support these designs by not using AMO instructions in the
> hard-written assembly if necessary, for which this patch introduces two
> new Kconfig options to indicate the availability of "Zaamo" and "Zalrsc".
>
> Note that even with this patch, "A" extension is specified in the ISA
> string passed to the compiler as long as one of "Zaamo" or "Zalrsc" is
> available, since they're only recognized with a quite recent version of
> GCC/Clang. The compiler usually doesn't automatically generate atomic
> instructions unless the source explicitly instructs it to do so, thus
> this should be safe.
>
> Link: https://github.com/riscv/riscv-zaamo-zalrsc/commit/d94c64c63e9120d56bdeb540caf2e5dae60a8126 # [1]
> Link: https://lore.kernel.org/u-boot/20250729162035.209849-9-uros.stajic@htecgroup.com/ # [2]
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
> arch/riscv/Kconfig | 17 +++++++++++++++++
> arch/riscv/Makefile | 7 ++++++-
> configs/ibex-ast2700_defconfig | 3 ++-
> 3 files changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 8c6feae5735..b1c2d657e99 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -339,10 +339,27 @@ endmenu
>
> config RISCV_ISA_A
> bool "Standard extension for Atomic Instructions"
> + depends on RISCV_ISA_ZAAMO && RISCV_ISA_ZALRSC
> default y
> help
> Adds "A" to the ISA string passed to the compiler.
>
> +config RISCV_ISA_ZAAMO
> + bool "Standard extension for Atomic Memory Operations"
> + default y
> + help
> + Indicates the platform supports Zaamo extension for atomic memory
> + operations. Assembly routines won't use AMO instructions if set
> + to n.
> +
> +config RISCV_ISA_ZALRSC
> + bool "Standard extension for LR/SC instructions"
> + default y
> + help
> + Indicates the platform supports Zalrsc extension for load-reserved
> + and store-conditional instructions. Assembly rutines won't use
> + LR/SC instructions if set to n.
> +
> config RISCV_ISA_ZICBOM
> bool "Zicbom support"
> depends on !SYS_DISABLE_DCACHE_OPS
> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> index 6f80f4a7108..fdda6da1df3 100644
> --- a/arch/riscv/Makefile
> +++ b/arch/riscv/Makefile
> @@ -11,7 +11,12 @@ ifeq ($(CONFIG_ARCH_RV32I),y)
> ARCH_BASE = rv32im
> ABI_BASE = ilp32
> endif
> -ifeq ($(CONFIG_RISCV_ISA_A),y)
> +# GCC starts to recognize "Zaamo" and "Zalrsc" from version 15, which is quite
> +# recent. We don't bother checking the exact compiler version, but pass "A"
> +# extension for -march as long as one of "Zaamo" or "Zalrsc" is available.
> +ifeq ($(findstring y,$(CONFIG_RISCV_ISA_A) \
> + $(CONFIG_RISCV_ISA_ZAAMO) \
> + $(CONFIG_RISCV_ISA_ZALRSC)),y)
> ARCH_A = a
> endif
> ifeq ($(CONFIG_RISCV_ISA_F),y)
> diff --git a/configs/ibex-ast2700_defconfig b/configs/ibex-ast2700_defconfig
> index f088aec8716..eb5cab43645 100644
> --- a/configs/ibex-ast2700_defconfig
> +++ b/configs/ibex-ast2700_defconfig
> @@ -23,7 +23,8 @@ CONFIG_SYS_MEM_TOP_HIDE=0x10000000
> CONFIG_BUILD_TARGET=""
> CONFIG_TARGET_ASPEED_AST2700_IBEX=y
> # CONFIG_RISCV_ISA_F is not set
> -# CONFIG_RISCV_ISA_A is not set
> +# CONFIG_RISCV_ISA_ZAAMO is not set
> +# CONFIG_RISCV_ISA_ZALRSC is not set
this is confusing, while in this patchset it actually equal to :
# CONFIG_RISCV_ISA_ZAAMO is not set
CONFIG_RISCV_ISA_ZALRSC=y
also I believe changes for configs/ibex-ast2700_defconfig should go as
an independent patch, please separate it
> # CONFIG_SPL_SMP is not set
> CONFIG_XIP=y
> CONFIG_SPL_XIP=y
> --
> 2.50.1
>
--
Yixun Lan (dlan)
next prev parent reply other threads:[~2025-08-03 1:24 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-02 9:21 [PATCH 0/2] Support SMP on RISC-V cores with Zalrsc only Yao Zi
2025-08-02 9:21 ` [PATCH 1/2] riscv: Add Kconfig options to distinguish Zaamo and Zalrsc Yao Zi
2025-08-02 23:59 ` Yixun Lan
2025-08-03 0:16 ` Yao Zi
2025-08-03 1:24 ` Yixun Lan [this message]
2025-08-03 3:28 ` Yao Zi
2025-08-02 9:21 ` [PATCH 2/2] riscv: Add a Zalrsc-only alternative for synchronization in start.S Yao Zi
2025-08-03 1:21 ` Yixun Lan
2025-08-03 3:53 ` Yao Zi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250803012422-GYA937575@gentoo \
--to=dlan@gentoo.org \
--cc=chiawei_wang@aspeedtech.com \
--cc=rick@andestech.com \
--cc=sjg@chromium.org \
--cc=trini@konsulko.com \
--cc=u-boot@lists.denx.de \
--cc=ycliang@andestech.com \
--cc=ziyao@disroot.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox