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Thu, 07 Aug 2025 00:45:57 -0700 (PDT) Received: from localhost.localdomain ([218.90.41.167]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-320f4909b8bsm16809202a91.16.2025.08.07.00.45.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Aug 2025 00:45:57 -0700 (PDT) From: WeiHao Li To: u-boot@lists.denx.de Cc: antonio.borneo@foss.st.com, mk7.kang@samsung.com, gregkh@linuxfoundation.org, semen.protsenko@linaro.org, mikhail.kshevetskiy@iopsys.eu, bb@ti.com, justin.swartz@risingedge.co.za, lukasz.czechowski@thaumatec.com, robh@kernel.org, tharvey@gateworks.com, clement.legoffic@foss.st.com, marek.vasut@mailbox.org, dinesh.maniyam@altera.com, patrice.chotard@foss.st.com, festevam@gmail.com, jerome.forissier@linaro.org, quentin.schulz@cherry.de, andrew.goodbody@linaro.org, sumit.garg@kernel.org, ag.dev.uboot@gmail.com, rfried.dev@gmail.com, joe.hershberger@ni.com, jh80.chung@samsung.com, peng.fan@nxp.com, seanga2@gmail.com, lukma@denx.de, kever.yang@rock-chips.com, philipp.tomsich@vrull.eu, sjg@chromium.org, trini@konsulko.com, WeiHao Li , WeiHao Li Subject: [PATCH 04/10] clk: rockchip: rk3368: Add bus clk get/set Date: Thu, 7 Aug 2025 15:44:12 +0800 Message-Id: <20250807074419.336752-5-cn.liweihao@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250807074419.336752-1-cn.liweihao@gmail.com> References: <20250807074419.336752-1-cn.liweihao@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Thu, 07 Aug 2025 10:26:22 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Patch get form Rockchip downstream uboot repository. Signed-off-by: WeiHao Li --- .../include/asm/arch-rockchip/cru_rk3368.h | 60 ++++++++++++ drivers/clk/rockchip/clk_rk3368.c | 94 +++++++++++++++++++ 2 files changed, 154 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h index ed2a612185..29f90454d4 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h @@ -80,6 +80,49 @@ enum { PLL_RESET = 1, PLL_RESET_MASK = GENMASK(5, 5), + /* CLKSEL1CON */ + CORE_ACLK_DIV_SHIFT = 0, + CORE_ACLK_DIV_MASK = 0x1f << CORE_ACLK_DIV_SHIFT, + CORE_DBG_DIV_SHIFT = 8, + CORE_DBG_DIV_MASK = 0x1f << CORE_DBG_DIV_SHIFT, + + CORE_CLK_PLL_SEL_SHIFT = 7, + CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, + CORE_CLK_PLL_SEL_APLL = 0, + CORE_CLK_PLL_SEL_GPLL, + CORE_DIV_CON_SHIFT = 0, + CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, + + /* CLKSEL8CON */ + PCLK_BUS_DIV_CON_SHIFT = 12, + PCLK_BUS_DIV_CON_MASK = 0x7 << PCLK_BUS_DIV_CON_SHIFT, + HCLK_BUS_DIV_CON_SHIFT = 8, + HCLK_BUS_DIV_CON_MASK = 0x3 << HCLK_BUS_DIV_CON_SHIFT, + CLK_BUS_PLL_SEL_CPLL = 0, + CLK_BUS_PLL_SEL_GPLL = 1, + CLK_BUS_PLL_SEL_SHIFT = 7, + CLK_BUS_PLL_SEL_MASK = 1 << CLK_BUS_PLL_SEL_SHIFT, + ACLK_BUS_DIV_CON_SHIFT = 0, + ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT, + + /* CLKSEL9CON */ + PCLK_PERI_DIV_CON_SHIFT = 12, + PCLK_PERI_DIV_CON_MASK = 0x3 << PCLK_PERI_DIV_CON_SHIFT, + HCLK_PERI_DIV_CON_SHIFT = 8, + HCLK_PERI_DIV_CON_MASK = 3 << HCLK_PERI_DIV_CON_SHIFT, + CLK_PERI_PLL_SEL_CPLL = 0, + CLK_PERI_PLL_SEL_GPLL, + CLK_PERI_PLL_SEL_SHIFT = 7, + CLK_PERI_PLL_SEL_MASK = 1 << CLK_PERI_PLL_SEL_SHIFT, + ACLK_PERI_DIV_CON_SHIFT = 0, + ACLK_PERI_DIV_CON_MASK = 0x1f, + + /* CLKSEL10CON */ + CLK_CRYPTO_DIV_CON_SHIFT = 14, + CLK_CRYPTO_DIV_CON_MASK = 0x3 << CLK_CRYPTO_DIV_CON_SHIFT, + PCLK_ALIVE_DIV_CON_SHIFT = 8, + PCLK_ALIVE_DIV_CON_MASK = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT, + /* CLKSEL12_CON */ MCU_STCLK_DIV_SHIFT = 8, MCU_STCLK_DIV_MASK = GENMASK(10, 8), @@ -90,6 +133,23 @@ enum { MCU_CLK_DIV_SHIFT = 0, MCU_CLK_DIV_MASK = GENMASK(4, 0), + /* CLKSEL19_CON */ + ACLK_VOP_PLL_SEL_SHIFT = 6, + ACLK_VOP_PLL_SEL_MASK = GENMASK(7, 6), + ACLK_VOP_PLL_SEL_CPLL = 0, + ACLK_VOP_PLL_SEL_GPLL = 1, + ACLK_VOP_DIV_SHIFT = 0, + ACLK_VOP_DIV_MASK = GENMASK(4, 0), + + /* CLKSEL20_CON */ + DCLK_VOP_PLL_SEL_SHIFT = 8, + DCLK_VOP_PLL_SEL_MASK = GENMASK(9, 8), + DCLK_VOP_PLL_SEL_CPLL = 0, + DCLK_VOP_PLL_SEL_GPLL = 1, + DCLK_VOP_PLL_SEL_NPLL = 2, + DCLK_VOP_DIV_SHIFT = 0, + DCLK_VOP_DIV_MASK = GENMASK(7, 0), + /* CLKSEL_CON25 */ CLK_SARADC_DIV_CON_SHIFT = 8, CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 6691801384..aba7f2cd47 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -451,6 +451,82 @@ static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz) return rk3368_saradc_get_clk(cru); } +#if !IS_ENABLED(CONFIG_XPL_BUILD) +static ulong rk3368_bus_get_clk(struct rk3368_cru *cru, ulong clk_id) +{ + u32 div, con, parent; + + switch (clk_id) { + case ACLK_BUS: + con = readl(&cru->clksel_con[8]); + div = (con & ACLK_BUS_DIV_CON_MASK) >> ACLK_BUS_DIV_CON_SHIFT; + parent = rkclk_pll_get_rate(cru, GPLL); + break; + case HCLK_BUS: + con = readl(&cru->clksel_con[8]); + div = (con & HCLK_BUS_DIV_CON_MASK) >> HCLK_BUS_DIV_CON_SHIFT; + parent = rk3368_bus_get_clk(cru, ACLK_BUS); + break; + case PCLK_BUS: + case PCLK_PWM0: + case PCLK_PWM1: + case PCLK_I2C0: + case PCLK_I2C1: + con = readl(&cru->clksel_con[8]); + div = (con & PCLK_BUS_DIV_CON_MASK) >> PCLK_BUS_DIV_CON_SHIFT; + parent = rk3368_bus_get_clk(cru, ACLK_BUS); + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(parent, div); +} + +static ulong rk3368_bus_set_clk(struct rk3368_cru *cru, + ulong clk_id, ulong hz) +{ + int src_clk_div; + + /* + * select gpll as pd_bus bus clock source and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + switch (clk_id) { + case ACLK_BUS: + src_clk_div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, GPLL), hz); + assert(src_clk_div - 1 < 31); + rk_clrsetreg(&cru->clksel_con[8], + CLK_BUS_PLL_SEL_MASK | ACLK_BUS_DIV_CON_MASK, + CLK_BUS_PLL_SEL_GPLL << CLK_BUS_PLL_SEL_SHIFT | + (src_clk_div - 1) << ACLK_BUS_DIV_CON_SHIFT); + break; + case HCLK_BUS: + src_clk_div = DIV_ROUND_UP(rk3368_bus_get_clk(cru, + ACLK_BUS), + hz); + assert(src_clk_div - 1 < 3); + rk_clrsetreg(&cru->clksel_con[8], + HCLK_BUS_DIV_CON_MASK, + (src_clk_div - 1) << HCLK_BUS_DIV_CON_SHIFT); + break; + case PCLK_BUS: + src_clk_div = DIV_ROUND_UP(rk3368_bus_get_clk(cru, + ACLK_BUS), + hz); + assert(src_clk_div - 1 < 3); + rk_clrsetreg(&cru->clksel_con[8], + PCLK_BUS_DIV_CON_MASK, + (src_clk_div - 1) << PCLK_BUS_DIV_CON_SHIFT); + break; + default: + printf("do not support this bus freq\n"); + return -EINVAL; + } + return rk3368_bus_get_clk(cru, clk_id); +} +#endif + static ulong rk3368_clk_get_rate(struct clk *clk) { struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); @@ -467,6 +543,17 @@ static ulong rk3368_clk_get_rate(struct clk *clk) case SCLK_SPI0 ... SCLK_SPI2: rate = rk3368_spi_get_clk(priv->cru, clk->id); break; +#if !IS_ENABLED(CONFIG_XPL_BUILD) + case ACLK_BUS: + case HCLK_BUS: + case PCLK_BUS: + case PCLK_PWM0: + case PCLK_PWM1: + case PCLK_I2C0: + case PCLK_I2C1: + rate = rk3368_bus_get_clk(priv->cru, clk->id); + break; +#endif #if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC) case HCLK_SDMMC: case HCLK_EMMC: @@ -498,6 +585,13 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) ret = rk3368_ddr_set_clk(priv->cru, rate); break; #endif +#if !IS_ENABLED(CONFIG_XPL_BUILD) + case ACLK_BUS: + case HCLK_BUS: + case PCLK_BUS: + rate = rk3368_bus_set_clk(priv->cru, clk->id, rate); + break; +#endif #if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC) case HCLK_SDMMC: case HCLK_EMMC: -- 2.39.5