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Thu, 14 Aug 2025 06:13:45 -0700 (PDT) Received: from localhost.localdomain ([104.28.159.212]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-24300f8c9d1sm67902195ad.129.2025.08.14.06.13.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Aug 2025 06:13:45 -0700 (PDT) From: WeiHao Li To: u-boot@lists.denx.de Cc: trini@konsulko.com, sjg@chromium.org, philipp.tomsich@vrull.eu, kever.yang@rock-chips.com, lukma@denx.de, seanga2@gmail.com, ag.dev.uboot@gmail.com, muratdemirtaseu@outlook.com, WeiHao Li Subject: [PATCH 5/5] video: rockchip: add RK3368 VOP support Date: Thu, 14 Aug 2025 21:12:37 +0800 Message-Id: <20250814131237.8135-6-cn.liweihao@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250814131237.8135-1-cn.liweihao@gmail.com> References: <20250814131237.8135-1-cn.liweihao@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This patch adds RK3368 VOP driver based on RK3288. I got its GRF register user manual from a online forum. Link: https://github.com/ieiao/wiki/blob/master/docs/embedded-dev/rockchip/rk3368/Rockchip_RK3368_GRF.pdf Signed-off-by: WeiHao Li --- drivers/video/rockchip/Makefile | 1 + drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 20 +++++ drivers/video/rockchip/rk3368_vop.c | 79 +++++++++++++++++++ 3 files changed, 100 insertions(+) create mode 100644 drivers/video/rockchip/rk3368_vop.c diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile index f55beceeb..83c0b7aef 100644 --- a/drivers/video/rockchip/Makefile +++ b/drivers/video/rockchip/Makefile @@ -7,6 +7,7 @@ ifdef CONFIG_VIDEO_ROCKCHIP obj-y += rk_vop.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288_vop.o obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328_vop.o +obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368_vop.o obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c index fa5121735..122974d60 100644 --- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c +++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c @@ -134,6 +134,11 @@ #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) #define DW_MIPI_NEEDS_GRF_CLK BIT(1) +#define RK3368_GRF_SOC_CON7 0x41c +#define RK3368_DSI_FORCETXSTOPMODE (0xf << 7) +#define RK3368_DSI_FORCERXMODE (0x1 << 6) +#define RK3368_DSI_TURNDISABLE (0x1 << 5) + #define RK3399_GRF_SOC_CON20 0x6250 #define RK3399_DSI0_LCDC_SEL BIT(0) #define RK3399_DSI1_LCDC_SEL BIT(4) @@ -911,6 +916,18 @@ struct video_bridge_ops dw_mipi_dsi_rockchip_ops = { .set_backlight = dw_mipi_dsi_rockchip_set_bl, }; +static const struct rockchip_dw_dsi_chip_data rk3368_chip_data[] = { + { + .reg = 0xff960000, + .lanecfg1_grf_reg = RK3368_GRF_SOC_CON7, + .lanecfg1 = HIWORD_UPDATE(0, RK3368_DSI_TURNDISABLE | + RK3368_DSI_FORCETXSTOPMODE | + RK3368_DSI_FORCERXMODE), + .max_data_lanes = 4, + }, + { /* sentinel */ } +}; + static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { { .reg = 0xff960000, @@ -980,6 +997,9 @@ static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { }; static const struct udevice_id dw_mipi_dsi_rockchip_dt_ids[] = { + { .compatible = "rockchip,rk3368-mipi-dsi", + .data = (long)&rk3368_chip_data, + }, { .compatible = "rockchip,rk3399-mipi-dsi", .data = (long)&rk3399_chip_data, }, diff --git a/drivers/video/rockchip/rk3368_vop.c b/drivers/video/rockchip/rk3368_vop.c new file mode 100644 index 000000000..b4aac51c5 --- /dev/null +++ b/drivers/video/rockchip/rk3368_vop.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Author(s): WeiHao Li + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk_vop.h" + +DECLARE_GLOBAL_DATA_PTR; + +static void rk3368_set_pin_polarity(struct udevice *dev, + enum vop_modes mode, u32 polarity) +{ + struct rk_vop_priv *priv = dev_get_priv(dev); + struct rk3288_vop *regs = priv->regs; + + /* The RK3368 VOP (v3.2) has its polarity configuration in ctrl0 */ + clrsetbits_le32(®s->dsp_ctrl0, + M_DSP_DCLK_POL | M_DSP_DEN_POL | + M_DSP_VSYNC_POL | M_DSP_HSYNC_POL, + V_DSP_PIN_POL(polarity)); +} + +/* + * Try some common regulators. We should really get these from the + * device tree somehow. + */ +static const char * const rk3368_regulator_names[] = { + "vcc18_lcd", + "VCC18_LCD", + "vdd10_lcd_pwren_h", + "vdd10_lcd", + "VDD10_LCD", + "vcc33_lcd" +}; + +static int rk3368_vop_probe(struct udevice *dev) +{ + /* Before relocation we don't need to do anything */ + if (!(gd->flags & GD_FLG_RELOC)) + return 0; + + /* Probe regulators required for the RK3368 VOP */ + rk_vop_probe_regulators(dev, rk3368_regulator_names, + ARRAY_SIZE(rk3368_regulator_names)); + + return rk_vop_probe(dev); +} + +struct rkvop_driverdata rk3368_driverdata = { + .set_pin_polarity = rk3368_set_pin_polarity, +}; + +static const struct udevice_id rk3368_vop_ids[] = { + { .compatible = "rockchip,rk3368-vop", + .data = (ulong)&rk3368_driverdata }, + { } +}; + +static const struct video_ops rk3368_vop_ops = { +}; + +U_BOOT_DRIVER(rockchip_rk3368_vop) = { + .name = "rockchip_rk3368_vop", + .id = UCLASS_VIDEO, + .of_match = rk3368_vop_ids, + .ops = &rk3368_vop_ops, + .bind = rk_vop_bind, + .probe = rk3368_vop_probe, + .priv_auto = sizeof(struct rk_vop_priv), +}; -- 2.39.5