* [PATCH v3 1/4] riscv: dts: starfive: prune redundant jh7110-common overrides
2025-09-17 0:02 [PATCH v3 0/4] riscv: dts: starfive: prune redundant jh7110-common E Shattow
@ 2025-09-17 0:02 ` E Shattow
2025-09-19 10:51 ` Leo Liang
2025-09-17 0:02 ` [PATCH v3 2/4] riscv: dts: starfive: sync visionfive2 overrides with upstream Linux for-next E Shattow
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: E Shattow @ 2025-09-17 0:02 UTC (permalink / raw)
To: Rick Chen, Leo, Minda Chen, Hal Feng, Tom Rini
Cc: u-boot, E Shattow, Heinrich Schuchardt
Prune jh7110-common-u-boot.dtsi (clocks, qspi flash, eeprom, and
bootph-pre-ram hints now upstream since devicetree-rebasing v6.16).
In preparation for removal of per-dts jh7110-*-u-boot.dtsi replace include
by next dependency jh7110-u-boot.dtsi in automatic dtsi inclusion order.
Signed-off-by: E Shattow <e@freeshell.de>
---
arch/riscv/dts/jh7110-common-u-boot.dtsi | 99 -------------------
.../jh7110-deepcomputing-fml13v01-u-boot.dtsi | 2 +-
arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi | 2 +-
.../dts/jh7110-pine64-star64-u-boot.dtsi | 2 +-
...10-starfive-visionfive-2-v1.2a-u-boot.dtsi | 2 +-
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 2 +-
6 files changed, 5 insertions(+), 104 deletions(-)
delete mode 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi
diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi
deleted file mode 100644
index 049b0a7ce28..00000000000
--- a/arch/riscv/dts/jh7110-common-u-boot.dtsi
+++ /dev/null
@@ -1,99 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2023 StarFive Technology Co., Ltd.
- */
-
-#include "jh7110-u-boot.dtsi"
-/ {
- aliases {
- spi0 = &qspi;
- };
-
- chosen {
- bootph-pre-ram;
- };
-
- firmware {
- spi0 = &qspi;
- bootph-pre-ram;
- };
-
- memory@40000000 {
- bootph-pre-ram;
- };
-};
-
-&uart0 {
- bootph-pre-ram;
- reg-offset = <0>;
- current-speed = <115200>;
-};
-
-&mmc0 {
- bootph-pre-ram;
-};
-
-&mmc1 {
- bootph-pre-ram;
-};
-
-&qspi {
- bootph-pre-ram;
-
- flash@0 {
- bootph-pre-ram;
- cdns,read-delay = <2>;
- spi-max-frequency = <100000000>;
- };
-};
-
-&syscrg {
- assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
- <&syscrg JH7110_SYSCLK_BUS_ROOT>,
- <&syscrg JH7110_SYSCLK_PERH_ROOT>,
- <&syscrg JH7110_SYSCLK_QSPI_REF>;
- assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
- <&pllclk JH7110_PLLCLK_PLL2_OUT>,
- <&pllclk JH7110_PLLCLK_PLL2_OUT>,
- <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
- assigned-clock-rates = <0>, <0>, <0>, <0>;
-};
-
-&sysgpio {
- bootph-pre-ram;
-};
-
-&mmc0_pins {
- bootph-pre-ram;
- rst-pins {
- bootph-pre-ram;
- };
-};
-
-&mmc1_pins {
- bootph-pre-ram;
- clk-pins {
- bootph-pre-ram;
- };
-
- mmc-pins {
- bootph-pre-ram;
- };
-};
-
-&i2c5_pins {
- bootph-pre-ram;
- i2c-pins {
- bootph-pre-ram;
- };
-};
-
-&i2c5 {
- bootph-pre-ram;
- eeprom@50 {
- bootph-pre-ram;
- compatible = "atmel,24c04";
- reg = <0x50>;
- pagesize = <16>;
- };
-};
diff --git a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
index ab882d07f6f..b9202f2acce 100644
--- a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
@@ -3,5 +3,5 @@
* Copyright (C) 2024 StarFive Technology Co., Ltd.
*/
-#include "jh7110-common-u-boot.dtsi"
+#include "jh7110-u-boot.dtsi"
#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi
index ab882d07f6f..b9202f2acce 100644
--- a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi
@@ -3,5 +3,5 @@
* Copyright (C) 2024 StarFive Technology Co., Ltd.
*/
-#include "jh7110-common-u-boot.dtsi"
+#include "jh7110-u-boot.dtsi"
#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi
index ab882d07f6f..b9202f2acce 100644
--- a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi
@@ -3,5 +3,5 @@
* Copyright (C) 2024 StarFive Technology Co., Ltd.
*/
-#include "jh7110-common-u-boot.dtsi"
+#include "jh7110-u-boot.dtsi"
#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
index ab882d07f6f..b9202f2acce 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
@@ -3,5 +3,5 @@
* Copyright (C) 2024 StarFive Technology Co., Ltd.
*/
-#include "jh7110-common-u-boot.dtsi"
+#include "jh7110-u-boot.dtsi"
#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
index 874074174ff..848ed8225ac 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
@@ -3,5 +3,5 @@
* Copyright (C) 2023 StarFive Technology Co., Ltd.
*/
-#include "jh7110-common-u-boot.dtsi"
+#include "jh7110-u-boot.dtsi"
#include "starfive-visionfive2-binman.dtsi"
--
2.50.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v3 1/4] riscv: dts: starfive: prune redundant jh7110-common overrides
2025-09-17 0:02 ` [PATCH v3 1/4] riscv: dts: starfive: prune redundant jh7110-common overrides E Shattow
@ 2025-09-19 10:51 ` Leo Liang
0 siblings, 0 replies; 10+ messages in thread
From: Leo Liang @ 2025-09-19 10:51 UTC (permalink / raw)
To: E Shattow
Cc: Rick Chen, Minda Chen, Hal Feng, Tom Rini, u-boot,
Heinrich Schuchardt
On Tue, Sep 16, 2025 at 05:02:22PM -0700, E Shattow wrote:
> Prune jh7110-common-u-boot.dtsi (clocks, qspi flash, eeprom, and
> bootph-pre-ram hints now upstream since devicetree-rebasing v6.16).
>
> In preparation for removal of per-dts jh7110-*-u-boot.dtsi replace include
> by next dependency jh7110-u-boot.dtsi in automatic dtsi inclusion order.
>
> Signed-off-by: E Shattow <e@freeshell.de>
> ---
> arch/riscv/dts/jh7110-common-u-boot.dtsi | 99 -------------------
> .../jh7110-deepcomputing-fml13v01-u-boot.dtsi | 2 +-
> arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi | 2 +-
> .../dts/jh7110-pine64-star64-u-boot.dtsi | 2 +-
> ...10-starfive-visionfive-2-v1.2a-u-boot.dtsi | 2 +-
> ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 2 +-
> 6 files changed, 5 insertions(+), 104 deletions(-)
> delete mode 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 2/4] riscv: dts: starfive: sync visionfive2 overrides with upstream Linux for-next
2025-09-17 0:02 [PATCH v3 0/4] riscv: dts: starfive: prune redundant jh7110-common E Shattow
2025-09-17 0:02 ` [PATCH v3 1/4] riscv: dts: starfive: prune redundant jh7110-common overrides E Shattow
@ 2025-09-17 0:02 ` E Shattow
2025-09-17 2:59 ` E Shattow
2025-09-19 10:58 ` Leo Liang
2025-09-17 0:02 ` [PATCH v3 3/4] riscv: dts: starfive: visionfive2 depend on SYS_CPU automatic dtsi inclusion E Shattow
2025-09-17 0:02 ` [PATCH v3 4/4] configs: starfive: Use visionfive2 DEVICE_TREE_INCLUDES dtsi named similar to defconfig E Shattow
3 siblings, 2 replies; 10+ messages in thread
From: E Shattow @ 2025-09-17 0:02 UTC (permalink / raw)
To: Rick Chen, Leo, Minda Chen, Hal Feng, Tom Rini
Cc: u-boot, E Shattow, Heinrich Schuchardt
Sync automatic dtsi inclusion overrides for JH7110 CPU with upstream
"riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot
loader" from upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21
Signed-off-by: E Shattow <e@freeshell.de>
---
arch/riscv/dts/jh7110-u-boot.dtsi | 81 ++++++++++++-------------------
1 file changed, 31 insertions(+), 50 deletions(-)
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index f8d13277d24..cc27dd648f8 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -3,36 +3,10 @@
* Copyright (C) 2022 StarFive Technology Co., Ltd.
*/
-#include <dt-bindings/reset/starfive,jh7110-crg.h>
-
-/ {
- timer {
- compatible = "riscv,timer";
- interrupts-extended = <&cpu0_intc 5>,
- <&cpu1_intc 5>,
- <&cpu2_intc 5>,
- <&cpu3_intc 5>,
- <&cpu4_intc 5>;
- };
+// BEGIN "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader"
+// From upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21
- soc {
- bootph-pre-ram;
-
- dmc: dmc@15700000 {
- bootph-pre-ram;
- compatible = "starfive,jh7110-dmc";
- reg = <0x0 0x15700000 0x0 0x10000>,
- <0x0 0x13000000 0x0 0x10000>;
- resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
- <&syscrg JH7110_SYSRST_DDR_OSC>,
- <&syscrg JH7110_SYSRST_DDR_APB>;
- reset-names = "axi", "osc", "apb";
- clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
- clock-names = "pll1_out";
- clock-frequency = <2133>;
- };
- };
-};
+#include <dt-bindings/reset/starfive,jh7110-crg.h>
&clint {
bootph-pre-ram;
@@ -58,22 +32,10 @@
bootph-pre-ram;
};
-&cpus {
- bootph-pre-ram;
-};
-
&osc {
bootph-pre-ram;
};
-&gmac0_rgmii_rxin {
- bootph-pre-ram;
-};
-
-&gmac0_rmii_refin {
- bootph-pre-ram;
-};
-
&gmac1_rgmii_rxin {
bootph-pre-ram;
};
@@ -82,23 +44,42 @@
bootph-pre-ram;
};
-&aoncrg {
- bootph-pre-ram;
+/ {
+ soc {
+ memory-controller@15700000 {
+ compatible = "starfive,jh7110-dmc";
+ reg = <0x0 0x15700000 0x0 0x10000>,
+ <0x0 0x13000000 0x0 0x10000>;
+ bootph-pre-ram;
+ clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+ clock-names = "pll";
+ resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+ <&syscrg JH7110_SYSRST_DDR_OSC>,
+ <&syscrg JH7110_SYSRST_DDR_APB>;
+ reset-names = "axi", "osc", "apb";
+ };
+ };
};
-&pllclk {
+&syscrg {
bootph-pre-ram;
};
-&syscrg {
- assigned-clock-rates = <0>; /* cpufreq not implemented, use defaults */
+&pllclk {
bootph-pre-ram;
};
-&stgcrg {
- bootph-pre-ram;
+// END "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader"
+
+/ {
+ soc {
+ memory-controller@15700000 {
+ clock-frequency = <2133>; /* FIXME: delete property and implement CCF */
+ };
+ };
};
-&sys_syscon {
- bootph-pre-ram;
+&syscrg {
+ assigned-clock-rates = <0>; /* FIXME: delete property and implement cpufreq */
};
+
--
2.50.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v3 2/4] riscv: dts: starfive: sync visionfive2 overrides with upstream Linux for-next
2025-09-17 0:02 ` [PATCH v3 2/4] riscv: dts: starfive: sync visionfive2 overrides with upstream Linux for-next E Shattow
@ 2025-09-17 2:59 ` E Shattow
2025-09-19 10:58 ` Leo Liang
1 sibling, 0 replies; 10+ messages in thread
From: E Shattow @ 2025-09-17 2:59 UTC (permalink / raw)
To: Rick Chen, Leo, Minda Chen, Hal Feng, Tom Rini
Cc: u-boot, Heinrich Schuchardt
On 9/16/25 17:02, E Shattow wrote:
> Sync automatic dtsi inclusion overrides for JH7110 CPU with upstream
> "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot
> loader" from upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21
>
> Signed-off-by: E Shattow <e@freeshell.de>
> ---
> arch/riscv/dts/jh7110-u-boot.dtsi | 81 ++++++++++++-------------------
> 1 file changed, 31 insertions(+), 50 deletions(-)
>
> diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
> index f8d13277d24..cc27dd648f8 100644
> --- a/arch/riscv/dts/jh7110-u-boot.dtsi
> +++ b/arch/riscv/dts/jh7110-u-boot.dtsi
> @@ -3,36 +3,10 @@
> * Copyright (C) 2022 StarFive Technology Co., Ltd.
> */
>
> -#include <dt-bindings/reset/starfive,jh7110-crg.h>
> -
> -/ {
> - timer {
> - compatible = "riscv,timer";
> - interrupts-extended = <&cpu0_intc 5>,
> - <&cpu1_intc 5>,
> - <&cpu2_intc 5>,
> - <&cpu3_intc 5>,
> - <&cpu4_intc 5>;
> - };
> +// BEGIN "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader"
> +// From upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21
>
> - soc {
> - bootph-pre-ram;
> -
> - dmc: dmc@15700000 {
> - bootph-pre-ram;
> - compatible = "starfive,jh7110-dmc";
> - reg = <0x0 0x15700000 0x0 0x10000>,
> - <0x0 0x13000000 0x0 0x10000>;
> - resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
> - <&syscrg JH7110_SYSRST_DDR_OSC>,
> - <&syscrg JH7110_SYSRST_DDR_APB>;
> - reset-names = "axi", "osc", "apb";
> - clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
> - clock-names = "pll1_out";
> - clock-frequency = <2133>;
> - };
> - };
> -};
> +#include <dt-bindings/reset/starfive,jh7110-crg.h>
>
> &clint {
> bootph-pre-ram;
> @@ -58,22 +32,10 @@
> bootph-pre-ram;
> };
>
> -&cpus {
> - bootph-pre-ram;
> -};
> -
> &osc {
> bootph-pre-ram;
> };
>
> -&gmac0_rgmii_rxin {
> - bootph-pre-ram;
> -};
> -
> -&gmac0_rmii_refin {
> - bootph-pre-ram;
> -};
> -
> &gmac1_rgmii_rxin {
> bootph-pre-ram;
> };
> @@ -82,23 +44,42 @@
> bootph-pre-ram;
> };
>
> -&aoncrg {
> - bootph-pre-ram;
> +/ {
> + soc {
> + memory-controller@15700000 {
> + compatible = "starfive,jh7110-dmc";
> + reg = <0x0 0x15700000 0x0 0x10000>,
> + <0x0 0x13000000 0x0 0x10000>;
> + bootph-pre-ram;
> + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
> + clock-names = "pll";
> + resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
> + <&syscrg JH7110_SYSRST_DDR_OSC>,
> + <&syscrg JH7110_SYSRST_DDR_APB>;
> + reset-names = "axi", "osc", "apb";
> + };
> + };
> };
>
> -&pllclk {
> +&syscrg {
> bootph-pre-ram;
> };
>
> -&syscrg {
> - assigned-clock-rates = <0>; /* cpufreq not implemented, use defaults */
> +&pllclk {
> bootph-pre-ram;
> };
>
> -&stgcrg {
> - bootph-pre-ram;
> +// END "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader"
> +
> +/ {
> + soc {
> + memory-controller@15700000 {
> + clock-frequency = <2133>; /* FIXME: delete property and implement CCF */
> + };
> + };
> };
>
> -&sys_syscon {
> - bootph-pre-ram;
> +&syscrg {
> + assigned-clock-rates = <0>; /* FIXME: delete property and implement cpufreq */
> };
> +
Newline at end of file gets a warning, will delete.
-E
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v3 2/4] riscv: dts: starfive: sync visionfive2 overrides with upstream Linux for-next
2025-09-17 0:02 ` [PATCH v3 2/4] riscv: dts: starfive: sync visionfive2 overrides with upstream Linux for-next E Shattow
2025-09-17 2:59 ` E Shattow
@ 2025-09-19 10:58 ` Leo Liang
1 sibling, 0 replies; 10+ messages in thread
From: Leo Liang @ 2025-09-19 10:58 UTC (permalink / raw)
To: E Shattow
Cc: Rick Chen, Minda Chen, Hal Feng, Tom Rini, u-boot,
Heinrich Schuchardt
On Tue, Sep 16, 2025 at 05:02:23PM -0700, E Shattow wrote:
> Sync automatic dtsi inclusion overrides for JH7110 CPU with upstream
> "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot
> loader" from upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21
>
> Signed-off-by: E Shattow <e@freeshell.de>
> ---
> arch/riscv/dts/jh7110-u-boot.dtsi | 81 ++++++++++++-------------------
> 1 file changed, 31 insertions(+), 50 deletions(-)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 3/4] riscv: dts: starfive: visionfive2 depend on SYS_CPU automatic dtsi inclusion
2025-09-17 0:02 [PATCH v3 0/4] riscv: dts: starfive: prune redundant jh7110-common E Shattow
2025-09-17 0:02 ` [PATCH v3 1/4] riscv: dts: starfive: prune redundant jh7110-common overrides E Shattow
2025-09-17 0:02 ` [PATCH v3 2/4] riscv: dts: starfive: sync visionfive2 overrides with upstream Linux for-next E Shattow
@ 2025-09-17 0:02 ` E Shattow
2025-09-19 10:58 ` Leo Liang
2025-09-17 0:02 ` [PATCH v3 4/4] configs: starfive: Use visionfive2 DEVICE_TREE_INCLUDES dtsi named similar to defconfig E Shattow
3 siblings, 1 reply; 10+ messages in thread
From: E Shattow @ 2025-09-17 0:02 UTC (permalink / raw)
To: Rick Chen, Leo, Minda Chen, Hal Feng, Tom Rini
Cc: u-boot, E Shattow, Heinrich Schuchardt
Drop visionfive2 per-board -u-boot.dtsi stubs and instead rely on
automatic inclusion of jh7110-u-boot.dtsi
Signed-off-by: E Shattow <e@freeshell.de>
---
arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi | 7 -------
arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi | 7 -------
arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi | 7 -------
.../dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi | 7 -------
.../dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi | 7 -------
arch/riscv/dts/jh7110-u-boot.dtsi | 1 +
6 files changed, 1 insertion(+), 35 deletions(-)
delete mode 100644 arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
delete mode 100644 arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi
delete mode 100644 arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi
delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
diff --git a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
deleted file mode 100644
index b9202f2acce..00000000000
--- a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2024 StarFive Technology Co., Ltd.
- */
-
-#include "jh7110-u-boot.dtsi"
-#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi
deleted file mode 100644
index b9202f2acce..00000000000
--- a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2024 StarFive Technology Co., Ltd.
- */
-
-#include "jh7110-u-boot.dtsi"
-#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi
deleted file mode 100644
index b9202f2acce..00000000000
--- a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2024 StarFive Technology Co., Ltd.
- */
-
-#include "jh7110-u-boot.dtsi"
-#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
deleted file mode 100644
index b9202f2acce..00000000000
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2024 StarFive Technology Co., Ltd.
- */
-
-#include "jh7110-u-boot.dtsi"
-#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
deleted file mode 100644
index 848ed8225ac..00000000000
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2023 StarFive Technology Co., Ltd.
- */
-
-#include "jh7110-u-boot.dtsi"
-#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index cc27dd648f8..0e5dc3685b2 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -83,3 +83,4 @@
assigned-clock-rates = <0>; /* FIXME: delete property and implement cpufreq */
};
+#include "starfive-visionfive2-binman.dtsi"
--
2.50.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v3 3/4] riscv: dts: starfive: visionfive2 depend on SYS_CPU automatic dtsi inclusion
2025-09-17 0:02 ` [PATCH v3 3/4] riscv: dts: starfive: visionfive2 depend on SYS_CPU automatic dtsi inclusion E Shattow
@ 2025-09-19 10:58 ` Leo Liang
0 siblings, 0 replies; 10+ messages in thread
From: Leo Liang @ 2025-09-19 10:58 UTC (permalink / raw)
To: E Shattow
Cc: Rick Chen, Minda Chen, Hal Feng, Tom Rini, u-boot,
Heinrich Schuchardt
On Tue, Sep 16, 2025 at 05:02:24PM -0700, E Shattow wrote:
> Drop visionfive2 per-board -u-boot.dtsi stubs and instead rely on
> automatic inclusion of jh7110-u-boot.dtsi
>
> Signed-off-by: E Shattow <e@freeshell.de>
> ---
> arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi | 7 -------
> arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi | 7 -------
> arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi | 7 -------
> .../dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi | 7 -------
> .../dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi | 7 -------
> arch/riscv/dts/jh7110-u-boot.dtsi | 1 +
> 6 files changed, 1 insertion(+), 35 deletions(-)
> delete mode 100644 arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
> delete mode 100644 arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi
> delete mode 100644 arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi
> delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
> delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 4/4] configs: starfive: Use visionfive2 DEVICE_TREE_INCLUDES dtsi named similar to defconfig
2025-09-17 0:02 [PATCH v3 0/4] riscv: dts: starfive: prune redundant jh7110-common E Shattow
` (2 preceding siblings ...)
2025-09-17 0:02 ` [PATCH v3 3/4] riscv: dts: starfive: visionfive2 depend on SYS_CPU automatic dtsi inclusion E Shattow
@ 2025-09-17 0:02 ` E Shattow
2025-09-19 10:59 ` Leo Liang
3 siblings, 1 reply; 10+ messages in thread
From: E Shattow @ 2025-09-17 0:02 UTC (permalink / raw)
To: Rick Chen, Leo, Minda Chen, Hal Feng, Tom Rini
Cc: u-boot, E Shattow, Heinrich Schuchardt
Add SYS_CPU automatic inclusion jh7110-u-boot.dtsi to item of config list
DEVICE_TREE_INCLUDES as starfive-visionfive2-u-boot.dtsi and rename file.
Signed-off-by: E Shattow <e@freeshell.de>
---
.../dts/{jh7110-u-boot.dtsi => starfive-visionfive2-u-boot.dtsi} | 0
configs/starfive_visionfive2_defconfig | 1 +
2 files changed, 1 insertion(+)
rename arch/riscv/dts/{jh7110-u-boot.dtsi => starfive-visionfive2-u-boot.dtsi} (100%)
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/starfive-visionfive2-u-boot.dtsi
similarity index 100%
rename from arch/riscv/dts/jh7110-u-boot.dtsi
rename to arch/riscv/dts/starfive-visionfive2-u-boot.dtsi
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index bd1aacbad6a..34ebf3b605b 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -78,6 +78,7 @@ CONFIG_CMD_WDT=y
CONFIG_CMD_WGET=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_BOARD=y
+CONFIG_DEVICE_TREE_INCLUDES="starfive-visionfive2-u-boot.dtsi"
CONFIG_OF_LIST="starfive/jh7110-deepcomputing-fml13v01 starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b"
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
--
2.50.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v3 4/4] configs: starfive: Use visionfive2 DEVICE_TREE_INCLUDES dtsi named similar to defconfig
2025-09-17 0:02 ` [PATCH v3 4/4] configs: starfive: Use visionfive2 DEVICE_TREE_INCLUDES dtsi named similar to defconfig E Shattow
@ 2025-09-19 10:59 ` Leo Liang
0 siblings, 0 replies; 10+ messages in thread
From: Leo Liang @ 2025-09-19 10:59 UTC (permalink / raw)
To: E Shattow
Cc: Rick Chen, Minda Chen, Hal Feng, Tom Rini, u-boot,
Heinrich Schuchardt
On Tue, Sep 16, 2025 at 05:02:25PM -0700, E Shattow wrote:
> Add SYS_CPU automatic inclusion jh7110-u-boot.dtsi to item of config list
> DEVICE_TREE_INCLUDES as starfive-visionfive2-u-boot.dtsi and rename file.
>
> Signed-off-by: E Shattow <e@freeshell.de>
> ---
> .../dts/{jh7110-u-boot.dtsi => starfive-visionfive2-u-boot.dtsi} | 0
> configs/starfive_visionfive2_defconfig | 1 +
> 2 files changed, 1 insertion(+)
> rename arch/riscv/dts/{jh7110-u-boot.dtsi => starfive-visionfive2-u-boot.dtsi} (100%)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 10+ messages in thread