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[95.249.236.54]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3ee0fc00a92sm12353716f8f.63.2025.09.20.07.37.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Sep 2025 07:37:04 -0700 (PDT) From: Christian Marangi To: Tom Rini , Joe Hershberger , Ramon Fried , Weijie Gao , Christian Marangi , u-boot@lists.denx.de Subject: [PATCH 1/5] net: mediatek: mt7988: fix broken phy_setting config Date: Sat, 20 Sep 2025 16:36:46 +0200 Message-ID: <20250920143656.29770-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250920143656.29770-1-ansuelsmth@gmail.com> References: <20250920143656.29770-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The PHY setting for MT7988 are actually never configured for the affected PHY as we are read/writing to the wrong PHY address. This is caused by the fact that we use the index of the NUM_PHYS loop as the PHY address without first offsetting it to the base address. Correctly offset the PHY address before configuring the PHY setting. Signed-off-by: Christian Marangi --- drivers/net/mtk_eth/mt7988.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/net/mtk_eth/mt7988.c b/drivers/net/mtk_eth/mt7988.c index a416d87840c..bc58462af26 100644 --- a/drivers/net/mtk_eth/mt7988.c +++ b/drivers/net/mtk_eth/mt7988.c @@ -34,16 +34,18 @@ static void mt7988_phy_setting(struct mt753x_switch_priv *priv) u32 i; for (i = 0; i < MT753X_NUM_PHYS; i++) { + u16 addr = MT753X_PHY_ADDR(priv->phy_base, i); + /* Enable HW auto downshift */ - mt7531_mii_write(priv, i, 0x1f, 0x1); - val = mt7531_mii_read(priv, i, PHY_EXT_REG_14); + mt7531_mii_write(priv, addr, 0x1f, 0x1); + val = mt7531_mii_read(priv, addr, PHY_EXT_REG_14); val |= PHY_EN_DOWN_SHFIT; - mt7531_mii_write(priv, i, PHY_EXT_REG_14, val); + mt7531_mii_write(priv, addr, PHY_EXT_REG_14, val); /* PHY link down power saving enable */ - val = mt7531_mii_read(priv, i, PHY_EXT_REG_17); + val = mt7531_mii_read(priv, addr, PHY_EXT_REG_17); val |= PHY_LINKDOWN_POWER_SAVING_EN; - mt7531_mii_write(priv, i, PHY_EXT_REG_17, val); + mt7531_mii_write(priv, addr, PHY_EXT_REG_17, val); } } -- 2.51.0