From: Christian Marangi <ansuelsmth@gmail.com>
To: Tom Rini <trini@konsulko.com>,
Joe Hershberger <joe.hershberger@ni.com>,
Ramon Fried <rfried.dev@gmail.com>,
Weijie Gao <weijie.gao@mediatek.com>,
Christian Marangi <ansuelsmth@gmail.com>,
u-boot@lists.denx.de
Subject: [PATCH v2 1/5] net: mediatek: mt7531/7988: fix broken PHY turn ON/OFF
Date: Sat, 20 Sep 2025 18:09:41 +0200 [thread overview]
Message-ID: <20250920161013.31799-2-ansuelsmth@gmail.com> (raw)
In-Reply-To: <20250920161013.31799-1-ansuelsmth@gmail.com>
The PHY for MT7531/MT7988 are never actully turned ON/OFF for the
affected PHY as we are read/writing to the wrong PHY address.
This is caused by the fact that we use the MT753X_PHY_ADDR macro 2
times offsetting the address multiple times.
One in the _setup() function and one in the mt7531_mii_read/write.
Drop the additional usage of MT753X_PHY_ADDR in setup() to correctly
set the PHY.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/mtk_eth/mt7531.c | 20 +++++++-------------
drivers/net/mtk_eth/mt7988.c | 12 +++++-------
2 files changed, 12 insertions(+), 20 deletions(-)
diff --git a/drivers/net/mtk_eth/mt7531.c b/drivers/net/mtk_eth/mt7531.c
index 32d6bebbbdb..965bc3cb7e9 100644
--- a/drivers/net/mtk_eth/mt7531.c
+++ b/drivers/net/mtk_eth/mt7531.c
@@ -22,17 +22,13 @@
static int mt7531_core_reg_read(struct mt753x_switch_priv *priv, u32 reg)
{
- u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0);
-
- return mt7531_mmd_read(priv, phy_addr, 0x1f, reg);
+ return mt7531_mmd_read(priv, 0, 0x1f, reg);
}
static void mt7531_core_reg_write(struct mt753x_switch_priv *priv, u32 reg,
u32 val)
{
- u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0);
-
- mt7531_mmd_write(priv, phy_addr, 0x1f, reg, val);
+ mt7531_mmd_write(priv, 0, 0x1f, reg, val);
}
static void mt7531_core_pll_setup(struct mt753x_switch_priv *priv)
@@ -171,7 +167,7 @@ static int mt7531_setup(struct mtk_eth_switch_priv *swpriv)
{
struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv;
u32 i, val, pmcr, port5_sgmii;
- u16 phy_addr, phy_val;
+ u16 phy_val;
priv->smi_addr = MT753X_DFL_SMI_ADDR;
priv->phy_base = (priv->smi_addr + 1) & MT753X_SMI_ADDR_MASK;
@@ -180,10 +176,9 @@ static int mt7531_setup(struct mtk_eth_switch_priv *swpriv)
/* Turn off PHYs */
for (i = 0; i < MT753X_NUM_PHYS; i++) {
- phy_addr = MT753X_PHY_ADDR(priv->phy_base, i);
- phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR);
+ phy_val = mt7531_mii_read(priv, i, MII_BMCR);
phy_val |= BMCR_PDOWN;
- mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val);
+ mt7531_mii_write(priv, i, MII_BMCR, phy_val);
}
/* Force MAC link down before reset */
@@ -239,10 +234,9 @@ static int mt7531_setup(struct mtk_eth_switch_priv *swpriv)
/* Turn on PHYs */
for (i = 0; i < MT753X_NUM_PHYS; i++) {
- phy_addr = MT753X_PHY_ADDR(priv->phy_base, i);
- phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR);
+ phy_val = mt7531_mii_read(priv, i, MII_BMCR);
phy_val &= ~BMCR_PDOWN;
- mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val);
+ mt7531_mii_write(priv, i, MII_BMCR, phy_val);
}
mt7531_phy_setting(priv);
diff --git a/drivers/net/mtk_eth/mt7988.c b/drivers/net/mtk_eth/mt7988.c
index a416d87840c..87b6ed30cd0 100644
--- a/drivers/net/mtk_eth/mt7988.c
+++ b/drivers/net/mtk_eth/mt7988.c
@@ -61,7 +61,7 @@ static void mt7988_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable)
static int mt7988_setup(struct mtk_eth_switch_priv *swpriv)
{
struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv;
- u16 phy_addr, phy_val;
+ u16 phy_val;
u32 pmcr;
int i;
@@ -72,10 +72,9 @@ static int mt7988_setup(struct mtk_eth_switch_priv *swpriv)
/* Turn off PHYs */
for (i = 0; i < MT753X_NUM_PHYS; i++) {
- phy_addr = MT753X_PHY_ADDR(priv->phy_base, i);
- phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR);
+ phy_val = mt7531_mii_read(priv, i, MII_BMCR);
phy_val |= BMCR_PDOWN;
- mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val);
+ mt7531_mii_write(priv, i, MII_BMCR, phy_val);
}
switch (priv->epriv.phy_interface) {
@@ -128,10 +127,9 @@ static int mt7988_setup(struct mtk_eth_switch_priv *swpriv)
/* Turn on PHYs */
for (i = 0; i < MT753X_NUM_PHYS; i++) {
- phy_addr = MT753X_PHY_ADDR(priv->phy_base, i);
- phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR);
+ phy_val = mt7531_mii_read(priv, i, MII_BMCR);
phy_val &= ~BMCR_PDOWN;
- mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val);
+ mt7531_mii_write(priv, i, MII_BMCR, phy_val);
}
mt7988_phy_setting(priv);
--
2.51.0
next prev parent reply other threads:[~2025-09-20 16:10 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-20 16:09 [PATCH v2 0/5] net: mediatek: mt7988: various fixup + MDIO detach Christian Marangi
2025-09-20 16:09 ` Christian Marangi [this message]
2025-09-20 16:09 ` [PATCH v2 2/5] net: mediatek: mt7988: restore PHY page on PHY setting exit Christian Marangi
2025-09-20 16:09 ` [PATCH v2 3/5] net: mediatek: mt7988: free allocated MDIO bus on cleanup Christian Marangi
2025-09-20 16:09 ` [PATCH v2 4/5] net: mediatek: move MT7531 MMIO MDIO to dedicated driver Christian Marangi
2025-09-20 16:09 ` [PATCH v2 5/5] net: airoha: bind MDIO controller on Ethernet load Christian Marangi
2025-10-22 13:42 ` Jerome Forissier
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