From: E Shattow <e@freeshell.de>
To: Tom Rini <trini@konsulko.com>
Cc: u-boot@lists.denx.de, E Shattow <e@freeshell.de>,
Hal Feng <hal.feng@starfivetech.com>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v2 03/10] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader
Date: Wed, 15 Oct 2025 03:22:46 -0700 [thread overview]
Message-ID: <20251015102253.48276-4-e@freeshell.de> (raw)
In-Reply-To: <20251015102253.48276-1-e@freeshell.de>
Add bootph-pre-ram hinting to jh7110.dtsi:
- CPU interrupt controller(s)
- gmac1_rgmii_rxin fixed-clock (dependency of syscrg)
- gmac1_rmii_refin fixed-clock (dependency of syscrg)
- oscillator
- core local interrupt timer
- syscrg clock-controller
- pllclk clock-controller (dependency of syscrg)
- DDR memory controller
Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
[ upstream commit: 8181cc2f3f21657392da912eb20ee17514c87828 ]
(cherry picked from commit a31c1c85876bf9f15f3df14959354ab9a200ffa0)
---
dts/upstream/src/riscv/starfive/jh7110.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/dts/upstream/src/riscv/starfive/jh7110.dtsi b/dts/upstream/src/riscv/starfive/jh7110.dtsi
index f3876660c07..6e56e9d20bb 100644
--- a/dts/upstream/src/riscv/starfive/jh7110.dtsi
+++ b/dts/upstream/src/riscv/starfive/jh7110.dtsi
@@ -35,6 +35,7 @@
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
+ bootph-pre-ram;
interrupt-controller;
#interrupt-cells = <1>;
};
@@ -68,6 +69,7 @@
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
+ bootph-pre-ram;
interrupt-controller;
#interrupt-cells = <1>;
};
@@ -101,6 +103,7 @@
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
+ bootph-pre-ram;
interrupt-controller;
#interrupt-cells = <1>;
};
@@ -134,6 +137,7 @@
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
+ bootph-pre-ram;
interrupt-controller;
#interrupt-cells = <1>;
};
@@ -167,6 +171,7 @@
cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
+ bootph-pre-ram;
interrupt-controller;
#interrupt-cells = <1>;
};
@@ -273,12 +278,14 @@
gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
compatible = "fixed-clock";
+ bootph-pre-ram;
clock-output-names = "gmac1_rgmii_rxin";
#clock-cells = <0>;
};
gmac1_rmii_refin: gmac1-rmii-refin-clock {
compatible = "fixed-clock";
+ bootph-pre-ram;
clock-output-names = "gmac1_rmii_refin";
#clock-cells = <0>;
};
@@ -321,6 +328,7 @@
osc: oscillator {
compatible = "fixed-clock";
+ bootph-pre-ram;
clock-output-names = "osc";
#clock-cells = <0>;
};
@@ -354,6 +362,7 @@
clint: timer@2000000 {
compatible = "starfive,jh7110-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0x10000>;
+ bootph-pre-ram;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>,
<&cpu2_intc 3>, <&cpu2_intc 7>,
@@ -880,6 +889,7 @@
syscrg: clock-controller@13020000 {
compatible = "starfive,jh7110-syscrg";
reg = <0x0 0x13020000 0x0 0x10000>;
+ bootph-pre-ram;
clocks = <&osc>, <&gmac1_rmii_refin>,
<&gmac1_rgmii_rxin>,
<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
@@ -904,6 +914,7 @@
pllclk: clock-controller {
compatible = "starfive,jh7110-pll";
+ bootph-pre-ram;
clocks = <&osc>;
#clock-cells = <1>;
};
@@ -935,6 +946,7 @@
compatible = "starfive,jh7110-dmc";
reg = <0x0 0x15700000 0x0 0x10000>,
<0x0 0x13000000 0x0 0x10000>;
+ bootph-pre-ram;
clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
clock-names = "pll";
resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
--
2.50.0
next prev parent reply other threads:[~2025-10-15 10:24 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-15 10:22 [PATCH v2 00/10] dts: starfive: cherry-pick jh7110 updates from v6.18-rc1-dts E Shattow
2025-10-15 10:22 ` [PATCH v2 01/10] riscv: dts: starfive: jh7110-common: drop no-sdio property from mmc1 E Shattow
2025-10-15 10:22 ` [PATCH v2 02/10] riscv: dts: starfive: jh7110: add DMC memory controller E Shattow
2025-10-15 10:22 ` E Shattow [this message]
2025-10-15 10:22 ` [PATCH v2 04/10] riscv: dts: starfive: jh7110-common: drop no-mmc property from mmc1 E Shattow
2025-10-15 10:22 ` [PATCH v2 05/10] riscv: dts: starfive: jh7110-common: drop mmc post-power-on-delay-ms E Shattow
2025-10-15 10:22 ` [PATCH v2 06/10] riscv: dts: starfive: add common board dtsi for Milk-V Mars CM variants E Shattow
2025-10-15 10:22 ` [PATCH v2 07/10] dt-bindings: riscv: starfive: add milkv,marscm-emmc E Shattow
2025-10-15 10:22 ` [PATCH v2 08/10] riscv: dts: starfive: add Milk-V Mars CM system-on-module E Shattow
2025-10-15 10:22 ` [PATCH v2 09/10] dt-bindings: riscv: starfive: add milkv,marscm-lite E Shattow
2025-10-15 10:22 ` [PATCH v2 10/10] riscv: dts: starfive: add Milk-V Mars CM Lite system-on-module E Shattow
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