From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B61CCCD195 for ; Fri, 17 Oct 2025 13:17:00 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B0570838A0; Fri, 17 Oct 2025 15:16:08 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="hWKOHUKs"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 2AB68837E4; Fri, 17 Oct 2025 15:16:08 +0200 (CEST) Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 10CC8837E4 for ; Fri, 17 Oct 2025 15:16:05 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=anshuld@ti.com Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 59HDFxvq2274966; Fri, 17 Oct 2025 08:15:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1760706959; bh=LhxoT3vy/YnaunorY/1/LmiXdiFYOYw3AJyDed7puyU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hWKOHUKsNLdWOPSTaLf9N2dqIoH3VEZHc8z+83QhlRkqW/vyJGU1kQ+b6YO2ob+bX k21sywZL2f6gOBKqZUkXtBHBf71zTlxgbcdsAbkMZP07TSIDuikqc+jfvQObL+XJBa +EyXw1XR0Ubv9fdL7T3Z7vLhsYRuR9f0aOi5zqlc= Received: from DLEE212.ent.ti.com (dlee212.ent.ti.com [157.170.170.114]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 59HDFxQG2818600 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 17 Oct 2025 08:15:59 -0500 Received: from DLEE206.ent.ti.com (157.170.170.90) by DLEE212.ent.ti.com (157.170.170.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 17 Oct 2025 08:15:59 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE206.ent.ti.com (157.170.170.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Fri, 17 Oct 2025 08:15:59 -0500 Received: from localhost (dhcp-172-24-233-105.dhcp.ti.com [172.24.233.105]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 59HDFwtR1343296; Fri, 17 Oct 2025 08:15:58 -0500 From: Anshul Dalal To: CC: Anshul Dalal , , , , , , , , , , , , , , , , Subject: [PATCH v11 09/11] mach-k3: add reserved memory fixups for next boot stage Date: Fri, 17 Oct 2025 18:45:31 +0530 Message-ID: <20251017131540.3636067-10-anshuld@ti.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251017131540.3636067-1-anshuld@ti.com> References: <20251017131540.3636067-1-anshuld@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The boot flow in K3 platforms requires the subsequent boot stages to be aware of the memory reserved for previous boot binaries. In the regular boot sequence of: R5 SPL -> ATF -> OP-TEE -> A-core SPL -> U-Boot -> Kernel, Both A-core SPL and U-Boot should be made aware of the memory reserved for ATF and OP-TEE from their device-tree. Currently this information is absent. Therefore this patch adds the reserved-memory regions as part of spl_perform_arch_fixups for the next stage's DT. This is called during both R5 and A-core SPL which fixes up the DT for their respective next stages: A-core SPL and U-Boot proper. Reviewed-by: Dhruva Gole Signed-off-by: Anshul Dalal Tested-by: Wadim Egorov --- arch/arm/mach-k3/common.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 30ad98a68a2..f734f10b605 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -321,6 +321,17 @@ static __maybe_unused void k3_dma_remove(void) pr_warn("DMA Device not found (err=%d)\n", rc); } +void spl_perform_arch_fixups(struct spl_image_info *spl_image) +{ + void *fdt = spl_image_fdt_addr(spl_image); + + if (!fdt) + return; + + fdt_fixup_reserved(fdt, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000); + fdt_fixup_reserved(fdt, "optee", CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000); +} + void spl_board_prepare_for_boot(void) { #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) -- 2.51.0