From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E50CCCD199 for ; Fri, 17 Oct 2025 13:16:22 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0D91E83835; Fri, 17 Oct 2025 15:15:58 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="xbULD1vJ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id E76E983839; Fri, 17 Oct 2025 15:15:55 +0200 (CEST) Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id BAAD083734 for ; Fri, 17 Oct 2025 15:15:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=anshuld@ti.com Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 59HDFmxL277445; Fri, 17 Oct 2025 08:15:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1760706948; bh=/TsTgUJWonwNdxUt3rrYagHlRE1AJH4qcPN28IN4sWw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xbULD1vJx1e6qnlTboQr1W8AI9uLnhPrMElTF+KH+sX8enAa4SVB0VxQAIs8pwZF2 QvfwMUlJ0eN/QlPWiSrQvIS+DdW6IEJ5Jyx9NDdpTvKD/RtyvQD8nNFeg9khb6fM3Y UXp/0r0agpaEzg164nIcjCYOljDfPAnDPhrcSuFw= Received: from DLEE214.ent.ti.com (dlee214.ent.ti.com [157.170.170.117]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 59HDFmgC2419186 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 17 Oct 2025 08:15:48 -0500 Received: from DLEE206.ent.ti.com (157.170.170.90) by DLEE214.ent.ti.com (157.170.170.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 17 Oct 2025 08:15:48 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE206.ent.ti.com (157.170.170.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Fri, 17 Oct 2025 08:15:47 -0500 Received: from localhost (dhcp-172-24-233-105.dhcp.ti.com [172.24.233.105]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 59HDFkZg1347515; Fri, 17 Oct 2025 08:15:47 -0500 From: Anshul Dalal To: CC: Anshul Dalal , , , , , , , , , , , , , , , , Subject: [PATCH v11 03/11] arm: armv8: mmu: export mmu_setup Date: Fri, 17 Oct 2025 18:45:25 +0530 Message-ID: <20251017131540.3636067-4-anshuld@ti.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251017131540.3636067-1-anshuld@ti.com> References: <20251017131540.3636067-1-anshuld@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The mmu_setup function configures the page tables based on the board supplied mem_map struct array. It is called implicitly as part of dcache_enable but this limits us to only be able to use APIs such as mmu_change_region_attr only after caches are enabled. This might lead to speculative accesses before we can unmap a region that is marked as cacheable in the static memory map. Therefore this patch exports the mmu_setup function in mmu.h allowing users to have more control over when the mmu is configured. For K3 specifically this allows for the following configuration sequence as part of enable_caches: static mem_map fixups (TODO) -> mmu_setup -> carveouts using mmu_change_region_attr (TODO) -> icache/dcache enable Reviewed-by: Dhruva Gole Reviewed-by: Ilias Apalodimas Signed-off-by: Anshul Dalal Tested-by: Wadim Egorov --- arch/arm/include/asm/armv8/mmu.h | 5 +++++ arch/arm/mach-k3/common.c | 3 +++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 6af8cd111a4..3807c702fb6 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -197,6 +197,11 @@ struct mm_region { extern struct mm_region *mem_map; void setup_pgtables(void); u64 get_tcr(u64 *pips, u64 *pva_bits); + +/** + * mmu_setup() - Sets up the mmu page tables as per mem_map + */ +void mmu_setup(void); #endif #endif /* _ASM_ARMV8_MMU_H_ */ diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 7f2a4e6260e..ea287ba1226 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -30,6 +30,7 @@ #include #include #include +#include #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002 @@ -261,6 +262,8 @@ void board_prep_linux(struct bootm_headers *images) void enable_caches(void) { + mmu_setup(); + icache_enable(); dcache_enable(); } -- 2.51.0