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[187.190.202.235]) by smtp.gmail.com with ESMTPSA id 5614622812f47-443debfe8f0sm132435b6e.15.2025.10.17.13.40.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Oct 2025 13:40:42 -0700 (PDT) Date: Fri, 17 Oct 2025 14:40:40 -0600 From: Tom Rini To: Kaustabh Chakraborty , Duje =?utf-8?Q?Mihanovi=C4=87?= Cc: u-boot@lists.denx.de Subject: Re: [PATCH v2] armv8: implement workaround for broken CNTFRQ_EL0 value Message-ID: <20251017204040.GI6688@bill-the-cat> References: <20251017-armv8-broken-cntfrq-v2-1-1e043cbb657e@disroot.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="qDx3EHW/MWlJWAa2" Content-Disposition: inline In-Reply-To: <20251017-armv8-broken-cntfrq-v2-1-1e043cbb657e@disroot.org> X-Clacks-Overhead: GNU Terry Pratchett X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean --qDx3EHW/MWlJWAa2 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Oct 17, 2025 at 08:49:47PM +0530, Kaustabh Chakraborty wrote: > In devices where the U-Boot is used as a secondary bootloader, we rely > on the device's primary bootloader to implement CNTFRQ_EL0. However, > this reliance may lead to a non-functional timer in broken firmware. >=20 > For instance, some versions of Samsung's S-Boot don't implement it. It's > also not possible to set it in the U-Boot, because it's booted in a lower > exception level. CNTFRQ_EL0 is reported to be 0. >=20 > Use gd->arch.timer_rate_hz to override the queried value if set. This > setting needs to be done in the board file, preferrably in timer_init(). >=20 > Signed-off-by: Kaustabh Chakraborty > --- > Changes in v2: > - Switched to using gd->arch.timer_rate_hz instead of a new config > option (Ahmad Fatoum) > - Link to v1: https://lore.kernel.org/r/20251014-armv8-broken-cntfrq-v1-1= -b63f9c69ffcb@disroot.org > --- > arch/arm/cpu/armv8/generic_timer.c | 4 ++++ > 1 file changed, 4 insertions(+) >=20 > diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/gene= ric_timer.c > index 1de7ec596fc7cbbc3e78a241f163bc0a4fcad6b6..1bc72ed26ca31af8e8e72008e= d7885cbde23b076 100644 > --- a/arch/arm/cpu/armv8/generic_timer.c > +++ b/arch/arm/cpu/armv8/generic_timer.c > @@ -19,6 +19,10 @@ DECLARE_GLOBAL_DATA_PTR; > unsigned long notrace get_tbclk(void) > { > unsigned long cntfrq; > + > + if (gd->arch.timer_rate_hz) > + return gd->arch.timer_rate_hz; > + > asm volatile("mrs %0, cntfrq_el0" : "=3Dr" (cntfrq)); > return cntfrq; > } This would impact coreprimevelte (as it's the only ARM64 platform to set gd->arch.timer_rate_hz) but as it's also a Samsung platform it's likely in the same broken situation your platforms are. --=20 Tom --qDx3EHW/MWlJWAa2 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTzzqh0PWDgGS+bTHor4qD1Cr/kCgUCaPKpxAAKCRAr4qD1Cr/k CrZqAP9eymrkOEbKcDLXCfGjavdu3y378HzOul+Cy/dKJK10jAEA7BleS/a1T1DO LkKMoT+K5tFi7jf2TL0kRZAgnVaqvQQ= =D9Q/ -----END PGP SIGNATURE----- --qDx3EHW/MWlJWAa2--