* [PATCH] FPGA2SDRAM setup fix
@ 2025-10-20 8:23 Brian Sune
2025-10-20 12:38 ` Fabio Estevam
0 siblings, 1 reply; 6+ messages in thread
From: Brian Sune @ 2025-10-20 8:23 UTC (permalink / raw)
To: Tom Rini, u-boot
From: intel <intel@intel.com>
After testing, w/o proper setup
the FPGA2SDRAM bridge will not work and stall.
Pulling from official fix and w/o this initialization,
both 2025.07 and 2025.10 also suffer stall on U-Boot
and distro. Any FPGA to HPS-SDRAM action will immediate
stall the CPU. As such, this patch fix the issue.
Signed-off-by: intel <intel@intel.com>
---
arch/arm/mach-socfpga/misc_gen5.c | 34 ++++++++++++++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index b136691c685..5259ef54d73 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -217,6 +217,34 @@ int arch_early_init_r(void)
static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+void socfpga_sdram_apply_static_cfg(void)
+{
+ const u32 applymask = 0x8;
+ u32 val = readl(&sdr_ctrl->static_cfg) | applymask;
+
+ /*
+ * SDRAM staticcfg register specific:
+ * When applying the register setting, the CPU must not access
+ * SDRAM. Luckily for us, we can use i-cache here to help us
+ * circumvent the SDRAM access issue. The idea is to make sure
+ * that the code is in one full i-cache line by branching past
+ * it and back. Once it is in the i-cache, we execute the core
+ * of the code and apply the register settings.
+ *
+ * The code below uses 7 instructions, while the Cortex-A9 has
+ * 32-byte cachelines, thus the limit is 8 instructions total.
+ */
+ asm volatile(".align 5 \n"
+ " b 2f \n"
+ "1: str %0, [%1] \n"
+ " dsb \n"
+ " isb \n"
+ " b 3f \n"
+ "2: b 1b \n"
+ "3: nop \n"
+ : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");
+}
+
void do_bridge_reset(int enable, unsigned int mask)
{
int i;
@@ -234,7 +262,10 @@ void do_bridge_reset(int enable, unsigned int mask)
writel(iswgrp_handoff[2],
socfpga_get_sysmgr_addr() +
SYSMGR_GEN5_FPGAINFGRP_MODULE);
- writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
+ if (iswgrp_handoff[3]) {
+ writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
+ socfpga_sdram_apply_static_cfg();
+ }
writel(iswgrp_handoff[0],
socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
writel(iswgrp_handoff[1], &nic301_regs->remap);
@@ -246,6 +277,7 @@ void do_bridge_reset(int enable, unsigned int mask)
writel(0, socfpga_get_sysmgr_addr() +
SYSMGR_GEN5_FPGAINFGRP_MODULE);
writel(0, &sdr_ctrl->fpgaport_rst);
+ socfpga_sdram_apply_static_cfg();
writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
writel(1, &nic301_regs->remap);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] FPGA2SDRAM setup fix
2025-10-20 8:23 Brian Sune
@ 2025-10-20 12:38 ` Fabio Estevam
2025-10-20 13:13 ` Sune Brian
0 siblings, 1 reply; 6+ messages in thread
From: Fabio Estevam @ 2025-10-20 12:38 UTC (permalink / raw)
To: Brian Sune; +Cc: Tom Rini, u-boot
On Mon, Oct 20, 2025 at 5:32 AM Brian Sune <briansune@gmail.com> wrote:
>
> From: intel <intel@intel.com>
>
> After testing, w/o proper setup
> the FPGA2SDRAM bridge will not work and stall.
> Pulling from official fix and w/o this initialization,
> both 2025.07 and 2025.10 also suffer stall on U-Boot
> and distro. Any FPGA to HPS-SDRAM action will immediate
> stall the CPU. As such, this patch fix the issue.
>
> Signed-off-by: intel <intel@intel.com>
You should use a real name in the From and Signed-off-by lines.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] FPGA2SDRAM setup fix
2025-10-20 12:38 ` Fabio Estevam
@ 2025-10-20 13:13 ` Sune Brian
0 siblings, 0 replies; 6+ messages in thread
From: Sune Brian @ 2025-10-20 13:13 UTC (permalink / raw)
To: Fabio Estevam; +Cc: Tom Rini, u-boot
> > Signed-off-by: intel <intel@intel.com>
>
> You should use a real name in the From and Signed-off-by lines.
Indeed, I forgot to amend the signed-off.
There are too many virtual machine on my side to work on these.
Close this and reopen a new one.
Sorry about the signed-off issue, not pay enough attention.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] FPGA2SDRAM setup fix
@ 2025-10-20 13:15 Brian Sune
0 siblings, 0 replies; 6+ messages in thread
From: Brian Sune @ 2025-10-20 13:15 UTC (permalink / raw)
To: Tom Rini, u-boot
From: intel <intel@intel.com>
After testing, w/o proper setup
the FPGA2SDRAM bridge will not work and stall.
Pulling from official fix and w/o this initialization,
both 2025.07 and 2025.10 also suffer stall on U-Boot
and distro. Any FPGA to HPS-SDRAM action will immediate
stall the CPU. As such, this patch fix the issue.
Signed-off-by: Brian Sune <briansune@gmail.com>
---
arch/arm/mach-socfpga/misc_gen5.c | 34 ++++++++++++++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index b136691c685..5259ef54d73 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -217,6 +217,34 @@ int arch_early_init_r(void)
static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+void socfpga_sdram_apply_static_cfg(void)
+{
+ const u32 applymask = 0x8;
+ u32 val = readl(&sdr_ctrl->static_cfg) | applymask;
+
+ /*
+ * SDRAM staticcfg register specific:
+ * When applying the register setting, the CPU must not access
+ * SDRAM. Luckily for us, we can use i-cache here to help us
+ * circumvent the SDRAM access issue. The idea is to make sure
+ * that the code is in one full i-cache line by branching past
+ * it and back. Once it is in the i-cache, we execute the core
+ * of the code and apply the register settings.
+ *
+ * The code below uses 7 instructions, while the Cortex-A9 has
+ * 32-byte cachelines, thus the limit is 8 instructions total.
+ */
+ asm volatile(".align 5 \n"
+ " b 2f \n"
+ "1: str %0, [%1] \n"
+ " dsb \n"
+ " isb \n"
+ " b 3f \n"
+ "2: b 1b \n"
+ "3: nop \n"
+ : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");
+}
+
void do_bridge_reset(int enable, unsigned int mask)
{
int i;
@@ -234,7 +262,10 @@ void do_bridge_reset(int enable, unsigned int mask)
writel(iswgrp_handoff[2],
socfpga_get_sysmgr_addr() +
SYSMGR_GEN5_FPGAINFGRP_MODULE);
- writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
+ if (iswgrp_handoff[3]) {
+ writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
+ socfpga_sdram_apply_static_cfg();
+ }
writel(iswgrp_handoff[0],
socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
writel(iswgrp_handoff[1], &nic301_regs->remap);
@@ -246,6 +277,7 @@ void do_bridge_reset(int enable, unsigned int mask)
writel(0, socfpga_get_sysmgr_addr() +
SYSMGR_GEN5_FPGAINFGRP_MODULE);
writel(0, &sdr_ctrl->fpgaport_rst);
+ socfpga_sdram_apply_static_cfg();
writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
writel(1, &nic301_regs->remap);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] FPGA2SDRAM setup fix
@ 2025-10-20 13:35 Brian Sune
2025-11-17 7:37 ` Chee, Tien Fong
0 siblings, 1 reply; 6+ messages in thread
From: Brian Sune @ 2025-10-20 13:35 UTC (permalink / raw)
To: Fabio Estevam, Tom Rini, u-boot
After testing, w/o proper setup
the FPGA2SDRAM bridge will not work and stall.
Pulling from official fix and w/o this initialization,
both 2025.07 and 2025.10 also suffer stall on U-Boot
and distro. Any FPGA to HPS-SDRAM action will immediate
stall the CPU. As such, this patch fix the issue.
Signed-off-by: Brian Sune <briansune@gmail.com>
---
arch/arm/mach-socfpga/misc_gen5.c | 34 ++++++++++++++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index b136691c685..5259ef54d73 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -217,6 +217,34 @@ int arch_early_init_r(void)
static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+void socfpga_sdram_apply_static_cfg(void)
+{
+ const u32 applymask = 0x8;
+ u32 val = readl(&sdr_ctrl->static_cfg) | applymask;
+
+ /*
+ * SDRAM staticcfg register specific:
+ * When applying the register setting, the CPU must not access
+ * SDRAM. Luckily for us, we can use i-cache here to help us
+ * circumvent the SDRAM access issue. The idea is to make sure
+ * that the code is in one full i-cache line by branching past
+ * it and back. Once it is in the i-cache, we execute the core
+ * of the code and apply the register settings.
+ *
+ * The code below uses 7 instructions, while the Cortex-A9 has
+ * 32-byte cachelines, thus the limit is 8 instructions total.
+ */
+ asm volatile(".align 5 \n"
+ " b 2f \n"
+ "1: str %0, [%1] \n"
+ " dsb \n"
+ " isb \n"
+ " b 3f \n"
+ "2: b 1b \n"
+ "3: nop \n"
+ : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");
+}
+
void do_bridge_reset(int enable, unsigned int mask)
{
int i;
@@ -234,7 +262,10 @@ void do_bridge_reset(int enable, unsigned int mask)
writel(iswgrp_handoff[2],
socfpga_get_sysmgr_addr() +
SYSMGR_GEN5_FPGAINFGRP_MODULE);
- writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
+ if (iswgrp_handoff[3]) {
+ writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
+ socfpga_sdram_apply_static_cfg();
+ }
writel(iswgrp_handoff[0],
socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
writel(iswgrp_handoff[1], &nic301_regs->remap);
@@ -246,6 +277,7 @@ void do_bridge_reset(int enable, unsigned int mask)
writel(0, socfpga_get_sysmgr_addr() +
SYSMGR_GEN5_FPGAINFGRP_MODULE);
writel(0, &sdr_ctrl->fpgaport_rst);
+ socfpga_sdram_apply_static_cfg();
writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
writel(1, &nic301_regs->remap);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] FPGA2SDRAM setup fix
2025-10-20 13:35 Brian Sune
@ 2025-11-17 7:37 ` Chee, Tien Fong
0 siblings, 0 replies; 6+ messages in thread
From: Chee, Tien Fong @ 2025-11-17 7:37 UTC (permalink / raw)
To: Brian Sune, Fabio Estevam, Tom Rini, u-boot
Hi,
On 20/10/2025 9:35 pm, Brian Sune wrote:
> After testing, w/o proper setup
> the FPGA2SDRAM bridge will not work and stall.
> Pulling from official fix and w/o this initialization,
> both 2025.07 and 2025.10 also suffer stall on U-Boot
> and distro. Any FPGA to HPS-SDRAM action will immediate
> stall the CPU. As such, this patch fix the issue.
>
> Signed-off-by: Brian Sune<briansune@gmail.com>
> ---
> arch/arm/mach-socfpga/misc_gen5.c | 34 ++++++++++++++++++++++++++++++-
> 1 file changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
> index b136691c685..5259ef54d73 100644
> --- a/arch/arm/mach-socfpga/misc_gen5.c
> +++ b/arch/arm/mach-socfpga/misc_gen5.c
> @@ -217,6 +217,34 @@ int arch_early_init_r(void)
> static struct socfpga_sdr_ctrl *sdr_ctrl =
> (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
>
> +void socfpga_sdram_apply_static_cfg(void)
> +{
> + const u32 applymask = 0x8;
> + u32 val = readl(&sdr_ctrl->static_cfg) | applymask;
> +
> + /*
> + * SDRAM staticcfg register specific:
> + * When applying the register setting, the CPU must not access
> + * SDRAM. Luckily for us, we can use i-cache here to help us
> + * circumvent the SDRAM access issue. The idea is to make sure
> + * that the code is in one full i-cache line by branching past
> + * it and back. Once it is in the i-cache, we execute the core
> + * of the code and apply the register settings.
> + *
> + * The code below uses 7 instructions, while the Cortex-A9 has
> + * 32-byte cachelines, thus the limit is 8 instructions total.
> + */
> + asm volatile(".align 5 \n"
> + " b 2f \n"
> + "1: str %0, [%1] \n"
> + " dsb \n"
> + " isb \n"
> + " b 3f \n"
> + "2: b 1b \n"
> + "3: nop \n"
> + : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");
> +}
> +
> void do_bridge_reset(int enable, unsigned int mask)
> {
> int i;
> @@ -234,7 +262,10 @@ void do_bridge_reset(int enable, unsigned int mask)
> writel(iswgrp_handoff[2],
> socfpga_get_sysmgr_addr() +
> SYSMGR_GEN5_FPGAINFGRP_MODULE);
> - writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
> + if (iswgrp_handoff[3]) {
> + writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
> + socfpga_sdram_apply_static_cfg();
> + }
> writel(iswgrp_handoff[0],
> socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
> writel(iswgrp_handoff[1], &nic301_regs->remap);
> @@ -246,6 +277,7 @@ void do_bridge_reset(int enable, unsigned int mask)
> writel(0, socfpga_get_sysmgr_addr() +
> SYSMGR_GEN5_FPGAINFGRP_MODULE);
> writel(0, &sdr_ctrl->fpgaport_rst);
> + socfpga_sdram_apply_static_cfg();
> writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
> writel(1, &nic301_regs->remap);
> }
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Best regards,
Tien Fong
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-11-17 7:37 UTC | newest]
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2025-10-20 13:15 [PATCH] FPGA2SDRAM setup fix Brian Sune
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2025-10-20 13:35 Brian Sune
2025-11-17 7:37 ` Chee, Tien Fong
2025-10-20 8:23 Brian Sune
2025-10-20 12:38 ` Fabio Estevam
2025-10-20 13:13 ` Sune Brian
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