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[13.158.138.160]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7acd6824811sm2528441b3a.64.2025.11.04.03.03.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Nov 2025 03:03:22 -0800 (PST) From: Ssunk To: marek.vasut@mailbox.org Cc: Takahiro.Kuwano@infineon.com, jagan@amarulasolutions.com, pratyush@kernel.org, ssunkkan@gmail.com, trini@konsulko.com, tudor.ambarus@linaro.org, u-boot@lists.denx.de, vigneshr@ti.com Subject: Re: [PATCH v2] spi-nor: add support for XM25QH01D Date: Tue, 4 Nov 2025 19:03:07 +0800 Message-Id: <20251104110307.3993-1-ssunkkan@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Hello Marek, >I'm sorry, my original suggestion was unclear. > >If you want to sort the whole XMC part list, then please do 2-patch >series, sort the list in patch 1/2 and then add the chip in 2/2 . Thanks for the clarification! Actually, I don’t intend to sort the whole XMC flash list — I only want to add the new XM25QH01D entry. Would it be acceptable if I just place it in the appropriate position without reordering the rest of the list? Best regards, Ssunk >On 11/3/25 12:12 PM, Ssunk wrote: >> Add support for the XMC XM25QH01D SPI NOR flash. >> >> This device has 1Gbit (128MB) capacity, with 64KB sectors and >> supports 4KB erase, dual and quad read modes, and 4-byte opcodes. >> Datasheet link: https://www.xmcwh.com/uploads/958/XM25QH01D_Ver1.0.pdf >> >> Changes in v2: >> - Keep the list sorted of XMC >> >> Signed-off-by: Ssunk >> --- >> drivers/mtd/spi/spi-nor-ids.c | 5 +++-- >> 1 file changed, 3 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c >> index 0383175beb5..03596d38e6e 100644 >> --- a/drivers/mtd/spi/spi-nor-ids.c >> +++ b/drivers/mtd/spi/spi-nor-ids.c >> @@ -595,13 +595,14 @@ const struct flash_info spi_nor_ids[] = { >> #endif >> #ifdef CONFIG_SPI_FLASH_XMC >> /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ >> + { INFO("XM25QH01D", 0x204021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, >> { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, >> { INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, >> { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, >> - { INFO("XM25QU128C", 0x204118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, >> { INFO("XM25QH256C", 0x204019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, >> - { INFO("XM25QU256C", 0x204119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, >> { INFO("XM25QH512C", 0x204020, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, >> + { INFO("XM25QU128C", 0x204118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, >> + { INFO("XM25QU256C", 0x204119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, >> { INFO("XM25QU512C", 0x204120, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, >I'm sorry, my original suggestion was unclear. > >If you want to sort the whole XMC part list, then please do 2-patch >series, sort the list in patch 1/2 and then add the chip in 2/2 .