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[189.203.103.235]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c90f5fedbbsm4810151a34.10.2025.12.01.08.51.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Dec 2025 08:51:23 -0800 (PST) Date: Mon, 1 Dec 2025 10:51:22 -0600 From: Tom Rini To: Brian Sune Cc: Jan Kiszka , Chee Tien Fong , u-boot@lists.denx.de Subject: Re: [PATCH v2] Fix socfpga GEN5 boot by spl+u-boot sfp on RAW Message-ID: <20251201165122.GH303283@bill-the-cat> References: <20251129064818.1587-1-briansune@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="ri9XMpKZfqpVtWFP" Content-Disposition: inline In-Reply-To: <20251129064818.1587-1-briansune@gmail.com> X-Clacks-Overhead: GNU Terry Pratchett X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean --ri9XMpKZfqpVtWFP Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sat, Nov 29, 2025 at 02:48:18PM +0800, Brian Sune wrote: > Thanks to Jan Kiszka had provided info on > u-boot is not able to boot by u-boot-with-spl.sfp. >=20 > All three TYPE, NUM, OFFSET mode methods > are nonfunctional on combined raw boot. >=20 > The major cause is spl+u-boot structure is > defined as 4x[spl+zero_pad] + u-boot.img. > Deal to this configuration since GEN5 is used, > the spl would require to seek by an offset > on top of the spl offset. This means for > each spl=3D0x10000 the offset is 0x40000. >=20 > However latest u-boot do not consider this > major structure on GEN5 socfpga. > Meanwhile, the default include file as Jan > pointed out is completely wrong syntax and > caused issue. >=20 > Combining both concepts, the minimum fix > patch is provide as follows. >=20 > 1) Offset is control and default set to a > proper offset under: > SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET >=20 > 2) Only GEN5 socfpga will be affected and > minimized contamination on other devices. >=20 > 3) Only one compuatation adjustment is made > on spl_mmc_load. And simply introduce the > offset adding by the kconfig offset control. > It should be 0 by default and gate as well. > So no possible harm should be done. This sounds like a tricky problem to solve in a "nice" looking way. The first thing that's unclear to me is, which of SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR, SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION or SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is being used here? --=20 Tom --ri9XMpKZfqpVtWFP Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTzzqh0PWDgGS+bTHor4qD1Cr/kCgUCaS3HiQAKCRAr4qD1Cr/k CvesAP9p9Fbxl7KxAEWos60QQ+D3xhnjNTBmqdsISAkkWFp4/gEA2Dt7h0GVzSt/ EAtiWlHd/DJAB5Tpop6r1bASShvaZws= =pJaN -----END PGP SIGNATURE----- --ri9XMpKZfqpVtWFP--