Re: [PATCH v2 2/5] riscv: dts: starfive: add Orange Pi RV

Sumit Garg
2025-12-29T04:33:09Z

On Fri, Dec 26, 2025 at 11:30:03AM -0800, E Shattow wrote:
> From: Icenowy Zheng <uwu@icenowy.me>
>
> Orange Pi RV is a SBC based on the StarFive VisionFive 2 board.
>
> Orange Pi RV features:
>
> - StarFive JH7110 SoC
> - GbE port connected to JH7110 GMAC0 via YT8531 PHY
> - 4x USB ports via VL805 PCIe USB controller connected to JH7110 pcie0
> - M.2 M-key slot connected to JH7110 pcie1
> - HDMI video output
> - 3.5mm audio output
> - Ampak AP6256 SDIO Wi-Fi/Bluetooth module on mmc0
> - microSD slot on mmc1
> - SPI NOR flash memory
> - 24c02 EEPROM (read only by default)
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> Signed-off-by: E Shattow <e@freeshell.de>
> [conor: amend comment to say what's missing]
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>
> [ upstream commit: 5b70764e10190d57e6cd3287d3a3b06f8c89f69c ]
>
> (cherry picked from commit ca39a8e36acbe7d258cadee4ae703fbaac60e18b)
> ---
> .../src/riscv/starfive/jh7110-orangepi-rv.dts | 76 +++++++++++++++++++
> 1 file changed, 76 insertions(+)
> create mode 100644 dts/upstream/src/riscv/starfive/jh7110-orangepi-rv.dts

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

-Sumit

>
> diff --git a/dts/upstream/src/riscv/starfive/jh7110-orangepi-rv.dts b/dts/upstream/src/riscv/starfive/jh7110-orangepi-rv.dts
> new file mode 100644
> index 00000000000..053c35992ec
> --- /dev/null
> +++ b/dts/upstream/src/riscv/starfive/jh7110-orangepi-rv.dts
> @@ -0,0 +1,76 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2025 Icenowy Zheng <uwu@icenowy.me>
> + */
> +
> +/dts-v1/;
> +#include "jh7110-common.dtsi"
> +
> +/ {
> + model = "Xunlong Orange Pi RV";
> + compatible = "xunlong,orangepi-rv", "starfive,jh7110";
> +
> + /* This regulator is always on by hardware */
> + reg_vcc3v3_pcie: regulator-vcc3v3-pcie {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3-pcie";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + wifi_pwrseq: wifi-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&sysgpio 62 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +&gmac0 {
> + assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
> + assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
> + starfive,tx-use-rgmii-clk;
> + status = "okay";
> +};
> +
> +&mmc0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cap-sd-highspeed;
> + mmc-pwrseq = <&wifi_pwrseq>;
> + vmmc-supply = <&reg_vcc3v3_pcie>;
> + vqmmc-supply = <&vcc_3v3>;
> + status = "okay";
> +
> + ap6256: wifi@1 {
> + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
> + reg = <1>;
> + /* TODO: out-of-band IRQ on GPIO21, lacking pinctrl support */
> + };
> +};
> +
> +&mmc1 {
> + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_HIGH>;
> +};
> +
> +&pcie0 {
> + status = "okay";
> +};
> +
> +&pcie1 {
> + status = "okay";
> +};
> +
> +&phy0 {
> + rx-internal-delay-ps = <1500>;
> + tx-internal-delay-ps = <1500>;
> + motorcomm,rx-clk-drv-microamp = <3970>;
> + motorcomm,rx-data-drv-microamp = <2910>;
> + motorcomm,tx-clk-adj-enabled;
> + motorcomm,tx-clk-10-inverted;
> + motorcomm,tx-clk-100-inverted;
> + motorcomm,tx-clk-1000-inverted;
> +};
> +
> +&pwmdac {
> + status = "okay";
> +};
> --
> 2.50.0
>