[PATCH 0/2] clk: renesas: Fix booting Linux on R8A77995 D3

[PATCH 0/2] clk: renesas: Fix booting Linux on R8A77995 D3

[Niklas Söderlund]

Hello,

While trying to update stock U-Boot to latest upstream I ran into 
trouble as anything after v2023.07 failed to boot Linux. U-Boot itself 
function as it should.

	NOTICE:  BL2: R-Car Gen3 Initial Program Loader(CA53) Rev.4.0.0
	NOTICE:  BL2: PRR is R-Car D3 Ver.1.0
	NOTICE:  BL2: PLL1 SSCG Clock select
	NOTICE:  BL2: Board is Draak Rev.1.0
	NOTICE:  BL2: Boot device is HyperFlash(80MHz)
	NOTICE:  BL2: LCM state is CM
	NOTICE:  BL2: DDR1866(rev.0.02)
	NOTICE:  BL2: QoS is default setting(rev.0.05)
	NOTICE:  BL2: CH0: 400000000 - 41fffffff, 512 MiB
	NOTICE:  BL2: FDT at 0xe6313e80
	NOTICE:  BL2: v2.14.0(release):sandbox/v2.14
	NOTICE:  BL2: Built : 00:36:13, Dec 27 2025
	NOTICE:  BL2: Normal boot
	NOTICE:  BL2: dst=0xe6313500 src=0x8180000 len=512(0x200)
	NOTICE:  BL2: dst=0x43f00000 src=0x8180400 len=6144(0x1800)
	NOTICE:  rcar_file_len: len: 0x0003e000
	NOTICE:  BL2: dst=0x44000000 src=0x81c0000 len=253952(0x3e000)
	NOTICE:  rcar_file_len: len: 0x00100000
	NOTICE:  BL2: dst=0x50000000 src=0x8640000 len=1048576(0x100000)
	NOTICE:  BL2: Booting BL31


	U-Boot 2026.01-rc5-00004-ga434270faaa2 (Dec 28 2025 - 01:38:34 +0100)

	CPU:   Renesas Electronics R8A77995 rev 1.0
	Model: Renesas Draak board rev 1.0
	DRAM:  384 MiB
	Core:  60 devices, 23 uclasses, devicetree: separate
	Flash: 64 MiB
	MMC:   mmc@ee140000: 0
	Loading Environment from MMC... Reading from MMC(0)... OK
	In:    serial@e6e88000
	Out:   serial@e6e88000
	Err:   serial@e6e88000
	Net:   eth0: ethernet@e6800000
	Hit any key to stop autoboot: 0
	ethernet@e6800000 Waiting for PHY auto negotiation to complete...... done
	BOOTP broadcast 1
	BOOTP broadcast 2
	DHCP client bound to address 10.0.1.14 (255 ms)
	Using ethernet@e6800000 device
	TFTP from server 10.0.1.1; our IP address is 10.0.1.14
	Filename 'gen3/gen3.itb'.
	Load address: 0x58000000
	Loading: ##################################################  11.5 MiB
		 14.2 MiB/s
	done
	Bytes transferred = 12020010 (b7692a hex)
	## Loading kernel (any) from FIT Image at 58000000 ...
	   Using 'conf-r8a77995-draak.dtb' configuration
	   Trying 'kernel' kernel subimage
	     Description:  Linux kernel
	     Type:         Kernel Image
	     Compression:  gzip compressed
	     Data Start:   0x580000cc
	     Data Size:    11650399 Bytes = 11.1 MiB
	     Architecture: AArch64
	     OS:           Linux
	     Load Address: 0x51000000
	     Entry Point:  0x51000000
	     Hash algo:    crc32
	     Hash value:   7d1cb66c
	     Hash algo:    sha1
	     Hash value:   7d7bfeb112fea08c86f8a67caf08b74d021ef7d6
	   Verifying Hash Integrity ... crc32+ sha1+ OK
	## Loading fdt (any) from FIT Image at 58000000 ...
	   Using 'conf-r8a77995-draak.dtb' configuration
	   Trying 'fdt-r8a77995-draak.dtb' fdt subimage
	     Description:  Flattened Device Tree r8a77995-draak.dtb
	     Type:         Flat Device Tree
	     Compression:  gzip compressed
	     Data Start:   0x58b3c5d4
	     Data Size:    10124 Bytes = 9.9 KiB
	     Architecture: AArch64
	     Load Address: 0x48000000
	     Hash algo:    crc32
	     Hash value:   916adb0b
	     Hash algo:    sha1
	     Hash value:   499bee16ef678e98a3d1de25860c9221657a4301
	   Verifying Hash Integrity ... crc32+ sha1+ OK
	   Loading fdt from 0x58b3c5d4 to 0x48000000
	   Uncompressing Flat Device Tree to 48000000
	   Booting using the fdt blob at 0x48000000
	Working FDT set to 48000000
	   Uncompressing Kernel Image to 51000000
	   Loading Device Tree to 0000000057ff1000, end 0000000057fff2dd ... OK
	Working FDT set to 57ff1000

	Starting kernel ...

	[ SYSTEM IS DEAD ]

Turns out changes to properly turn modules on/off had uncovered a bug in 
the tables in r8a77995-cpg-mssr driver. Never versions of the datasheet 
have made it clear some module its are not available on D3, and setting 
them (as U-Boot do since v2023.10) prevents the system from booting 
Linux. Fixing this and the system boots as it should.

A huge thanks to Marek Vasut who helped me debug this and aided me to 
get up to speed with the U-Boot drivers!

Niklas Söderlund (2):
  clk: renesas: Do not enable MSTP4 modules on R8A77995 D3
  clk: renesas: Do not disable realtime modules on R8A77995 D3

 drivers/clk/renesas/r8a77995-cpg-mssr.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

-- 
2.52.0

[PATCH 1/2] clk: renesas: Do not enable MSTP4 modules on R8A77995 D3

[Niklas Söderlund]

Since commit a2bd99549c61 ("clk: renesas: Tear clock controller down
last before booting OS") enabling the module gated by bit 8 in MSTP4
prevents Linux from booting. Furthermore bits 8 and 7 of MSTP4 where
only documented in early versions of the datasheet and have since been
removed, do the same in the driver to allow Linux to boot.

Suggested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
 drivers/clk/renesas/r8a77995-cpg-mssr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index f49faa47cb37..0a59a19cb227 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -220,7 +220,7 @@ static const struct mstp_stop_table r8a77995_mstp_table[] = {
 	{ 0x03e01000, 0x0, 0x03e01000, 0 },
 	{ 0x000e2fdc, 0x2000, 0x000e2fd8, 0 },
 	{ 0xc00014df, 0x400, 0xc00014df, 0 },
-	{ 0x80000004, 0x180, 0x80000004, 0 },
+	{ 0x80000004, 0x0, 0x80000004, 0 },
 	{ 0x40d20004, 0x0, 0x40d20004, 0 },
 	{ 0x08c0008c, 0x0, 0x08c0008c, 0 },
 	{ 0x09941c18, 0x0, 0x09941c18, 0 },
-- 
2.52.0

Re: [PATCH 1/2] clk: renesas: Do not enable MSTP4 modules on R8A77995 D3

[Marek Vasut]

On 12/28/25 2:03 AM, Niklas Söderlund wrote:
> Since commit a2bd99549c61 ("clk: renesas: Tear clock controller down
> last before booting OS") enabling the module gated by bit 8 in MSTP4
> prevents Linux from booting. Furthermore bits 8 and 7 of MSTP4 where
> only documented in early versions of the datasheet and have since been
> removed, do the same in the driver to allow Linux to boot.
> 
> Suggested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> ---
>   drivers/clk/renesas/r8a77995-cpg-mssr.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
> index f49faa47cb37..0a59a19cb227 100644
> --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
> @@ -220,7 +220,7 @@ static const struct mstp_stop_table r8a77995_mstp_table[] = {
>   	{ 0x03e01000, 0x0, 0x03e01000, 0 },
>   	{ 0x000e2fdc, 0x2000, 0x000e2fd8, 0 },
>   	{ 0xc00014df, 0x400, 0xc00014df, 0 },
> -	{ 0x80000004, 0x180, 0x80000004, 0 },
> +	{ 0x80000004, 0x0, 0x80000004, 0 },
Should we disable both BIT(8) and BIT(7), or only the BIT(8) that hangs 
the system ?

Re: [PATCH 1/2] clk: renesas: Do not enable MSTP4 modules on R8A77995 D3

[Niklas Söderlund]

On 2025-12-28 03:03:31 +0100, Marek Vasut wrote:
> On 12/28/25 2:03 AM, Niklas Söderlund wrote:
> > Since commit a2bd99549c61 ("clk: renesas: Tear clock controller down
> > last before booting OS") enabling the module gated by bit 8 in MSTP4
> > prevents Linux from booting. Furthermore bits 8 and 7 of MSTP4 where
> > only documented in early versions of the datasheet and have since been
> > removed, do the same in the driver to allow Linux to boot.
> > 
> > Suggested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> > ---
> >   drivers/clk/renesas/r8a77995-cpg-mssr.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
> > index f49faa47cb37..0a59a19cb227 100644
> > --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
> > @@ -220,7 +220,7 @@ static const struct mstp_stop_table r8a77995_mstp_table[] = {
> >   	{ 0x03e01000, 0x0, 0x03e01000, 0 },
> >   	{ 0x000e2fdc, 0x2000, 0x000e2fd8, 0 },
> >   	{ 0xc00014df, 0x400, 0xc00014df, 0 },
> > -	{ 0x80000004, 0x180, 0x80000004, 0 },
> > +	{ 0x80000004, 0x0, 0x80000004, 0 },
> Should we disable both BIT(8) and BIT(7), or only the BIT(8) that hangs the
> system ?

I think we shall remove both as the datasheet removes both, no?

-- 
Kind Regards,
Niklas Söderlund

Re: [PATCH 1/2] clk: renesas: Do not enable MSTP4 modules on R8A77995 D3

[Marek Vasut]

On 12/28/25 9:12 AM, Niklas Söderlund wrote:
> On 2025-12-28 03:03:31 +0100, Marek Vasut wrote:
>> On 12/28/25 2:03 AM, Niklas Söderlund wrote:
>>> Since commit a2bd99549c61 ("clk: renesas: Tear clock controller down
>>> last before booting OS") enabling the module gated by bit 8 in MSTP4
>>> prevents Linux from booting. Furthermore bits 8 and 7 of MSTP4 where
>>> only documented in early versions of the datasheet and have since been
>>> removed, do the same in the driver to allow Linux to boot.
>>>
>>> Suggested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
>>> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
>>> ---
>>>    drivers/clk/renesas/r8a77995-cpg-mssr.c | 2 +-
>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
>>> index f49faa47cb37..0a59a19cb227 100644
>>> --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
>>> +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
>>> @@ -220,7 +220,7 @@ static const struct mstp_stop_table r8a77995_mstp_table[] = {
>>>    	{ 0x03e01000, 0x0, 0x03e01000, 0 },
>>>    	{ 0x000e2fdc, 0x2000, 0x000e2fd8, 0 },
>>>    	{ 0xc00014df, 0x400, 0xc00014df, 0 },
>>> -	{ 0x80000004, 0x180, 0x80000004, 0 },
>>> +	{ 0x80000004, 0x0, 0x80000004, 0 },
>> Should we disable both BIT(8) and BIT(7), or only the BIT(8) that hangs the
>> system ?
> 
> I think we shall remove both as the datasheet removes both, no?
Drop only bit 8 please, bit 7 is set so keep it set.

[PATCH 2/2] clk: renesas: Do not disable realtime modules on R8A77995 D3

[Niklas Söderlund]

Later versions of the datasheet makes it clear D3 do not have any
realtime module stop control registers (RMSTPCRx). Remove the
manipulation of them from the module clock table to match this.

Suggested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
 drivers/clk/renesas/r8a77995-cpg-mssr.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index 0a59a19cb227..736812e04d0b 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -216,18 +216,18 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
 };
 
 static const struct mstp_stop_table r8a77995_mstp_table[] = {
-	{ 0x00210000, 0x0, 0x00210000, 0 },
-	{ 0x03e01000, 0x0, 0x03e01000, 0 },
-	{ 0x000e2fdc, 0x2000, 0x000e2fd8, 0 },
-	{ 0xc00014df, 0x400, 0xc00014df, 0 },
-	{ 0x80000004, 0x0, 0x80000004, 0 },
-	{ 0x40d20004, 0x0, 0x40d20004, 0 },
-	{ 0x08c0008c, 0x0, 0x08c0008c, 0 },
-	{ 0x09941c18, 0x0, 0x09941c18, 0 },
-	{ 0x00801087, 0x0, 0x00801087, 0 },
-	{ 0xf143dfc0, 0x0, 0xf143dfc0, 0 },
-	{ 0x063e1820, 0x0, 0x063e1820, 0 },
-	{ 0x00000000, 0x0, 0x00000000, 0 },
+	{ 0x00210000, 0x0, 0, 0 },
+	{ 0x03e01000, 0x0, 0, 0 },
+	{ 0x000e2fdc, 0x2000, 0, 0 },
+	{ 0xc00014df, 0x400, 0, 0 },
+	{ 0x80000004, 0x0, 0, 0 },
+	{ 0x40d20004, 0x0, 0, 0 },
+	{ 0x08c0008c, 0x0, 0, 0 },
+	{ 0x09941c18, 0x0, 0, 0 },
+	{ 0x00801087, 0x0, 0, 0 },
+	{ 0xf143dfc0, 0x0, 0, 0 },
+	{ 0x063e1820, 0x0, 0, 0 },
+	{ 0x00000000, 0x0, 0, 0 },
 };
 
 static const void *r8a77995_get_pll_config(const u32 cpg_mode)
-- 
2.52.0

Re: [PATCH 2/2] clk: renesas: Do not disable realtime modules on R8A77995 D3

[Marek Vasut]

On 12/28/25 2:03 AM, Niklas Söderlund wrote:
> Later versions of the datasheet makes it clear D3 do not have any
> realtime module stop control registers (RMSTPCRx). Remove the
> manipulation of them from the module clock table to match this.
> 
> Suggested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> ---
>   drivers/clk/renesas/r8a77995-cpg-mssr.c | 24 ++++++++++++------------
>   1 file changed, 12 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
> index 0a59a19cb227..736812e04d0b 100644
> --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
> @@ -216,18 +216,18 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
>   };
>   
>   static const struct mstp_stop_table r8a77995_mstp_table[] = {
> -	{ 0x00210000, 0x0, 0x00210000, 0 },
> -	{ 0x03e01000, 0x0, 0x03e01000, 0 },
> -	{ 0x000e2fdc, 0x2000, 0x000e2fd8, 0 },
> -	{ 0xc00014df, 0x400, 0xc00014df, 0 },
> -	{ 0x80000004, 0x0, 0x80000004, 0 },
> -	{ 0x40d20004, 0x0, 0x40d20004, 0 },
> -	{ 0x08c0008c, 0x0, 0x08c0008c, 0 },
> -	{ 0x09941c18, 0x0, 0x09941c18, 0 },
> -	{ 0x00801087, 0x0, 0x00801087, 0 },
> -	{ 0xf143dfc0, 0x0, 0xf143dfc0, 0 },
> -	{ 0x063e1820, 0x0, 0x063e1820, 0 },
> -	{ 0x00000000, 0x0, 0x00000000, 0 },
> +	{ 0x00210000, 0x0, 0, 0 },
> +	{ 0x03e01000, 0x0, 0, 0 },
> +	{ 0x000e2fdc, 0x2000, 0, 0 },
> +	{ 0xc00014df, 0x400, 0, 0 },
> +	{ 0x80000004, 0x0, 0, 0 },
> +	{ 0x40d20004, 0x0, 0, 0 },
> +	{ 0x08c0008c, 0x0, 0, 0 },
> +	{ 0x09941c18, 0x0, 0, 0 },
> +	{ 0x00801087, 0x0, 0, 0 },
> +	{ 0xf143dfc0, 0x0, 0, 0 },
> +	{ 0x063e1820, 0x0, 0, 0 },
> +	{ 0x00000000, 0x0, 0, 0 },
>   };
>   
>   static const void *r8a77995_get_pll_config(const u32 cpg_mode)

You likely also need this part to avoid any RMSTPCR access:

diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c 
b/drivers/clk/renesas/renesas-cpg-mssr.c
index 39ff4541c1e..4b07dbb3277 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -127,7 +127,8 @@ int renesas_clk_remove(void __iomem *base, struct 
cpg_mssr_info *info)
                                 info->mstp_table[i].sdis,
                                 info->mstp_table[i].sen);

-               if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4)
+               if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4 ||
+                   renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77995)
                         continue;

                 clrsetbits_le32(base + RMSTPCR(i),

Re: [PATCH 2/2] clk: renesas: Do not disable realtime modules on R8A77995 D3

[Niklas Söderlund]

On 2025-12-28 03:04:35 +0100, Marek Vasut wrote:
> On 12/28/25 2:03 AM, Niklas Söderlund wrote:
> > Later versions of the datasheet makes it clear D3 do not have any
> > realtime module stop control registers (RMSTPCRx). Remove the
> > manipulation of them from the module clock table to match this.
> > 
> > Suggested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> > ---
> >   drivers/clk/renesas/r8a77995-cpg-mssr.c | 24 ++++++++++++------------
> >   1 file changed, 12 insertions(+), 12 deletions(-)
> > 
> > diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
> > index 0a59a19cb227..736812e04d0b 100644
> > --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
> > @@ -216,18 +216,18 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
> >   };
> >   static const struct mstp_stop_table r8a77995_mstp_table[] = {
> > -	{ 0x00210000, 0x0, 0x00210000, 0 },
> > -	{ 0x03e01000, 0x0, 0x03e01000, 0 },
> > -	{ 0x000e2fdc, 0x2000, 0x000e2fd8, 0 },
> > -	{ 0xc00014df, 0x400, 0xc00014df, 0 },
> > -	{ 0x80000004, 0x0, 0x80000004, 0 },
> > -	{ 0x40d20004, 0x0, 0x40d20004, 0 },
> > -	{ 0x08c0008c, 0x0, 0x08c0008c, 0 },
> > -	{ 0x09941c18, 0x0, 0x09941c18, 0 },
> > -	{ 0x00801087, 0x0, 0x00801087, 0 },
> > -	{ 0xf143dfc0, 0x0, 0xf143dfc0, 0 },
> > -	{ 0x063e1820, 0x0, 0x063e1820, 0 },
> > -	{ 0x00000000, 0x0, 0x00000000, 0 },
> > +	{ 0x00210000, 0x0, 0, 0 },
> > +	{ 0x03e01000, 0x0, 0, 0 },
> > +	{ 0x000e2fdc, 0x2000, 0, 0 },
> > +	{ 0xc00014df, 0x400, 0, 0 },
> > +	{ 0x80000004, 0x0, 0, 0 },
> > +	{ 0x40d20004, 0x0, 0, 0 },
> > +	{ 0x08c0008c, 0x0, 0, 0 },
> > +	{ 0x09941c18, 0x0, 0, 0 },
> > +	{ 0x00801087, 0x0, 0, 0 },
> > +	{ 0xf143dfc0, 0x0, 0, 0 },
> > +	{ 0x063e1820, 0x0, 0, 0 },
> > +	{ 0x00000000, 0x0, 0, 0 },
> >   };
> >   static const void *r8a77995_get_pll_config(const u32 cpg_mode)
> 
> You likely also need this part to avoid any RMSTPCR access:

Indeed, thanks! I will respin when we agree about the bits in 1/2.

> 
> diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c
> b/drivers/clk/renesas/renesas-cpg-mssr.c
> index 39ff4541c1e..4b07dbb3277 100644
> --- a/drivers/clk/renesas/renesas-cpg-mssr.c
> +++ b/drivers/clk/renesas/renesas-cpg-mssr.c
> @@ -127,7 +127,8 @@ int renesas_clk_remove(void __iomem *base, struct
> cpg_mssr_info *info)
>                                 info->mstp_table[i].sdis,
>                                 info->mstp_table[i].sen);
> 
> -               if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4)
> +               if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4 ||
> +                   renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77995)
>                         continue;
> 
>                 clrsetbits_le32(base + RMSTPCR(i),

-- 
Kind Regards,
Niklas Söderlund