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[34.81.118.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3a8770e66sm40000615ad.42.2026.01.01.09.54.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jan 2026 09:54:41 -0800 (PST) From: Kuan-Wei Chiu To: alison.wang@nxp.com, angelo@kernel-space.org, trini@konsulko.com Cc: me@ziyao.cc, daniel@0x0f.com, heinrich.schuchardt@canonical.com, jserv@ccns.ncku.edu.tw, eleanor15x@gmail.com, u-boot@lists.denx.de, Kuan-Wei Chiu Subject: [PATCH v4 2/6] timer: Add Goldfish timer driver Date: Thu, 1 Jan 2026 17:54:16 +0000 Message-ID: <20260101175420.4118024-3-visitorckw@gmail.com> X-Mailer: git-send-email 2.52.0.358.g0dd7633a29-goog In-Reply-To: <20260101175420.4118024-1-visitorckw@gmail.com> References: <20260101175420.4118024-1-visitorckw@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Thu, 01 Jan 2026 22:15:35 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add support for the Goldfish timer driver. This driver utilizes the Goldfish RTC hardware to provide a nanosecond-resolution timer. This virtual device is commonly found in QEMU virtual machines (such as the m68k virt machine) and Android emulators. The driver implements the standard U-Boot timer UCLASS interface, exposing a 64-bit monotonically increasing counter with a 1GHz clock rate derived from the RTC registers. Signed-off-by: Kuan-Wei Chiu Tested-by: Daniel Palmer Reviewed-by: Yao Zi --- Changes in v4: - Sort headers alphabetically. - Add comment explaining read latching behavior. - Support DT probing with platform data as a fallback. MAINTAINERS | 6 +++ drivers/timer/Kconfig | 8 ++++ drivers/timer/Makefile | 1 + drivers/timer/goldfish_timer.c | 81 ++++++++++++++++++++++++++++++++++ include/goldfish_timer.h | 13 ++++++ 5 files changed, 109 insertions(+) create mode 100644 drivers/timer/goldfish_timer.c create mode 100644 include/goldfish_timer.h diff --git a/MAINTAINERS b/MAINTAINERS index da4a6e4d518..fcc437a53ce 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1265,6 +1265,12 @@ S: Maintained F: drivers/serial/serial_goldfish.c F: include/goldfish_tty.h +GOLDFISH TIMER DRIVER +M: Kuan-Wei Chiu +S: Maintained +F: drivers/timer/goldfish_timer.c +F: include/goldfish_timer.h + I2C M: Heiko Schocher S: Maintained diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index f9511503b02..a84a0dc0539 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -340,4 +340,12 @@ config STARFIVE_TIMER Select this to enable support for the timer found on Starfive SoC. +config GOLDFISH_TIMER + bool "Goldfish Timer support" + depends on TIMER + help + Select this to enable support for the Goldfish Timer. + It uses the Goldfish RTC hardware to provide a nanosecond-resolution + timer, commonly found in QEMU virt machines. + endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index a72e411fb2f..d8b3f2b65d4 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -36,3 +36,4 @@ obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o obj-$(CONFIG_IMX_GPT_TIMER) += imx-gpt-timer.o obj-$(CONFIG_XILINX_TIMER) += xilinx-timer.o obj-$(CONFIG_STARFIVE_TIMER) += starfive-timer.o +obj-$(CONFIG_GOLDFISH_TIMER) += goldfish_timer.o diff --git a/drivers/timer/goldfish_timer.c b/drivers/timer/goldfish_timer.c new file mode 100644 index 00000000000..63946b9ed97 --- /dev/null +++ b/drivers/timer/goldfish_timer.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025, Kuan-Wei Chiu + * + * Goldfish Timer driver + */ + +#include +#include +#include +#include +#include +#include + +struct goldfish_timer_priv { + void __iomem *base; +}; + +/* Goldfish RTC registers used as Timer */ +#define TIMER_TIME_LOW 0x00 +#define TIMER_TIME_HIGH 0x04 + +static u64 goldfish_timer_get_count(struct udevice *dev) +{ + struct goldfish_timer_priv *priv = dev_get_priv(dev); + u32 low, high; + u64 time; + + /* + * TIMER_TIME_HIGH is only updated when TIMER_TIME_LOW is read. + * We must read LOW before HIGH to latch the high 32-bit value + * and ensure a consistent 64-bit timestamp. + */ + low = readl(priv->base + TIMER_TIME_LOW); + high = readl(priv->base + TIMER_TIME_HIGH); + + time = ((u64)high << 32) | low; + + return time; +} + +static int goldfish_timer_probe(struct udevice *dev) +{ + struct goldfish_timer_priv *priv = dev_get_priv(dev); + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct goldfish_timer_plat *plat; + fdt_addr_t addr; + + addr = dev_read_addr(dev); + if (addr != FDT_ADDR_T_NONE) { + priv->base = map_sysmem(addr, 0x20); + } else { + plat = dev_get_plat(dev); + if (!plat) + return -EINVAL; + priv->base = plat->base; + } + + /* Goldfish RTC counts in nanoseconds, so the rate is 1GHz */ + uc_priv->clock_rate = 1000000000; + + return 0; +} + +static const struct timer_ops goldfish_timer_ops = { + .get_count = goldfish_timer_get_count, +}; + +static const struct udevice_id goldfish_timer_ids[] = { + { .compatible = "google,goldfish-rtc" }, + { } +}; + +U_BOOT_DRIVER(goldfish_timer) = { + .name = "goldfish_timer", + .id = UCLASS_TIMER, + .of_match = goldfish_timer_ids, + .ops = &goldfish_timer_ops, + .probe = goldfish_timer_probe, + .priv_auto = sizeof(struct goldfish_timer_priv), +}; diff --git a/include/goldfish_timer.h b/include/goldfish_timer.h new file mode 100644 index 00000000000..2ea28170759 --- /dev/null +++ b/include/goldfish_timer.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2025, Kuan-Wei Chiu + */ + +#ifndef _GOLDFISH_TIMER_H_ +#define _GOLDFISH_TIMER_H_ + +struct goldfish_timer_plat { + void __iomem *base; +}; + +#endif /* _GOLDFISH_TIMER_H_ */ -- 2.52.0.358.g0dd7633a29-goog