[PATCH 0/2] clk: versaclock: Fix clock parentage issues

[PATCH 0/2] clk: versaclock: Fix clock parentage issues

[Sean Anderson]

Fix two issues I found while adding 5P49V6975 support.


Sean Anderson (2):
  clk: versaclock: Fix clk_get_rate
  clk: versaclock: Fix internal crystal clock

 drivers/clk/clk_versaclock.c | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

-- 
2.35.1.1320.gc452695387.dirty

base-commit: 1d59479362c7f6a681a2b3c14e97edff7c0f5a7c
branch: versaclk_fix

[PATCH 1/2] clk: versaclock: Fix clk_get_rate

[Sean Anderson]

Devicetree clock references point at the main versaclock device. We
must determine the parent clock manually, as it depends on the clock id.
The device parent of the versaclock will generally be an I2C bus and not
another clock.

Fixes: dcf2cee77f2 ("clk: clk_versaclock: Add support for versaclock driver")
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
---

 drivers/clk/clk_versaclock.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk_versaclock.c b/drivers/clk/clk_versaclock.c
index 19a787eaf0c..7a1052a1be7 100644
--- a/drivers/clk/clk_versaclock.c
+++ b/drivers/clk/clk_versaclock.c
@@ -633,7 +633,15 @@ static unsigned long vc5_clk_out_set_rate(struct clk *hw, unsigned long rate)
 
 static unsigned long vc5_clk_out_get_rate(struct clk *hw)
 {
-	return clk_get_parent_rate(hw);
+	struct udevice *dev;
+	struct vc5_driver_data *vc;
+	struct clk *parent;
+
+	uclass_get_device_by_name(UCLASS_CLK, clk_hw_get_name(hw), &dev);
+	vc = dev_get_priv(dev);
+	parent = clk_get_parent(&vc->clk_out[hw->id].hw);
+
+	return clk_get_rate(parent);
 }
 
 static const struct clk_ops vc5_clk_out_ops = {
-- 
2.35.1.1320.gc452695387.dirty

[PATCH 2/2] clk: versaclock: Fix internal crystal clock

[Sean Anderson]

When pin_xin does not exist and the chip supports an internal crystal,
we must create it. Do so, and don't try to enable an error pointer.

Fixes: dcf2cee77f2 ("clk: clk_versaclock: Add support for versaclock driver")
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
---

 drivers/clk/clk_versaclock.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/clk_versaclock.c b/drivers/clk/clk_versaclock.c
index 7a1052a1be7..be01f34ceec 100644
--- a/drivers/clk/clk_versaclock.c
+++ b/drivers/clk/clk_versaclock.c
@@ -889,23 +889,22 @@ int versaclock_probe(struct udevice *dev)
 
 	vc5->chip_info = chip;
 	vc5->pin_xin = devm_clk_get(dev, "xin");
-
-	if (IS_ERR(vc5->pin_xin))
-		dev_dbg(dev, "failed to get xin clock\n");
-
-	ret = clk_enable(vc5->pin_xin);
-	if (ret)
-		dev_dbg(dev, "failed to enable XIN clock\n");
-
 	vc5->pin_clkin = devm_clk_get(dev, "clkin");
 
 	/* Register clock input mux */
 	if (!IS_ERR(vc5->pin_xin)) {
+		ret = clk_enable(vc5->pin_xin);
+		if (ret)
+			dev_dbg(dev, "failed to enable XIN clock\n");
 		vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
 	} else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) {
+		vc5->pin_xin = clk_register_fixed_rate(NULL, "internal-xtal",
+						       25000000);
 		if (IS_ERR(vc5->pin_xin))
 			return PTR_ERR(vc5->pin_xin);
 		vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
+	} else {
+		return PTR_ERR(vc5->pin_xin);
 	}
 
 	mux_name = versaclock_get_name(dev->name, "mux", -1);
-- 
2.35.1.1320.gc452695387.dirty