[PATCH v3 7/9] pinctrl: sunxi: a733: add initial support

Yixun Lan
2026-01-13T04:03:54Z

Introduce pinctrl driver for A733 SoC, but only limited devices are
supported which includes GMAC, MMC, SPI, UART.

Setup an offset 0x80 for virtual PA port, as A733 changes the register
layout, with this adjustment, all other ports can be found correctly.

Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
drivers/pinctrl/sunxi/Kconfig | 10 ++++++
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 57 ++++++++++++++++++++++++++++++++++-
2 files changed, 66 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 54314992299..0e48a71e8b5 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -149,4 +149,14 @@ config PINCTRL_SUN55I_A523_R
default MACH_SUN55I_A523
select PINCTRL_SUNXI

+config PINCTRL_SUN60I_A733
+ bool "Support for the Allwinner A733 PIO"
+ default MACH_SUN60I_A733
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN60I_A733_R
+ bool "Support for the Allwinner A733 R-PIO"
+ default MACH_SUN60I_A733
+ select PINCTRL_SUNXI
+
endif
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index fd357ab0d4e..b6c901f14c1 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -30,6 +30,7 @@ struct sunxi_pinctrl_function {

struct sunxi_pinctrl_desc {
const struct sunxi_pinctrl_function *functions;
+ u32 pio_offset;
u8 num_functions;
u8 first_bank;
u8 num_banks;
@@ -195,7 +196,7 @@ static int sunxi_pinctrl_bind(struct udevice *dev)
return -EINVAL;
dev_set_priv(dev, desc);

- plat->base = dev_read_addr_ptr(dev);
+ plat->base = dev_read_addr_ptr(dev) + desc->pio_offset;

ret = device_bind_driver_to_node(dev, "gpio_sunxi", dev->name,
dev_ofnode(dev), &gpio_dev);
@@ -782,6 +783,32 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun55i_a523_pinctrl_desc =
.num_banks = 11,
};

+static const struct sunxi_pinctrl_function sun60i_a733_pinctrl_functions[] = {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "gmac0", 5 }, /* PH0-PH15 */
+ { "gmac1", 5 }, /* PJ0-PJ15 */
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 2 }, /* PG0-PG5 */
+ { "mmc2", 3 }, /* PC0, PC1, PC5, PC6, PC8-PC11, PC13-PC16 */
+ { "mmc3", 4 }, /* PC0, PC1, PC5, PC6, PC8-PC11, PC13-PC16 */
+ { "spi0", 5 }, /* PC2-PC4, PC7, PC12 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 3 }, /* PF2, PF4 */
+#else
+ { "uart0", 2 }, /* PB9, PB10 */
+#endif
+ { "uart1", 2 }, /* PG6, PG7 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun60i_a733_pinctrl_desc = {
+ .functions = sun60i_a733_pinctrl_functions,
+ .pio_offset = SUNXI_PIO_OFFSET,
+ .num_functions = ARRAY_SIZE(sun60i_a733_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 11,
+};
+
static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
@@ -847,6 +874,21 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun55i_a523_r_pinctrl_desc
.num_banks = 2,
};

+static const struct sunxi_pinctrl_function sun60i_a733_r_pinctrl_functions[] = {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "r_i2c0", 2 }, /* PL0-PL1 */
+ { "r_uart0", 3 }, /* PL2-PL3 */
+ { "r_uart1", 2 }, /* PL2-PL3 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun60i_a733_r_pinctrl_desc = {
+ .functions = sun60i_a733_r_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun60i_a733_r_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_L,
+ .num_banks = 2,
+};
+
static const struct udevice_id sunxi_pinctrl_ids[] = {
#ifdef CONFIG_PINCTRL_SUNIV_F1C100S
{
@@ -1034,6 +1076,19 @@ static const struct udevice_id sunxi_pinctrl_ids[] = {
.data = (ulong)&sun55i_a523_r_pinctrl_desc,
},
#endif
+
+#ifdef CONFIG_PINCTRL_SUN60I_A733
+ {
+ .compatible = "allwinner,sun60i-a733-pinctrl",
+ .data = (ulong)&sun60i_a733_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN60I_A733_R
+ {
+ .compatible = "allwinner,sun60i-a733-r-pinctrl",
+ .data = (ulong)&sun60i_a733_r_pinctrl_desc,
+ },
+#endif
{}
};

--
2.52.0