* [PATCH 1/7] pinctrl: rockchip: Add support for RV1103
2026-02-01 0:44 [PATCH 0/7] ARM: Add RV1103 Omega4 board support Fabio Estevam
@ 2026-02-01 0:44 ` Fabio Estevam
2026-02-01 1:28 ` Jonas Karlman
2026-02-01 0:44 ` [PATCH 2/7] clk: " Fabio Estevam
` (6 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Fabio Estevam @ 2026-02-01 0:44 UTC (permalink / raw)
To: kever.yang; +Cc: trini, u-boot, Fabio Estevam
From: Fabio Estevam <festevam@nabladev.com>
Add pinctrl driver for RV1103.
Imported from Rockchip U-Boot 2017.09 next-dev branch.
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
drivers/pinctrl/Kconfig | 10 +
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rv1103.c | 411 ++++++++++++++++++++++
3 files changed, 422 insertions(+)
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rv1103.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index ea90713ec6ca..e204d9880d83 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -254,6 +254,16 @@ config PINCTRL_QE
This option is to enable the QE pinctrl driver for QE based io
controller.
+config PINCTRL_ROCKCHIP_RV1103
+ bool "Rockchip rv1103 pin control driver"
+ depends on DM
+ help
+ Support pin multiplexing control on Rockchip rv1103 SoC.
+
+ The driver is controlled by a device tree node which contains
+ both the GPIO definitions and pin control functions for each
+ available multiplex function.
+
config PINCTRL_ROCKCHIP_RV1108
bool "Rockchip rv1108 pin control driver"
depends on DM
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index e17415e1ca68..f0ffd2b5fe86 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_ROCKCHIP_RK3528) += pinctrl-rk3528.o
obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
obj-$(CONFIG_ROCKCHIP_RK3576) += pinctrl-rk3576.o
obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o
+obj-$(CONFIG_ROCKCHIP_RV1103) += pinctrl-rv1103.o
obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o
diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1103.c b/drivers/pinctrl/rockchip/pinctrl-rv1103.c
new file mode 100644
index 000000000000..362c520212ee
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rv1103.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2024 Rockchip Electronics Co., Ltd
+ */
+
+#include <dm.h>
+#include <log.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+
+#include "pinctrl-rockchip.h"
+
+static int rv1103_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask;
+ u8 bit;
+ u32 data;
+
+ debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
+
+ if (bank->bank_num == 2 && pin >= 12)
+ return 0;
+
+ regmap = priv->regmap_base;
+ reg = bank->iomux[iomux_num].offset;
+ if ((pin % 8) >= 4)
+ reg += 0x4;
+ bit = (pin % 4) * 4;
+ mask = 0xf;
+
+ if (bank->recalced_mask & BIT(pin))
+ rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+
+ debug("iomux write reg = %x data = %x\n", reg, data);
+
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define RV1103_DRV_BITS_PER_PIN 8
+#define RV1103_DRV_PINS_PER_REG 2
+#define RV1103_DRV_GPIO0_A_OFFSET 0x40100
+#define RV1103_DRV_GPIO0_B_OFFSET 0x50110
+#define RV1103_DRV_GPIO1_A01_OFFSET 0x140
+#define RV1103_DRV_GPIO1_A67_OFFSET 0x1014C
+#define RV1103_DRV_GPIO2_OFFSET 0x30180
+#define RV1103_DRV_GPIO2_SARADC_OFFSET 0x3080C
+
+static int rv1103_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int ret = 0;
+
+ *regmap = priv->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ if (pin_num < 7)
+ *reg = RV1103_DRV_GPIO0_A_OFFSET;
+ else if (pin_num > 7 && pin_num < 14)
+ *reg = RV1103_DRV_GPIO0_B_OFFSET - 0x10;
+ else
+ ret = -EINVAL;
+ break;
+
+ case 1:
+ if (pin_num < 6)
+ *reg = RV1103_DRV_GPIO1_A01_OFFSET;
+ else if (pin_num >= 6 && pin_num < 23)
+ *reg = RV1103_DRV_GPIO1_A67_OFFSET - 0xc;
+ else if (pin_num >= 24 && pin_num < 30)
+ *reg = RV1103_DRV_GPIO1_A67_OFFSET - 0xc;
+ else
+ ret = -EINVAL;
+ break;
+
+ case 2:
+ if (pin_num < 12) {
+ *reg = RV1103_DRV_GPIO2_OFFSET;
+ } else if (pin_num >= 16) {
+ ret = -EINVAL;
+ } else {
+ *reg = RV1103_DRV_GPIO2_SARADC_OFFSET;
+ *bit = 10;
+
+ return 0;
+ }
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ if (ret) {
+ printf("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
+
+ return ret;
+ }
+
+ *reg += ((pin_num / RV1103_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RV1103_DRV_PINS_PER_REG;
+ *bit *= RV1103_DRV_BITS_PER_PIN;
+
+ return 0;
+}
+
+static int rv1103_set_drive(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct regmap *regmap;
+ int reg, ret, i;
+ u32 data;
+ u8 bit;
+ int rmask_bits = RV1103_DRV_BITS_PER_PIN;
+
+ ret = rv1103_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ if (ret)
+ return ret;
+
+ for (i = 0, ret = 1; i < strength; i++)
+ ret = (ret << 1) | 1;
+
+ if (bank->bank_num == 2 && pin_num >= 12) {
+ rmask_bits = 2;
+ ret = strength;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << rmask_bits) - 1) << (bit + 16);
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define RV1103_PULL_BITS_PER_PIN 2
+#define RV1103_PULL_PINS_PER_REG 8
+#define RV1103_PULL_GPIO0_A_OFFSET 0x40200
+#define RV1103_PULL_GPIO0_B_OFFSET 0x50204
+#define RV1103_PULL_GPIO1_A01_OFFSET 0x210
+#define RV1103_PULL_GPIO1_A67_OFFSET 0x10210
+#define RV1103_PULL_GPIO2_OFFSET 0x30220
+#define RV1103_PULL_GPIO2_SARADC_OFFSET 0x3080C
+
+static int rv1103_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int ret = 0;
+
+ *regmap = priv->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ if (pin_num < 7)
+ *reg = RV1103_PULL_GPIO0_A_OFFSET;
+ else if (pin_num > 7 && pin_num < 14)
+ *reg = RV1103_PULL_GPIO0_B_OFFSET - 0x4;
+ else
+ ret = -EINVAL;
+ break;
+
+ case 1:
+ if (pin_num < 6)
+ *reg = RV1103_PULL_GPIO1_A01_OFFSET;
+ else if (pin_num >= 6 && pin_num < 23)
+ *reg = RV1103_PULL_GPIO1_A67_OFFSET;
+ else if (pin_num >= 24 && pin_num < 30)
+ *reg = RV1103_PULL_GPIO1_A67_OFFSET;
+ else
+ ret = -EINVAL;
+ break;
+
+ case 2:
+ if (pin_num < 12) {
+ *reg = RV1103_PULL_GPIO2_OFFSET;
+ } else if (pin_num >= 16) {
+ ret = -EINVAL;
+ } else {
+ *reg = RV1103_PULL_GPIO2_SARADC_OFFSET;
+ *bit = 13;
+
+ return 0;
+ }
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ if (ret) {
+ printf("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
+
+ return ret;
+ }
+
+ *reg += ((pin_num / RV1103_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RV1103_PULL_PINS_PER_REG;
+ *bit *= RV1103_PULL_BITS_PER_PIN;
+
+ return 0;
+}
+
+static int rv1103_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -EINVAL;
+
+ ret = rv1103_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ if (ret)
+ return ret;
+ type = bank->pull_type[pin_num / 8];
+
+ if (bank->bank_num == 2 && pin_num >= 12)
+ type = 1;
+
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RV1103_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define RV1103_SMT_BITS_PER_PIN 1
+#define RV1103_SMT_PINS_PER_REG 8
+#define RV1103_SMT_GPIO0_A_OFFSET 0x40400
+#define RV1103_SMT_GPIO0_B_OFFSET 0x50404
+#define RV1103_SMT_GPIO1_A01_OFFSET 0x410
+#define RV1103_SMT_GPIO1_A67_OFFSET 0x10410
+#define RV1103_SMT_GPIO2_OFFSET 0x30420
+#define RV1103_SMT_GPIO2_SARADC_OFFSET 0x3080C
+
+static int rv1103_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int ret = 0;
+
+ *regmap = priv->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ if (pin_num < 7)
+ *reg = RV1103_SMT_GPIO0_A_OFFSET;
+ else if (pin_num > 7 && pin_num < 14)
+ *reg = RV1103_SMT_GPIO0_B_OFFSET - 0x4;
+ else
+ ret = -EINVAL;
+ break;
+
+ case 1:
+ if (pin_num < 6)
+ *reg = RV1103_SMT_GPIO1_A01_OFFSET;
+ else if (pin_num >= 6 && pin_num < 23)
+ *reg = RV1103_SMT_GPIO1_A67_OFFSET;
+ else if (pin_num >= 24 && pin_num < 30)
+ *reg = RV1103_SMT_GPIO1_A67_OFFSET;
+ else
+ ret = -EINVAL;
+ break;
+
+ case 2:
+ if (pin_num < 12) {
+ *reg = RV1103_SMT_GPIO2_OFFSET;
+ } else if (pin_num >= 16) {
+ ret = -EINVAL;
+ } else {
+ *reg = RV1103_SMT_GPIO2_SARADC_OFFSET;
+ *bit = 8;
+
+ return 0;
+ }
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ if (ret) {
+ printf("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
+
+ return ret;
+ }
+
+ *reg += ((pin_num / RV1103_SMT_PINS_PER_REG) * 4);
+ *bit = pin_num % RV1103_SMT_PINS_PER_REG;
+ *bit *= RV1103_SMT_BITS_PER_PIN;
+
+ return 0;
+}
+
+static int rv1103_set_schmitt(struct rockchip_pin_bank *bank,
+ int pin_num, int enable)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u32 data;
+ u8 bit;
+
+ ret = rv1103_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ if (ret)
+ return ret;
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RV1103_SMT_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (enable << bit);
+
+ if (bank->bank_num == 2 && pin_num >= 12) {
+ data = 0x3 << (bit + 16);
+ data |= ((enable ? 0x3 : 0) << bit);
+ }
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+static struct rockchip_mux_recalced_data rv1103_mux_recalced_data[] = {
+ {
+ .num = 1,
+ .pin = 6,
+ .reg = 0x10024,
+ .bit = 8,
+ .mask = 0xf
+ }, {
+ .num = 1,
+ .pin = 7,
+ .reg = 0x10024,
+ .bit = 12,
+ .mask = 0xf
+ },
+};
+
+static struct rockchip_pin_bank rv1103_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x40000, 0x50008, 0x50010, 0x50018),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x20, 0x10028, 0x10030, 0x10038),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x30040, 0x30048, 0x30050, 0x30058),
+};
+
+static const struct rockchip_pin_ctrl rv1103_pin_ctrl = {
+ .pin_banks = rv1103_pin_banks,
+ .nr_banks = ARRAY_SIZE(rv1103_pin_banks),
+ .iomux_recalced = rv1103_mux_recalced_data,
+ .niomux_recalced = ARRAY_SIZE(rv1103_mux_recalced_data),
+ .set_mux = rv1103_set_mux,
+ .set_pull = rv1103_set_pull,
+ .set_drive = rv1103_set_drive,
+ .set_schmitt = rv1103_set_schmitt,
+};
+
+static const struct udevice_id rv1103_pinctrl_ids[] = {
+ {
+ .compatible = "rockchip,rv1103-pinctrl",
+ .data = (ulong)&rv1103_pin_ctrl
+ },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_rv1103) = {
+ .name = "rockchip_rv1103_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = rv1103_pinctrl_ids,
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
+ .ops = &rockchip_pinctrl_ops,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .bind = dm_scan_fdt_dev,
+#endif
+ .probe = rockchip_pinctrl_probe,
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 1/7] pinctrl: rockchip: Add support for RV1103
2026-02-01 0:44 ` [PATCH 1/7] pinctrl: rockchip: Add support for RV1103 Fabio Estevam
@ 2026-02-01 1:28 ` Jonas Karlman
0 siblings, 0 replies; 12+ messages in thread
From: Jonas Karlman @ 2026-02-01 1:28 UTC (permalink / raw)
To: Fabio Estevam, Fabio Estevam; +Cc: kever.yang, trini, u-boot
Hi Fabio,
On 2/1/2026 1:44 AM, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@nabladev.com>
>
> Add pinctrl driver for RV1103.
See prior note about rv1103b vs rv1106/rv1103 compatibility and naming.
> Imported from Rockchip U-Boot 2017.09 next-dev branch.
This driver looks very close to vendor version [1], maybe this patch
should be From/Signed-off-by the original author? That is the practice
we typically follow for Rockchip platform.
[1] https://github.com/rockchip-linux/u-boot/commit/b73745f4bfe57b0a3ff47ae0bd8eea687a26f456
> Signed-off-by: Fabio Estevam <festevam@nabladev.com>
> ---
> drivers/pinctrl/Kconfig | 10 +
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl-rv1103.c | 411 ++++++++++++++++++++++
> 3 files changed, 422 insertions(+)
> create mode 100644 drivers/pinctrl/rockchip/pinctrl-rv1103.c
>
> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> index ea90713ec6ca..e204d9880d83 100644
> --- a/drivers/pinctrl/Kconfig
> +++ b/drivers/pinctrl/Kconfig
> @@ -254,6 +254,16 @@ config PINCTRL_QE
> This option is to enable the QE pinctrl driver for QE based io
> controller.
>
> +config PINCTRL_ROCKCHIP_RV1103
> + bool "Rockchip rv1103 pin control driver"
> + depends on DM
> + help
> + Support pin multiplexing control on Rockchip rv1103 SoC.
> +
> + The driver is controlled by a device tree node which contains
> + both the GPIO definitions and pin control functions for each
> + available multiplex function.
This Kconfig is not use for anything, please drop.
> config PINCTRL_ROCKCHIP_RV1108
> bool "Rockchip rv1108 pin control driver"
> depends on DM
> diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
> index e17415e1ca68..f0ffd2b5fe86 100644
> --- a/drivers/pinctrl/rockchip/Makefile
> +++ b/drivers/pinctrl/rockchip/Makefile
> @@ -18,5 +18,6 @@ obj-$(CONFIG_ROCKCHIP_RK3528) += pinctrl-rk3528.o
> obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
> obj-$(CONFIG_ROCKCHIP_RK3576) += pinctrl-rk3576.o
> obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o
> +obj-$(CONFIG_ROCKCHIP_RV1103) += pinctrl-rv1103.o
> obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
> obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o
> diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1103.c b/drivers/pinctrl/rockchip/pinctrl-rv1103.c
> new file mode 100644
> index 000000000000..362c520212ee
> --- /dev/null
> +++ b/drivers/pinctrl/rockchip/pinctrl-rv1103.c
> @@ -0,0 +1,411 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2024 Rockchip Electronics Co., Ltd
> + */
> +
> +#include <dm.h>
> +#include <log.h>
> +#include <dm/pinctrl.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +#include <linux/bitops.h>
> +
> +#include "pinctrl-rockchip.h"
> +
> +static int rv1103_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int iomux_num = (pin / 8);
> + struct regmap *regmap;
> + int reg, ret, mask;
> + u8 bit;
> + u32 data;
> +
> + debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
This is already logged in pinctrl-rockchip-core, please drop.
> + if (bank->bank_num == 2 && pin >= 12)
> + return 0;
> +
> + regmap = priv->regmap_base;
> + reg = bank->iomux[iomux_num].offset;
> + if ((pin % 8) >= 4)
> + reg += 0x4;
> + bit = (pin % 4) * 4;
> + mask = 0xf;
> +
> + if (bank->recalced_mask & BIT(pin))
> + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
> + data = (mask << (bit + 16));
> + data |= (mux & mask) << bit;
> +
> + debug("iomux write reg = %x data = %x\n", reg, data);
Please be consistent, log for all reg write or none.
> +
> + ret = regmap_write(regmap, reg, data);
Please update this driver to use regmap_update_bits instead of
regmap_write, see e.g. pinctrl for rk3528 or pending rk3506.
> +
> + return ret;
> +}
> +
> +#define RV1103_DRV_BITS_PER_PIN 8
> +#define RV1103_DRV_PINS_PER_REG 2
> +#define RV1103_DRV_GPIO0_A_OFFSET 0x40100
> +#define RV1103_DRV_GPIO0_B_OFFSET 0x50110
> +#define RV1103_DRV_GPIO1_A01_OFFSET 0x140
> +#define RV1103_DRV_GPIO1_A67_OFFSET 0x1014C
> +#define RV1103_DRV_GPIO2_OFFSET 0x30180
> +#define RV1103_DRV_GPIO2_SARADC_OFFSET 0x3080C
> +
> +static int rv1103_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int ret = 0;
> +
> + *regmap = priv->regmap_base;
> + switch (bank->bank_num) {
> + case 0:
> + if (pin_num < 7)
> + *reg = RV1103_DRV_GPIO0_A_OFFSET;
> + else if (pin_num > 7 && pin_num < 14)
> + *reg = RV1103_DRV_GPIO0_B_OFFSET - 0x10;
> + else
> + ret = -EINVAL;
> + break;
> +
> + case 1:
> + if (pin_num < 6)
> + *reg = RV1103_DRV_GPIO1_A01_OFFSET;
> + else if (pin_num >= 6 && pin_num < 23)
> + *reg = RV1103_DRV_GPIO1_A67_OFFSET - 0xc;
> + else if (pin_num >= 24 && pin_num < 30)
> + *reg = RV1103_DRV_GPIO1_A67_OFFSET - 0xc;
> + else
> + ret = -EINVAL;
> + break;
> +
> + case 2:
> + if (pin_num < 12) {
> + *reg = RV1103_DRV_GPIO2_OFFSET;
> + } else if (pin_num >= 16) {
> + ret = -EINVAL;
> + } else {
> + *reg = RV1103_DRV_GPIO2_SARADC_OFFSET;
> + *bit = 10;
> +
> + return 0;
> + }
> + break;
> +
> + default:
> + ret = -EINVAL;
> + break;
> + }
> +
> + if (ret) {
> + printf("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
> +
Please drop unnecessary blank lines in this file.
> + return ret;
> + }
> +
> + *reg += ((pin_num / RV1103_DRV_PINS_PER_REG) * 4);
> + *bit = pin_num % RV1103_DRV_PINS_PER_REG;
> + *bit *= RV1103_DRV_BITS_PER_PIN;
> +
> + return 0;
> +}
> +
> +static int rv1103_set_drive(struct rockchip_pin_bank *bank,
> + int pin_num, int strength)
> +{
> + struct regmap *regmap;
> + int reg, ret, i;
> + u32 data;
> + u8 bit;
> + int rmask_bits = RV1103_DRV_BITS_PER_PIN;
> +
> + ret = rv1103_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> + if (ret)
> + return ret;
> +
> + for (i = 0, ret = 1; i < strength; i++)
> + ret = (ret << 1) | 1;
> +
> + if (bank->bank_num == 2 && pin_num >= 12) {
> + rmask_bits = 2;
> + ret = strength;
> + }
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << rmask_bits) - 1) << (bit + 16);
> + data |= (ret << bit);
> + ret = regmap_write(regmap, reg, data);
> +
> + return ret;
> +}
> +
> +#define RV1103_PULL_BITS_PER_PIN 2
> +#define RV1103_PULL_PINS_PER_REG 8
> +#define RV1103_PULL_GPIO0_A_OFFSET 0x40200
> +#define RV1103_PULL_GPIO0_B_OFFSET 0x50204
> +#define RV1103_PULL_GPIO1_A01_OFFSET 0x210
> +#define RV1103_PULL_GPIO1_A67_OFFSET 0x10210
> +#define RV1103_PULL_GPIO2_OFFSET 0x30220
> +#define RV1103_PULL_GPIO2_SARADC_OFFSET 0x3080C
> +
> +static int rv1103_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int ret = 0;
> +
> + *regmap = priv->regmap_base;
> + switch (bank->bank_num) {
> + case 0:
> + if (pin_num < 7)
> + *reg = RV1103_PULL_GPIO0_A_OFFSET;
> + else if (pin_num > 7 && pin_num < 14)
> + *reg = RV1103_PULL_GPIO0_B_OFFSET - 0x4;
> + else
> + ret = -EINVAL;
> + break;
> +
> + case 1:
> + if (pin_num < 6)
> + *reg = RV1103_PULL_GPIO1_A01_OFFSET;
> + else if (pin_num >= 6 && pin_num < 23)
> + *reg = RV1103_PULL_GPIO1_A67_OFFSET;
> + else if (pin_num >= 24 && pin_num < 30)
> + *reg = RV1103_PULL_GPIO1_A67_OFFSET;
> + else
> + ret = -EINVAL;
> + break;
> +
> + case 2:
> + if (pin_num < 12) {
> + *reg = RV1103_PULL_GPIO2_OFFSET;
> + } else if (pin_num >= 16) {
> + ret = -EINVAL;
> + } else {
> + *reg = RV1103_PULL_GPIO2_SARADC_OFFSET;
> + *bit = 13;
> +
> + return 0;
> + }
> + break;
> +
> + default:
> + ret = -EINVAL;
> + break;
> + }
> +
> + if (ret) {
> + printf("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
> +
> + return ret;
> + }
> +
> + *reg += ((pin_num / RV1103_PULL_PINS_PER_REG) * 4);
> + *bit = pin_num % RV1103_PULL_PINS_PER_REG;
> + *bit *= RV1103_PULL_BITS_PER_PIN;
> +
> + return 0;
> +}
> +
> +static int rv1103_set_pull(struct rockchip_pin_bank *bank,
> + int pin_num, int pull)
> +{
> + struct regmap *regmap;
> + int reg, ret;
> + u8 bit, type;
> + u32 data;
> +
> + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
> + return -EINVAL;
> +
> + ret = rv1103_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> + if (ret)
> + return ret;
> + type = bank->pull_type[pin_num / 8];
> +
> + if (bank->bank_num == 2 && pin_num >= 12)
> + type = 1;
> +
> + ret = rockchip_translate_pull_value(type, pull);
> + if (ret < 0) {
> + debug("unsupported pull setting %d\n", pull);
> +
> + return ret;
> + }
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << RV1103_PULL_BITS_PER_PIN) - 1) << (bit + 16);
> +
> + data |= (ret << bit);
> + ret = regmap_write(regmap, reg, data);
> +
> + return ret;
> +}
> +
> +#define RV1103_SMT_BITS_PER_PIN 1
> +#define RV1103_SMT_PINS_PER_REG 8
> +#define RV1103_SMT_GPIO0_A_OFFSET 0x40400
> +#define RV1103_SMT_GPIO0_B_OFFSET 0x50404
> +#define RV1103_SMT_GPIO1_A01_OFFSET 0x410
> +#define RV1103_SMT_GPIO1_A67_OFFSET 0x10410
> +#define RV1103_SMT_GPIO2_OFFSET 0x30420
> +#define RV1103_SMT_GPIO2_SARADC_OFFSET 0x3080C
> +
> +static int rv1103_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num,
> + struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int ret = 0;
> +
> + *regmap = priv->regmap_base;
> + switch (bank->bank_num) {
> + case 0:
> + if (pin_num < 7)
> + *reg = RV1103_SMT_GPIO0_A_OFFSET;
> + else if (pin_num > 7 && pin_num < 14)
> + *reg = RV1103_SMT_GPIO0_B_OFFSET - 0x4;
> + else
> + ret = -EINVAL;
> + break;
> +
> + case 1:
> + if (pin_num < 6)
> + *reg = RV1103_SMT_GPIO1_A01_OFFSET;
> + else if (pin_num >= 6 && pin_num < 23)
> + *reg = RV1103_SMT_GPIO1_A67_OFFSET;
> + else if (pin_num >= 24 && pin_num < 30)
> + *reg = RV1103_SMT_GPIO1_A67_OFFSET;
> + else
> + ret = -EINVAL;
> + break;
> +
> + case 2:
> + if (pin_num < 12) {
> + *reg = RV1103_SMT_GPIO2_OFFSET;
> + } else if (pin_num >= 16) {
> + ret = -EINVAL;
> + } else {
> + *reg = RV1103_SMT_GPIO2_SARADC_OFFSET;
> + *bit = 8;
> +
> + return 0;
> + }
> + break;
> +
> + default:
> + ret = -EINVAL;
> + break;
> + }
> +
> + if (ret) {
> + printf("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
> +
> + return ret;
> + }
> +
> + *reg += ((pin_num / RV1103_SMT_PINS_PER_REG) * 4);
> + *bit = pin_num % RV1103_SMT_PINS_PER_REG;
> + *bit *= RV1103_SMT_BITS_PER_PIN;
> +
> + return 0;
> +}
> +
> +static int rv1103_set_schmitt(struct rockchip_pin_bank *bank,
> + int pin_num, int enable)
> +{
> + struct regmap *regmap;
> + int reg, ret;
> + u32 data;
> + u8 bit;
> +
> + ret = rv1103_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> + if (ret)
> + return ret;
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << RV1103_SMT_BITS_PER_PIN) - 1) << (bit + 16);
> + data |= (enable << bit);
> +
> + if (bank->bank_num == 2 && pin_num >= 12) {
> + data = 0x3 << (bit + 16);
> + data |= ((enable ? 0x3 : 0) << bit);
> + }
> + ret = regmap_write(regmap, reg, data);
> +
> + return ret;
> +}
> +
> +static struct rockchip_mux_recalced_data rv1103_mux_recalced_data[] = {
> + {
> + .num = 1,
> + .pin = 6,
> + .reg = 0x10024,
> + .bit = 8,
> + .mask = 0xf
> + }, {
> + .num = 1,
> + .pin = 7,
> + .reg = 0x10024,
> + .bit = 12,
> + .mask = 0xf
> + },
> +};
> +
> +static struct rockchip_pin_bank rv1103_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + 0x40000, 0x50008, 0x50010, 0x50018),
> + PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + 0x20, 0x10028, 0x10030, 0x10038),
> + PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + 0x30040, 0x30048, 0x30050, 0x30058),
> +};
> +
> +static const struct rockchip_pin_ctrl rv1103_pin_ctrl = {
> + .pin_banks = rv1103_pin_banks,
> + .nr_banks = ARRAY_SIZE(rv1103_pin_banks),
> + .iomux_recalced = rv1103_mux_recalced_data,
> + .niomux_recalced = ARRAY_SIZE(rv1103_mux_recalced_data),
> + .set_mux = rv1103_set_mux,
> + .set_pull = rv1103_set_pull,
> + .set_drive = rv1103_set_drive,
> + .set_schmitt = rv1103_set_schmitt,
> +};
> +
> +static const struct udevice_id rv1103_pinctrl_ids[] = {
> + {
> + .compatible = "rockchip,rv1103-pinctrl",
As already mentioned, please send out and get this complatible acked in
Linux, especially with the rv1103b vs rv1106/rv1103 confusion.
Regards,
Jonas
> + .data = (ulong)&rv1103_pin_ctrl
> + },
> + { }
> +};
> +
> +U_BOOT_DRIVER(pinctrl_rv1103) = {
> + .name = "rockchip_rv1103_pinctrl",
> + .id = UCLASS_PINCTRL,
> + .of_match = rv1103_pinctrl_ids,
> + .priv_auto = sizeof(struct rockchip_pinctrl_priv),
> + .ops = &rockchip_pinctrl_ops,
> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
> + .bind = dm_scan_fdt_dev,
> +#endif
> + .probe = rockchip_pinctrl_probe,
> +};
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/7] clk: rockchip: Add support for RV1103
2026-02-01 0:44 [PATCH 0/7] ARM: Add RV1103 Omega4 board support Fabio Estevam
2026-02-01 0:44 ` [PATCH 1/7] pinctrl: rockchip: Add support for RV1103 Fabio Estevam
@ 2026-02-01 0:44 ` Fabio Estevam
2026-02-01 0:44 ` [PATCH 3/7] tools: rkcommon: Add rv1103 support Fabio Estevam
` (5 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Fabio Estevam @ 2026-02-01 0:44 UTC (permalink / raw)
To: kever.yang; +Cc: trini, u-boot, Fabio Estevam
From: Fabio Estevam <festevam@nabladev.com>
Add clock driver for RV1103.
Imported from Rockchip U-Boot 2017.09 next-dev branch.
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
.../include/asm/arch-rockchip/cru_rv1103.h | 271 +++++
.../include/asm/arch-rockchip/grf_rv1103.h | 31 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk_rv1103.c | 1068 +++++++++++++++++
4 files changed, 1371 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rv1103.h
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rv1103.h
create mode 100644 drivers/clk/rockchip/clk_rv1103.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1103.h b/arch/arm/include/asm/arch-rockchip/cru_rv1103.h
new file mode 100644
index 000000000000..c082d697231e
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rv1103.h
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _ASM_ARCH_CRU_RV1103B_H
+#define _ASM_ARCH_CRU_RV1103B_H
+
+#define MHz 1000000
+#define KHz 1000
+#define OSC_HZ (24 * MHz)
+#define RC_OSC_HZ (125 * MHz)
+
+#define GPLL_HZ (1188 * MHz)
+
+/* RV1103B pll id */
+enum rv1103b_pll_id {
+ GPLL,
+ PLL_COUNT,
+};
+
+struct rv1103b_clk_info {
+ unsigned long id;
+ char *name;
+ bool is_cru;
+};
+
+struct rv1103b_clk_priv {
+ struct rv1103b_cru *cru;
+ struct rv1103b_grf *grf;
+ ulong gpll_hz;
+ ulong armclk_hz;
+ ulong armclk_enter_hz;
+ ulong armclk_init_hz;
+ bool sync_kernel;
+ bool set_armclk_rate;
+};
+
+struct rv1103b_grf_clk_priv {
+ struct rv1103b_grf *grf;
+};
+
+struct rv1103b_pll {
+ unsigned int con0;
+ unsigned int con1;
+ unsigned int con2;
+ unsigned int con3;
+ unsigned int con4;
+ unsigned int reserved0[3];
+};
+
+struct rv1103_clk_priv {
+ struct rv1103b_cru *cru;
+ ulong rate;
+};
+
+struct rv1103b_cru {
+ unsigned int reserved0[192];
+ unsigned int peri_clksel_con[4];
+ unsigned int reserved1[316];
+ unsigned int peri_clkgate_con[12];
+ unsigned int reserved2[116];
+ unsigned int peri_softrst_con[12];
+ unsigned int reserved3[15924];
+ unsigned int vepu_clksel_con[3];
+ unsigned int reserved4[317];
+ unsigned int vepu_clkgate_con[1];
+ unsigned int reserved5[127];
+ unsigned int vepu_softrst_con[1];
+ unsigned int reserved6[15935];
+ unsigned int npu_clksel_con[3];
+ unsigned int reserved7[317];
+ unsigned int npu_clkgate_con[1];
+ unsigned int reserved8[127];
+ unsigned int npu_softrst_con[1];
+ unsigned int reserved9[15935];
+ unsigned int vi_clksel_con[1];
+ unsigned int reserved10[319];
+ unsigned int vi_clkgate_con[3];
+ unsigned int reserved11[125];
+ unsigned int vi_softrst_con[3];
+ unsigned int reserved12[15933];
+ unsigned int core_clksel_con[3];
+ unsigned int reserved13[16381];
+ unsigned int ddr_clksel_con[1];
+ unsigned int reserved14[16207];
+ struct rv1103b_pll pll[2];
+ unsigned int reserved15[128];
+ unsigned int mode;
+ unsigned int reserved16[31];
+ unsigned int clksel_con[42];
+ unsigned int reserved17[278];
+ unsigned int clkgate_con[7];
+ unsigned int reserved18[121];
+ unsigned int softrst_con[1];
+ unsigned int reserved19[127];
+ unsigned int glb_cnt_th;
+ unsigned int glb_rst_st;
+ unsigned int glb_srst_fst;
+ unsigned int glb_srst_snd;
+ unsigned int glb_rst_con;
+ unsigned int reserved20[15803];
+ unsigned int pmu_clksel_con[3];
+ unsigned int reserved21[317];
+ unsigned int pmu_clkgate_con[3];
+ unsigned int reserved22[125];
+ unsigned int pmu_softrst_con[3];
+ unsigned int reserved23[15933];
+ unsigned int pmu1_clksel_con[1];
+ unsigned int reserved24[319];
+ unsigned int pmu1_clkgate_con[2];
+ unsigned int reserved25[126];
+ unsigned int pmu1_softrst_con[2];
+};
+
+check_member(rv1103b_cru, pmu1_softrst_con[1], 0x80a04);
+
+struct pll_rate_table {
+ unsigned long rate;
+ unsigned int fbdiv;
+ unsigned int postdiv1;
+ unsigned int refdiv;
+ unsigned int postdiv2;
+ unsigned int dsmpd;
+ unsigned int frac;
+};
+
+#define RV1103B_TOPCRU_BASE 0x60000
+#define RV1103B_PERICRU_BASE 0x0
+#define RV1103B_VICRU_BASE 0x30000
+#define RV1103B_NPUCRU_BASE 0x20000
+#define RV1103B_CORECRU_BASE 0x40000
+#define RV1103B_VEPUCRU_BASE 0x10000
+#define RV1103B_DDRCRU_BASE 0x50000
+#define RV1103B_SUBDDRCRU_BASE 0x58000
+#define RV1103B_PMUCRU_BASE 0x70000
+#define RV1103B_PMU1CRU_BASE 0x80000
+
+#define RV1103B_CRU_BASE 0x20000000
+
+#define RV1103B_PLL_CON(x) ((x) * 0x4 + RV1103B_TOPCRU_BASE)
+#define RV1103B_MODE_CON (0x280 + RV1103B_TOPCRU_BASE)
+#define RV1103B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_TOPCRU_BASE)
+#define RV1103B_SUBDDRMODE_CON (0x280 + RV1103B_SUBDDRCRU_BASE)
+
+enum {
+ /* CORECRU_CLK_SEL0_CON */
+ CLK_CORE_SRC_SEL_SHIFT = 1,
+ CLK_CORE_SRC_SEL_MASK = 0x1 << CLK_CORE_SRC_SEL_SHIFT,
+ CLK_CORE_SRC_SEL_GPLL = 0,
+ CLK_CORE_SRC_SEL_PVTPLL,
+
+ /* CRU_PERI_CLK_SEL0_CON */
+ CLK_TSADC_TSEN_DIV_SHIFT = 10,
+ CLK_TSADC_TSEN_DIV_MASK = 0x1f << CLK_TSADC_TSEN_DIV_SHIFT,
+ CLK_TSADC_DIV_SHIFT = 4,
+ CLK_TSADC_DIV_MASK = 0x1f << CLK_TSADC_DIV_SHIFT,
+ PCLK_PERI_DIV_SHIFT = 0,
+ PCLK_PERI_DIV_MASK = 0x3 << PCLK_PERI_DIV_SHIFT,
+
+ /* CRU_PERI_CLK_SEL1_CON */
+ CLK_SARADC_DIV_SHIFT = 0,
+ CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL5_CON */
+ CLK_UART2_SRC_DIV_SHIFT = 10,
+ CLK_UART2_SRC_DIV_MASK = 0x1f << CLK_UART2_SRC_DIV_SHIFT,
+ CLK_UART1_SRC_DIV_SHIFT = 5,
+ CLK_UART1_SRC_DIV_MASK = 0x1f << CLK_UART1_SRC_DIV_SHIFT,
+ CLK_UART0_SRC_DIV_SHIFT = 0,
+ CLK_UART0_SRC_DIV_MASK = 0x1f << CLK_UART0_SRC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL10_CON */
+ CLK_UART_FRAC_NUMERATOR_SHIFT = 16,
+ CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16,
+ CLK_UART_FRAC_DENOMINATOR_SHIFT = 0,
+ CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff,
+
+ /* CRU_CLK_SEL31_CON */
+ CLK_EMMC_SEL_SHIFT = 15,
+ CLK_EMMC_SEL_MASK = 0x1 << CLK_EMMC_SEL_SHIFT,
+ ACLK_PERI_SEL_SHIFT = 10,
+ ACLK_PERI_SEL_MASK = 0x3 << ACLK_PERI_SEL_SHIFT,
+ ACLK_PERI_SEL_600M = 0,
+ ACLK_PERI_SEL_480M,
+ ACLK_PERI_SEL_400M,
+ LSCLK_PERI_SEL_SHIFT = 9,
+ LSCLK_PERI_SEL_MASK = 0x1 << LSCLK_PERI_SEL_SHIFT,
+ LSCLK_PERI_SEL_300M = 0,
+ LSCLK_PERI_SEL_200M,
+ CLK_EMMC_DIV_SHIFT = 0,
+ CLK_EMMC_DIV_MASK = 0xff << CLK_EMMC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL32_CON */
+ CLK_SDMMC_SEL_SHIFT = 15,
+ CLK_SDMMC_SEL_MASK = 0x1 << CLK_SDMMC_SEL_SHIFT,
+ CLK_MMC_SEL_GPLL = 0,
+ CLK_MMC_SEL_OSC,
+ CLK_UART2_SEL_SHIFT = 12,
+ CLK_UART2_SEL_MASK = 3 << CLK_UART2_SEL_SHIFT,
+ CLK_UART1_SEL_SHIFT = 10,
+ CLK_UART1_SEL_MASK = 3 << CLK_UART1_SEL_SHIFT,
+ CLK_UART0_SEL_SHIFT = 8,
+ CLK_UART0_SEL_MASK = 3 << CLK_UART0_SEL_SHIFT,
+ CLK_UART_SEL_SRC = 0,
+ CLK_UART_SEL_FRAC,
+ CLK_UART_SEL_OSC,
+ CLK_SDMMC_DIV_SHIFT = 0,
+ CLK_SDMMC_DIV_MASK = 0xff << CLK_SDMMC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL33_CON */
+ CLK_SFC_SEL_SHIFT = 15,
+ CLK_SFC_SEL_MASK = 0x1 << CLK_SFC_SEL_SHIFT,
+ CLK_SFC_DIV_SHIFT = 0,
+ CLK_SFC_DIV_MASK = 0xff << CLK_SFC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL34_CON */
+ CLK_PWM2_SEL_SHIFT = 14,
+ CLK_PWM2_SEL_MASK = 1 << CLK_PWM2_SEL_SHIFT,
+ CLK_PWM1_SEL_SHIFT = 13,
+ CLK_PWM1_SEL_MASK = 1 << CLK_PWM1_SEL_SHIFT,
+ CLK_PWM0_SEL_SHIFT = 12,
+ CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT,
+ CLK_PWM_SEL_100M = 0,
+ CLK_PWM_SEL_24M,
+ CLK_SPI0_SEL_SHIFT = 2,
+ CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT,
+ CLK_SPI0_SEL_200M = 0,
+ CLK_SPI0_SEL_100M,
+ CLK_SPI0_SEL_50M,
+ CLK_SPI0_SEL_24M,
+ CLK_I2C1_SEL_SHIFT = 1,
+ CLK_I2C1_SEL_MASK = 0x1 << CLK_I2C1_SEL_SHIFT,
+ CLK_I2C0_SEL_SHIFT = 0,
+ CLK_I2C0_SEL_MASK = 0x1 << CLK_I2C0_SEL_SHIFT,
+ CLK_I2C_SEL_100M = 0,
+ CLK_I2C_SEL_24M,
+
+ /* CRU_CLK_SEL35_CON */
+ CLK_PKA_CRYPTO_SEL_SHIFT = 4,
+ CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT,
+ CLK_CORE_CRYPTO_SEL_SHIFT = 2,
+ CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT,
+ CLK_CORE_CRYPTO_SEL_300M = 0,
+ CLK_CORE_CRYPTO_SEL_200M,
+ CLK_CORE_CRYPTO_SEL_100M,
+ DCLK_DECOM_SEL_SHIFT = 0,
+ DCLK_DECOM_SEL_MASK = 0x3 << DCLK_DECOM_SEL_SHIFT,
+ DCLK_DECOM_SEL_480M = 0,
+ DCLK_DECOM_SEL_400M,
+ DCLK_DECOM_SEL_300M,
+
+ /* CRU_CLK_SEL37_CON */
+ CLK_CORE_GPLL_DIV_SHIFT = 13,
+ CLK_CORE_GPLL_DIV_MASK = 0x7 << CLK_CORE_GPLL_DIV_SHIFT,
+ CLK_CORE_GPLL_SEL_SHIFT = 12,
+ CLK_CORE_GPLL_SEL_MASK = 0x1 << CLK_CORE_GPLL_SEL_SHIFT,
+ CLK_CORE_GPLL_SEL_GPLL = 0,
+ CLK_CORE_GPLL_SEL_OSC,
+
+ /* CRU_PMU_CLK_SEL2_CON */
+ LSCLK_PMU_SEL_SHIFT = 4,
+ LSCLK_PMU_SEL_MASK = 0x1 << LSCLK_PMU_SEL_SHIFT,
+ LSCLK_PMU_SEL_24M = 0,
+ LSCLK_PMU_SEL_RC_OSC,
+ LSCLK_PMU_DIV_SHIFT = 0,
+ LSCLK_PMU_DIV_MASK = 0x3 << LSCLK_PMU_DIV_SHIFT,
+
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1103.h b/arch/arm/include/asm/arch-rockchip/grf_rv1103.h
new file mode 100644
index 000000000000..c5bcb8962bb5
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rv1103.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/*
+ * (C) Copyright 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _ASM_ARCH_GRF_RV1103B_H
+#define _ASM_ARCH_GRF_RV1103B_H
+
+#define VEPU_GRF 0x20100000
+#define NPU_GRF 0x20110000
+#define VI_GRF 0x20120000
+#define CPU_GRF 0x20130000
+#define DDR_GRF 0x20140000
+#define SYS_GRF 0x20150000
+#define PMU_GRF 0x20160000
+
+struct rv1103_grf {
+ u32 reserved0[(SYS_GRF + 0xA0 - VEPU_GRF) / 4];
+ u32 gmac_con0; /* address offset: 0x00a0 */
+ u32 gmac_clk_con; /* address offset: 0x00a4 */
+ u32 gmac_st; /* address offset: 0x00a8 */
+ u32 reserved00ac; /* address offset: 0x00ac */
+ u32 macphy_con0; /* address offset: 0x00b0 */
+ u32 macphy_con1; /* address offset: 0x00b4 */
+ u32 reserved1[(PMU_GRF + 0x10000 - (SYS_GRF + 0xB4)) / 4];
+};
+
+check_member(rv1103_grf, macphy_con1, SYS_GRF + 0xB4 - VEPU_GRF);
+
+#endif /* _ASM_ARCH_GRF_RV1103B_H */
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 34b63d4df34a..bb1332542d52 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -19,5 +19,6 @@ obj-$(CONFIG_ROCKCHIP_RK3528) += clk_rk3528.o
obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
obj-$(CONFIG_ROCKCHIP_RK3576) += clk_rk3576.o
obj-$(CONFIG_ROCKCHIP_RK3588) += clk_rk3588.o
+obj-$(CONFIG_ROCKCHIP_RV1103) += clk_rv1103.o
obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o
obj-$(CONFIG_ROCKCHIP_RV1126) += clk_rv1126.o
diff --git a/drivers/clk/rockchip/clk_rv1103.c b/drivers/clk/rockchip/clk_rv1103.c
new file mode 100644
index 000000000000..b13f34cafccb
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rv1103.c
@@ -0,0 +1,1068 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#include <bitfield.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/io.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rv1103-cru.h>
+
+#include <clk.h>
+#include <log.h>
+#include <malloc.h>
+#include <asm/global_data.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rv1103.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <linux/delay.h>
+#include <linux/stringify.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+
+#ifndef BITS_WITH_WMASK
+#define BITS_WITH_WMASK(bits, msk, shift) \
+ ((bits) << (shift)) | ((msk) << ((shift) + 16))
+#endif
+
+static struct rockchip_pll_rate_table rv1103b_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
+ { /* sentinel */ },
+};
+
+static struct rockchip_pll_clock rv1103b_pll_clks[] = {
+ [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1103B_PLL_CON(24),
+ RV1103B_MODE_CON, 0, 10, 0, rv1103b_pll_rates),
+};
+
+static ulong rv1103b_peri_get_clk(struct rv1103b_clk_priv *priv, ulong clk_id)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ u32 con, sel, div, rate, prate;
+
+ switch (clk_id) {
+ case ACLK_PERI_SRC:
+ con = readl(&cru->clksel_con[31]);
+ sel = (con & ACLK_PERI_SEL_MASK) >> ACLK_PERI_SEL_SHIFT;
+ if (sel == ACLK_PERI_SEL_600M)
+ rate = 600 * MHz;
+ else if (sel == ACLK_PERI_SEL_480M)
+ rate = 480 * MHz;
+ else
+ rate = 400 * MHz;
+ break;
+ case LSCLK_PERI_SRC:
+ con = readl(&cru->clksel_con[31]);
+ sel = (con & LSCLK_PERI_SEL_MASK) >> LSCLK_PERI_SEL_SHIFT;
+ if (sel == LSCLK_PERI_SEL_300M)
+ rate = 300 * MHz;
+ else
+ rate = 200 * MHz;
+ break;
+ case PCLK_PERI_ROOT:
+ con = readl(&cru->peri_clksel_con[0]);
+ div = (con & PCLK_PERI_DIV_MASK) >> PCLK_PERI_DIV_SHIFT;
+ rate = DIV_TO_RATE(rv1103b_peri_get_clk(priv, LSCLK_PERI_SRC),
+ div);
+ break;
+ case PCLK_TOP_ROOT:
+ rate = DIV_TO_RATE(priv->gpll_hz, 11);
+ break;
+ case LSCLK_PMU_ROOT:
+ case PCLK_PMU:
+ con = readl(&cru->pmu_clksel_con[2]);
+ sel = (con & LSCLK_PMU_SEL_MASK) >> LSCLK_PMU_SEL_SHIFT;
+ div = (con & LSCLK_PMU_DIV_MASK) >> LSCLK_PMU_DIV_SHIFT;
+ if (sel == LSCLK_PMU_SEL_24M)
+ prate = OSC_HZ;
+ else
+ prate = RC_OSC_HZ;
+ rate = DIV_TO_RATE(prate, div);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+}
+
+static ulong rv1103b_peri_set_clk(struct rv1103b_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ int src_clk, div;
+
+ switch (clk_id) {
+ case ACLK_PERI_SRC:
+ if (rate >= 594 * MHz)
+ src_clk = ACLK_PERI_SEL_600M;
+ else if (rate >= 480 * MHz)
+ src_clk = ACLK_PERI_SEL_480M;
+ else
+ src_clk = ACLK_PERI_SEL_400M;
+ rk_clrsetreg(&cru->clksel_con[31],
+ ACLK_PERI_SEL_MASK,
+ src_clk << ACLK_PERI_SEL_SHIFT);
+ break;
+ case LSCLK_PERI_SRC:
+ if (rate >= 297 * MHz)
+ src_clk = LSCLK_PERI_SEL_300M;
+ else
+ src_clk = LSCLK_PERI_SEL_200M;
+ rk_clrsetreg(&cru->clksel_con[31],
+ LSCLK_PERI_SEL_MASK,
+ src_clk << LSCLK_PERI_SEL_SHIFT);
+ break;
+ case PCLK_PERI_ROOT:
+ div = DIV_ROUND_UP(rv1103b_peri_get_clk(priv, LSCLK_PERI_SRC),
+ rate);
+ rk_clrsetreg(&cru->peri_clksel_con[0],
+ PCLK_PERI_DIV_MASK,
+ (div - 1) << PCLK_PERI_DIV_SHIFT);
+ break;
+ case PCLK_TOP_ROOT:
+ break;
+ case LSCLK_PMU_ROOT:
+ case PCLK_PMU:
+ if (!(OSC_HZ % rate)) {
+ src_clk = LSCLK_PMU_SEL_24M;
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ } else {
+ src_clk = LSCLK_PMU_SEL_RC_OSC;
+ div = DIV_ROUND_UP(RC_OSC_HZ, rate);
+ }
+ rk_clrsetreg(&cru->pmu_clksel_con[2],
+ LSCLK_PMU_SEL_MASK | LSCLK_PMU_DIV_MASK,
+ (src_clk << LSCLK_PMU_SEL_SHIFT) |
+ ((div - 1) << LSCLK_PMU_DIV_SHIFT));
+ break;
+ default:
+ printf("do not support this permid freq\n");
+ return -EINVAL;
+ }
+
+ return rv1103b_peri_get_clk(priv, clk_id);
+}
+
+static ulong rv1103b_i2c_get_clk(struct rv1103b_clk_priv *priv, ulong clk_id)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ u32 sel, con;
+ ulong rate;
+
+ switch (clk_id) {
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C_PERI:
+ con = readl(&cru->clksel_con[34]);
+ sel = (con & CLK_I2C1_SEL_MASK) >> CLK_I2C1_SEL_SHIFT;
+ break;
+ case CLK_I2C0:
+ case CLK_I2C_PMU:
+ con = readl(&cru->clksel_con[34]);
+ sel = (con & CLK_I2C0_SEL_MASK) >> CLK_I2C0_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ if (sel == CLK_I2C_SEL_100M)
+ rate = 100 * MHz;
+ else
+ rate = OSC_HZ;
+
+ return rate;
+}
+
+static ulong rv1103b_crypto_get_clk(struct rv1103b_clk_priv *priv, ulong clk_id)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ u32 sel, con, rate;
+
+ switch (clk_id) {
+ case ACLK_CRYPTO:
+ case HCLK_CRYPTO:
+ case HCLK_RK_RNG_NS:
+ case HCLK_RK_RNG_S:
+ return rv1103b_peri_get_clk(priv, LSCLK_PERI_SRC);
+ case CLK_CORE_CRYPTO:
+ con = readl(&cru->clksel_con[35]);
+ sel = (con & CLK_CORE_CRYPTO_SEL_MASK) >>
+ CLK_CORE_CRYPTO_SEL_SHIFT;
+ break;
+ case CLK_PKA_CRYPTO:
+ con = readl(&cru->clksel_con[35]);
+ sel = (con & CLK_PKA_CRYPTO_SEL_MASK) >>
+ CLK_PKA_CRYPTO_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+ if (sel == CLK_CORE_CRYPTO_SEL_300M)
+ rate = 300 * MHz;
+ else if (sel == CLK_CORE_CRYPTO_SEL_200M)
+ rate = 200 * MHz;
+ else
+ rate = 100 * MHz;
+
+ return rate;
+}
+
+static ulong rv1103b_crypto_set_clk(struct rv1103b_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ u32 sel;
+
+ if (rate >= 297 * MHz)
+ sel = CLK_CORE_CRYPTO_SEL_300M;
+ else if (rate >= 198 * MHz)
+ sel = CLK_CORE_CRYPTO_SEL_200M;
+ else
+ sel = CLK_CORE_CRYPTO_SEL_100M;
+
+ switch (clk_id) {
+ case ACLK_CRYPTO:
+ case HCLK_CRYPTO:
+ case HCLK_RK_RNG_NS:
+ case HCLK_RK_RNG_S:
+ rv1103b_peri_set_clk(priv, LSCLK_PERI_SRC, rate);
+ case CLK_CORE_CRYPTO:
+ rk_clrsetreg(&cru->clksel_con[35],
+ CLK_CORE_CRYPTO_SEL_MASK,
+ (sel << CLK_CORE_CRYPTO_SEL_SHIFT));
+ break;
+ case CLK_PKA_CRYPTO:
+ rk_clrsetreg(&cru->clksel_con[35],
+ CLK_PKA_CRYPTO_SEL_MASK,
+ (sel << CLK_PKA_CRYPTO_SEL_SHIFT));
+ break;
+ default:
+ return -ENOENT;
+ }
+ return rv1103b_crypto_get_clk(priv, clk_id);
+}
+
+static ulong rv1103b_mmc_get_clk(struct rv1103b_clk_priv *priv, ulong clk_id)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ u32 div, sel, con, prate;
+
+ switch (clk_id) {
+ case CCLK_SDMMC1:
+ case HCLK_SDMMC1:
+ con = readl(&cru->clksel_con[36]);
+ sel = (con & CLK_SDMMC_SEL_MASK) >>
+ CLK_SDMMC_SEL_SHIFT;
+ div = (con & CLK_SDMMC_DIV_MASK) >>
+ CLK_SDMMC_DIV_SHIFT;
+ if (sel == CLK_MMC_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case CCLK_SDMMC0:
+ case HCLK_SDMMC0:
+ con = readl(&cru->clksel_con[32]);
+ sel = (con & CLK_SDMMC_SEL_MASK) >>
+ CLK_SDMMC_SEL_SHIFT;
+ div = (con & CLK_SDMMC_DIV_MASK) >>
+ CLK_SDMMC_DIV_SHIFT;
+ if (sel == CLK_MMC_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case CCLK_EMMC:
+ case HCLK_EMMC:
+ con = readl(&cru->clksel_con[31]);
+ sel = (con & CLK_EMMC_SEL_MASK) >>
+ CLK_EMMC_SEL_SHIFT;
+ div = (con & CLK_EMMC_DIV_MASK) >>
+ CLK_EMMC_DIV_SHIFT;
+ if (sel == CLK_MMC_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case SCLK_SFC_2X:
+ case HCLK_SFC:
+ con = readl(&cru->clksel_con[33]);
+ sel = (con & CLK_SFC_SEL_MASK) >>
+ CLK_SFC_SEL_SHIFT;
+ div = (con & CLK_SFC_DIV_MASK) >>
+ CLK_SFC_DIV_SHIFT;
+ if (sel == CLK_MMC_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rv1103b_mmc_set_clk(struct rv1103b_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ u32 sel, src_clk_div;
+ ulong prate = 0;
+
+ if ((OSC_HZ % rate) == 0) {
+ sel = CLK_MMC_SEL_OSC;
+ prate = OSC_HZ;
+ } else {
+ sel = CLK_MMC_SEL_GPLL;
+ prate = priv->gpll_hz;
+ }
+ src_clk_div = DIV_ROUND_UP(prate, rate);
+
+ switch (clk_id) {
+ case CCLK_SDMMC1:
+ case HCLK_SDMMC1:
+ src_clk_div = DIV_ROUND_UP(prate, rate);
+ rk_clrsetreg(&cru->clksel_con[36],
+ CLK_SDMMC_SEL_MASK |
+ CLK_SDMMC_DIV_MASK,
+ (sel << CLK_SDMMC_SEL_SHIFT) |
+ ((src_clk_div - 1) <<
+ CLK_SDMMC_DIV_SHIFT));
+ break;
+ case CCLK_SDMMC0:
+ case HCLK_SDMMC0:
+ src_clk_div = DIV_ROUND_UP(prate, rate);
+ rk_clrsetreg(&cru->clksel_con[32],
+ CLK_SDMMC_SEL_MASK |
+ CLK_SDMMC_DIV_MASK,
+ (sel << CLK_SDMMC_SEL_SHIFT) |
+ ((src_clk_div - 1) <<
+ CLK_SDMMC_DIV_SHIFT));
+ break;
+ case CCLK_EMMC:
+ case HCLK_EMMC:
+ src_clk_div = DIV_ROUND_UP(prate, rate);
+ rk_clrsetreg(&cru->clksel_con[31],
+ CLK_EMMC_SEL_MASK |
+ CLK_EMMC_DIV_MASK,
+ (sel << CLK_EMMC_SEL_SHIFT) |
+ ((src_clk_div - 1) <<
+ CLK_EMMC_DIV_SHIFT));
+ break;
+ case SCLK_SFC_2X:
+ case HCLK_SFC:
+ src_clk_div = DIV_ROUND_UP(prate, rate);
+ rk_clrsetreg(&cru->clksel_con[33],
+ CLK_SFC_SEL_MASK |
+ CLK_SFC_DIV_MASK,
+ (sel << CLK_SFC_SEL_SHIFT) |
+ ((src_clk_div - 1) <<
+ CLK_SFC_DIV_SHIFT));
+ break;
+ default:
+ return -ENOENT;
+ }
+ return rv1103b_mmc_get_clk(priv, clk_id);
+}
+
+static ulong rv1103b_i2c_set_clk(struct rv1103b_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ int src_clk;
+
+ if (rate == OSC_HZ)
+ src_clk = CLK_I2C_SEL_24M;
+ else
+ src_clk = CLK_I2C_SEL_100M;
+
+ switch (clk_id) {
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C_PERI:
+ rk_clrsetreg(&cru->clksel_con[34], CLK_I2C1_SEL_MASK,
+ src_clk << CLK_I2C1_SEL_SHIFT);
+ break;
+ case CLK_I2C0:
+ case CLK_I2C_PMU:
+ rk_clrsetreg(&cru->clksel_con[34], CLK_I2C0_SEL_MASK,
+ src_clk << CLK_I2C0_SEL_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+ return rv1103b_i2c_get_clk(priv, clk_id);
+}
+
+static ulong rv1103b_spi_get_clk(struct rv1103b_clk_priv *priv, ulong clk_id)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ u32 sel, con, rate;
+
+ switch (clk_id) {
+ case CLK_SPI0:
+ con = readl(&cru->clksel_con[34]);
+ sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+ if (sel == CLK_SPI0_SEL_200M)
+ rate = 200 * MHz;
+ else if (sel == CLK_SPI0_SEL_100M)
+ rate = 100 * MHz;
+ else if (sel == CLK_SPI0_SEL_50M)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+
+ return rate;
+}
+
+static ulong rv1103b_spi_set_clk(struct rv1103b_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ int src_clk;
+
+ if (rate >= 198 * MHz)
+ src_clk = CLK_SPI0_SEL_200M;
+ else if (rate >= 99 * MHz)
+ src_clk = CLK_SPI0_SEL_100M;
+ else if (rate >= 48 * MHz)
+ src_clk = CLK_SPI0_SEL_50M;
+ else
+ src_clk = CLK_SPI0_SEL_24M;
+
+ switch (clk_id) {
+ case CLK_SPI0:
+ rk_clrsetreg(&cru->clksel_con[34], CLK_SPI0_SEL_MASK,
+ src_clk << CLK_SPI0_SEL_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rv1103b_spi_get_clk(priv, clk_id);
+}
+
+static ulong rv1103b_pwm_get_clk(struct rv1103b_clk_priv *priv, ulong clk_id)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ u32 sel, con;
+
+ switch (clk_id) {
+ case CLK_PWM0:
+ case CLK_PWM0_SRC:
+ con = readl(&cru->clksel_con[34]);
+ sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT;
+ break;
+ case CLK_PWM1:
+ con = readl(&cru->clksel_con[34]);
+ sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;
+ break;
+ case CLK_PWM2:
+ con = readl(&cru->clksel_con[34]);
+ sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ switch (sel) {
+ case CLK_PWM_SEL_100M:
+ return 100 * MHz;
+ case CLK_PWM_SEL_24M:
+ return OSC_HZ;
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rv1103b_pwm_set_clk(struct rv1103b_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ int src_clk;
+
+ if (rate >= 99 * MHz)
+ src_clk = CLK_PWM_SEL_100M;
+ else
+ src_clk = CLK_PWM_SEL_24M;
+
+ switch (clk_id) {
+ case CLK_PWM0:
+ case CLK_PWM0_SRC:
+ rk_clrsetreg(&cru->clksel_con[34],
+ CLK_PWM0_SEL_MASK,
+ src_clk << CLK_PWM0_SEL_SHIFT);
+ break;
+ case CLK_PWM1:
+ rk_clrsetreg(&cru->clksel_con[34],
+ CLK_PWM1_SEL_MASK,
+ src_clk << CLK_PWM1_SEL_SHIFT);
+ break;
+ case CLK_PWM2:
+ rk_clrsetreg(&cru->clksel_con[34],
+ CLK_PWM2_SEL_MASK,
+ src_clk << CLK_PWM2_SEL_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rv1103b_pwm_get_clk(priv, clk_id);
+}
+
+static ulong rv1103b_adc_get_clk(struct rv1103b_clk_priv *priv, ulong clk_id)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ u32 div, con;
+
+ switch (clk_id) {
+ case CLK_SARADC:
+ con = readl(&cru->peri_clksel_con[1]);
+ div = (con & CLK_SARADC_DIV_MASK) >>
+ CLK_SARADC_DIV_SHIFT;
+ return DIV_TO_RATE(OSC_HZ, div);
+ case CLK_TSADC_TSEN:
+ con = readl(&cru->peri_clksel_con[0]);
+ div = (con & CLK_TSADC_TSEN_DIV_MASK) >>
+ CLK_TSADC_TSEN_DIV_SHIFT;
+ return DIV_TO_RATE(OSC_HZ, div);
+ case CLK_TSADC:
+ con = readl(&cru->peri_clksel_con[0]);
+ div = (con & CLK_TSADC_DIV_MASK) >> CLK_TSADC_DIV_SHIFT;
+ return DIV_TO_RATE(OSC_HZ, div);
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rv1103b_adc_set_clk(struct rv1103b_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ int src_clk_div;
+
+ src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);
+
+ switch (clk_id) {
+ case CLK_SARADC:
+ assert(src_clk_div - 1 <= 7);
+ rk_clrsetreg(&cru->peri_clksel_con[1],
+ CLK_SARADC_DIV_MASK,
+ (src_clk_div - 1) <<
+ CLK_SARADC_DIV_SHIFT);
+ break;
+ case CLK_TSADC_TSEN:
+ assert(src_clk_div - 1 <= 32);
+ rk_clrsetreg(&cru->peri_clksel_con[0],
+ CLK_TSADC_TSEN_DIV_MASK,
+ (src_clk_div - 1) <<
+ CLK_TSADC_TSEN_DIV_SHIFT);
+ break;
+ case CLK_TSADC:
+ assert(src_clk_div - 1 <= 32);
+ rk_clrsetreg(&cru->peri_clksel_con[0],
+ CLK_TSADC_DIV_MASK,
+ (src_clk_div - 1) <<
+ CLK_TSADC_DIV_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+ return rv1103b_adc_get_clk(priv, clk_id);
+}
+
+/*
+ *
+ * rational_best_approximation(31415, 10000,
+ * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+static void rational_best_approximation(unsigned long given_numerator,
+ unsigned long given_denominator,
+ unsigned long max_numerator,
+ unsigned long max_denominator,
+ unsigned long *best_numerator,
+ unsigned long *best_denominator)
+{
+ unsigned long n, d, n0, d0, n1, d1;
+
+ n = given_numerator;
+ d = given_denominator;
+ n0 = 0;
+ d1 = 0;
+ n1 = 1;
+ d0 = 1;
+ for (;;) {
+ unsigned long t, a;
+
+ if (n1 > max_numerator || d1 > max_denominator) {
+ n1 = n0;
+ d1 = d0;
+ break;
+ }
+ if (d == 0)
+ break;
+ t = d;
+ a = n / d;
+ d = n % d;
+ n = t;
+ t = n0 + a * n1;
+ n0 = n1;
+ n1 = t;
+ t = d0 + a * d1;
+ d0 = d1;
+ d1 = t;
+ }
+ *best_numerator = n1;
+ *best_denominator = d1;
+}
+
+static ulong rv1103b_uart_get_rate(struct rv1103b_clk_priv *priv, ulong clk_id)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ u32 reg, con, fracdiv, div, src, p_rate;
+ unsigned long m, n;
+
+ switch (clk_id) {
+ case SCLK_UART0:
+ reg = 10;
+ con = readl(&cru->clksel_con[32]);
+ src = (con & CLK_UART0_SEL_MASK) >> CLK_UART0_SEL_SHIFT;
+ con = readl(&cru->clksel_con[5]);
+ div = (con & CLK_UART0_SRC_DIV_MASK) >> CLK_UART0_SRC_DIV_SHIFT;
+ break;
+ case SCLK_UART1:
+ reg = 11;
+ con = readl(&cru->clksel_con[32]);
+ src = (con & CLK_UART1_SEL_MASK) >> CLK_UART1_SEL_SHIFT;
+ con = readl(&cru->clksel_con[5]);
+ div = (con & CLK_UART1_SRC_DIV_MASK) >> CLK_UART1_SRC_DIV_SHIFT;
+ break;
+ case SCLK_UART2:
+ reg = 12;
+ con = readl(&cru->clksel_con[32]);
+ src = (con & CLK_UART2_SEL_MASK) >> CLK_UART2_SEL_SHIFT;
+ con = readl(&cru->clksel_con[5]);
+ div = (con & CLK_UART2_SRC_DIV_MASK) >> CLK_UART2_SRC_DIV_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ p_rate = priv->gpll_hz;
+ if (src == CLK_UART_SEL_SRC) {
+ return DIV_TO_RATE(p_rate, div);
+ } else if (src == CLK_UART_SEL_FRAC) {
+ fracdiv = readl(&cru->clksel_con[reg]);
+ n = fracdiv & CLK_UART_FRAC_NUMERATOR_MASK;
+ n >>= CLK_UART_FRAC_NUMERATOR_SHIFT;
+ m = fracdiv & CLK_UART_FRAC_DENOMINATOR_MASK;
+ m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT;
+ return DIV_TO_RATE(p_rate, div) * n / m;
+ } else {
+ return OSC_HZ;
+ }
+}
+
+static ulong rv1103b_uart_set_rate(struct rv1103b_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ u32 reg, uart_src, div;
+ unsigned long m = 0, n = 0, val;
+
+ if (priv->gpll_hz % rate == 0) {
+ uart_src = CLK_UART_SEL_SRC;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ } else if (rate == OSC_HZ) {
+ uart_src = CLK_UART_SEL_OSC;
+ div = 2;
+ } else {
+ uart_src = CLK_UART_SEL_FRAC;
+ div = 2;
+ rational_best_approximation(rate, priv->gpll_hz / div,
+ GENMASK(16 - 1, 0),
+ GENMASK(16 - 1, 0),
+ &m, &n);
+ }
+
+ switch (clk_id) {
+ case SCLK_UART0:
+ reg = 10;
+ rk_clrsetreg(&cru->clksel_con[5],
+ CLK_UART0_SRC_DIV_MASK,
+ div << CLK_UART0_SRC_DIV_SHIFT);
+ rk_clrsetreg(&cru->clksel_con[32],
+ CLK_UART0_SEL_MASK,
+ uart_src << CLK_UART0_SEL_SHIFT);
+ break;
+ case SCLK_UART1:
+ reg = 11;
+ rk_clrsetreg(&cru->clksel_con[5],
+ CLK_UART1_SRC_DIV_MASK,
+ div << CLK_UART1_SRC_DIV_SHIFT);
+ rk_clrsetreg(&cru->clksel_con[32],
+ CLK_UART1_SEL_MASK,
+ uart_src << CLK_UART1_SEL_SHIFT);
+ break;
+ case SCLK_UART2:
+ reg = 12;
+ rk_clrsetreg(&cru->clksel_con[5],
+ CLK_UART2_SRC_DIV_MASK,
+ div << CLK_UART2_SRC_DIV_SHIFT);
+ rk_clrsetreg(&cru->clksel_con[32],
+ CLK_UART2_SEL_MASK,
+ uart_src << CLK_UART2_SEL_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+ if (m && n) {
+ val = m << CLK_UART_FRAC_NUMERATOR_SHIFT | n;
+ writel(val, &cru->clksel_con[reg]);
+ }
+
+ return rv1103b_uart_get_rate(priv, clk_id);
+}
+
+static ulong rv1103b_decom_get_clk(struct rv1103b_clk_priv *priv)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ u32 sel, con, prate;
+
+ con = readl(&cru->clksel_con[35]);
+ sel = (con & DCLK_DECOM_SEL_MASK) >>
+ DCLK_DECOM_SEL_SHIFT;
+ if (sel == DCLK_DECOM_SEL_480M)
+ prate = 480 * MHz;
+ else if (sel == DCLK_DECOM_SEL_400M)
+ prate = 400 * MHz;
+ else
+ prate = 300 * MHz;
+ return prate;
+}
+
+static ulong rv1103b_decom_set_clk(struct rv1103b_clk_priv *priv, ulong rate)
+{
+ struct rv1103b_cru *cru = priv->cru;
+ u32 sel;
+
+ if (rate >= 480 * MHz)
+ sel = DCLK_DECOM_SEL_480M;
+ else if (rate >= 396 * MHz)
+ sel = DCLK_DECOM_SEL_400M;
+ else
+ sel = DCLK_DECOM_SEL_300M;
+ rk_clrsetreg(&cru->clksel_con[35], DCLK_DECOM_SEL_MASK,
+ (sel << DCLK_DECOM_SEL_SHIFT));
+
+ return rv1103b_decom_get_clk(priv);
+}
+
+static ulong rv1103b_clk_get_rate(struct clk *clk)
+{
+ struct rv1103b_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong rate = 0;
+
+ if (!priv->gpll_hz) {
+ printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
+ return -ENOENT;
+ }
+
+ switch (clk->id) {
+ case PLL_GPLL:
+ rate = rockchip_pll_get_rate(&rv1103b_pll_clks[GPLL], priv->cru,
+ GPLL);
+ break;
+ case ACLK_PERI_SRC:
+ case LSCLK_PERI_SRC:
+ case PCLK_PERI_ROOT:
+ case PCLK_TOP_ROOT:
+ case LSCLK_PMU_ROOT:
+ case PCLK_PMU:
+ rate = rv1103b_peri_get_clk(priv, clk->id);
+ break;
+ case ACLK_CRYPTO:
+ case HCLK_CRYPTO:
+ case HCLK_RK_RNG_NS:
+ case HCLK_RK_RNG_S:
+ case CLK_CORE_CRYPTO:
+ case CLK_PKA_CRYPTO:
+ rate = rv1103b_crypto_get_clk(priv, clk->id);
+ break;
+ case CCLK_SDMMC1:
+ case HCLK_SDMMC1:
+ case CCLK_SDMMC0:
+ case HCLK_SDMMC0:
+ case CCLK_EMMC:
+ case HCLK_EMMC:
+ case SCLK_SFC_2X:
+ case HCLK_SFC:
+ rate = rv1103b_mmc_get_clk(priv, clk->id);
+ break;
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C_PERI:
+ case CLK_I2C0:
+ case CLK_I2C_PMU:
+ rate = rv1103b_i2c_get_clk(priv, clk->id);
+ break;
+ case CLK_SPI0:
+ rate = rv1103b_spi_get_clk(priv, clk->id);
+ break;
+ case CLK_PWM0:
+ case CLK_PWM0_SRC:
+ case CLK_PWM1:
+ case CLK_PWM2:
+ rate = rv1103b_pwm_get_clk(priv, clk->id);
+ break;
+ case CLK_SARADC:
+ case CLK_TSADC_TSEN:
+ case CLK_TSADC:
+ rate = rv1103b_adc_get_clk(priv, clk->id);
+ break;
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ rate = rv1103b_uart_get_rate(priv, clk->id);
+ break;
+ case DCLK_DECOM_SRC:
+ case DCLK_DECOM:
+ rate = rv1103b_decom_get_clk(priv);
+ break;
+ case TCLK_WDT_LPMCU:
+ case TCLK_WDT_HPMCU:
+ case TCLK_WDT_NS:
+ case TCLK_WDT_S:
+ rate = OSC_HZ;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+};
+
+static ulong rv1103b_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct rv1103b_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong ret = 0;
+
+ if (!priv->gpll_hz) {
+ printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
+ return -ENOENT;
+ }
+
+ switch (clk->id) {
+ case PLL_GPLL:
+ ret = rockchip_pll_set_rate(&rv1103b_pll_clks[GPLL], priv->cru,
+ GPLL, rate);
+ break;
+ case ACLK_PERI_SRC:
+ case LSCLK_PERI_SRC:
+ case PCLK_PERI_ROOT:
+ case PCLK_TOP_ROOT:
+ case LSCLK_PMU_ROOT:
+ case PCLK_PMU:
+ ret = rv1103b_peri_set_clk(priv, clk->id, rate);
+ break;
+ case ACLK_CRYPTO:
+ case HCLK_CRYPTO:
+ case HCLK_RK_RNG_NS:
+ case HCLK_RK_RNG_S:
+ case CLK_CORE_CRYPTO:
+ case CLK_PKA_CRYPTO:
+ ret = rv1103b_crypto_set_clk(priv, clk->id, rate);
+ break;
+ case CCLK_SDMMC1:
+ case HCLK_SDMMC1:
+ case CCLK_SDMMC0:
+ case HCLK_SDMMC0:
+ case CCLK_EMMC:
+ case HCLK_EMMC:
+ case SCLK_SFC_2X:
+ case HCLK_SFC:
+ ret = rv1103b_mmc_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C_PERI:
+ case CLK_I2C0:
+ case CLK_I2C_PMU:
+ ret = rv1103b_i2c_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_SPI0:
+ ret = rv1103b_spi_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_PWM0:
+ case CLK_PWM0_SRC:
+ case CLK_PWM1:
+ case CLK_PWM2:
+ ret = rv1103b_pwm_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_SARADC:
+ case CLK_TSADC_TSEN:
+ case CLK_TSADC:
+ ret = rv1103b_adc_set_clk(priv, clk->id, rate);
+ break;
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ ret = rv1103b_uart_set_rate(priv, clk->id, rate);
+ break;
+ case DCLK_DECOM_SRC:
+ case DCLK_DECOM:
+ rate = rv1103b_decom_set_clk(priv, rate);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return ret;
+};
+
+static int rv1103b_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ switch (clk->id) {
+ default:
+ return -ENOENT;
+ }
+
+ return 0;
+}
+
+static struct clk_ops rv1103b_clk_ops = {
+ .get_rate = rv1103b_clk_get_rate,
+ .set_rate = rv1103b_clk_set_rate,
+#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))
+ .set_parent = rv1103b_clk_set_parent,
+#endif
+};
+
+static void rv1103b_clk_init(struct rv1103b_clk_priv *priv)
+{
+ int ret;
+ u32 div;
+
+ priv->sync_kernel = false;
+ priv->gpll_hz = rockchip_pll_get_rate(&rv1103b_pll_clks[GPLL],
+ priv->cru, GPLL);
+ if (priv->gpll_hz != GPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rv1103b_pll_clks[GPLL], priv->cru,
+ GPLL, GPLL_HZ);
+ if (!ret)
+ priv->gpll_hz = GPLL_HZ;
+ }
+
+ if (!priv->armclk_enter_hz) {
+ div = (readl(&priv->cru->clksel_con[37]) &
+ CLK_CORE_GPLL_DIV_MASK) >>
+ CLK_CORE_GPLL_DIV_SHIFT;
+ priv->armclk_enter_hz = DIV_TO_RATE(priv->gpll_hz, div);
+ priv->armclk_init_hz = priv->armclk_enter_hz;
+ }
+}
+
+static int rv1103b_clk_probe(struct udevice *dev)
+{
+ struct rv1103b_clk_priv *priv = dev_get_priv(dev);
+ int ret;
+
+#ifdef CONFIG_SPL_BUILD
+ /* fix lsclk_prei div */
+ writel(BITS_WITH_WMASK(1, 0x1U, 9), RV1103B_CRU_BASE + RV1103B_CLKSEL_CON(31));
+ /* fix cpu div */
+ writel(BITS_WITH_WMASK(1, 0x7U, 13), RV1103B_CRU_BASE + RV1103B_CLKSEL_CON(37));
+ /* fix gpll postdiv1 */
+ writel(BITS_WITH_WMASK(1, 0x7U, 12), RV1103B_CRU_BASE + RV1103B_PLL_CON(24));
+#endif
+
+ rv1103b_clk_init(priv);
+
+ /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
+ ret = clk_set_defaults(dev, 1);
+ if (ret)
+ debug("%s clk_set_defaults failed %d\n", __func__, ret);
+ else
+ priv->sync_kernel = true;
+ return 0;
+}
+
+static int rv1103_clk_of_to_plat(struct udevice *dev)
+{
+ struct rv1103_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = dev_read_addr_ptr(dev);
+
+ return 0;
+}
+
+static int rv1103b_clk_bind(struct udevice *dev)
+{
+ struct udevice *sys_child;
+ struct sysreset_reg *priv;
+ int ret;
+
+ /* The sysreset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rv1103b_cru, glb_srst_fst);
+ priv->glb_srst_snd_value = offsetof(struct rv1103b_cru, glb_srst_snd);
+ dev_set_priv(sys_child, priv);
+ }
+
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
+ ret = offsetof(struct rv1103b_cru, peri_softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 12); /* number of reset registers */
+ if (ret)
+ debug("Warning: software reset driver bind failed\n");
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id rv1103b_clk_ids[] = {
+ { .compatible = "rockchip,rv1103-cru" },
+ { }
+};
+
+U_BOOT_DRIVER(clk_rv1103) = {
+ .name = "clk_rv1103",
+ .id = UCLASS_CLK,
+ .of_match = rv1103b_clk_ids,
+ .priv_auto = sizeof(struct rv1103b_clk_priv),
+ .of_to_plat = rv1103_clk_of_to_plat,
+ .ops = &rv1103b_clk_ops,
+ .bind = rv1103b_clk_bind,
+ .probe = rv1103b_clk_probe,
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 3/7] tools: rkcommon: Add rv1103 support
2026-02-01 0:44 [PATCH 0/7] ARM: Add RV1103 Omega4 board support Fabio Estevam
2026-02-01 0:44 ` [PATCH 1/7] pinctrl: rockchip: Add support for RV1103 Fabio Estevam
2026-02-01 0:44 ` [PATCH 2/7] clk: " Fabio Estevam
@ 2026-02-01 0:44 ` Fabio Estevam
2026-02-01 1:44 ` Jonas Karlman
2026-02-01 0:44 ` [PATCH 4/7] rockchip: spl-boot-order: Add SPI NAND support Fabio Estevam
` (4 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Fabio Estevam @ 2026-02-01 0:44 UTC (permalink / raw)
To: kever.yang; +Cc: trini, u-boot, Fabio Estevam
From: Fabio Estevam <festevam@nabladev.com>
Allow rkcommon to generate an image for the RV1103.
Based on Rockchip U-Boot 2017.09 next-dev branch.
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
tools/rkcommon.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index e7e78ef7e5b7..c680c0144fef 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -148,6 +148,7 @@ static struct spl_info spl_infos[] = {
{ "rk3328", "RK32", 0x8000 - 0x800, false, RK_HEADER_V1 },
{ "rk3368", "RK33", 0x8000 - 0x1000, false, RK_HEADER_V1 },
{ "rk3399", "RK33", 0x30000 - 0x2000, false, RK_HEADER_V1 },
+ { "rv1103", "RV11", 0x40000 - 0x1000, false, RK_HEADER_V2 },
{ "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
{ "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
{ "rk3528", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 3/7] tools: rkcommon: Add rv1103 support
2026-02-01 0:44 ` [PATCH 3/7] tools: rkcommon: Add rv1103 support Fabio Estevam
@ 2026-02-01 1:44 ` Jonas Karlman
0 siblings, 0 replies; 12+ messages in thread
From: Jonas Karlman @ 2026-02-01 1:44 UTC (permalink / raw)
To: Fabio Estevam, Fabio Estevam; +Cc: kever.yang, trini, u-boot
Hi Fabio,
On 2/1/2026 1:44 AM, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@nabladev.com>
>
> Allow rkcommon to generate an image for the RV1103.
>
> Based on Rockchip U-Boot 2017.09 next-dev branch.
This very closely matches the vendor version [1] and should most likely
keep source From/Signed-off-by tags?
[1] https://github.com/rockchip-linux/u-boot/commit/05a029d3fe9ad682fb6fa13ff81b2cb7a9e6fe34
> Signed-off-by: Fabio Estevam <festevam@nabladev.com>
> ---
> tools/rkcommon.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tools/rkcommon.c b/tools/rkcommon.c
> index e7e78ef7e5b7..c680c0144fef 100644
> --- a/tools/rkcommon.c
> +++ b/tools/rkcommon.c
> @@ -148,6 +148,7 @@ static struct spl_info spl_infos[] = {
> { "rk3328", "RK32", 0x8000 - 0x800, false, RK_HEADER_V1 },
> { "rk3368", "RK33", 0x8000 - 0x1000, false, RK_HEADER_V1 },
> { "rk3399", "RK33", 0x30000 - 0x2000, false, RK_HEADER_V1 },
> + { "rv1103", "RV11", 0x40000 - 0x1000, false, RK_HEADER_V2 },
This should most likely use rv1103b, and also please keep the vendor
header tag 110E, something I expect matches the maskrom usb pid.
The rv11 line seem to use following usb pid enumeration:
rv1108 - 0x110a
rv1126 - 0x110b
rv1106 - 0x110c
???
rv1103b - 0x110e
rv1126b - 0x110f
Regards,
Jonas
> { "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
> { "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
> { "rk3528", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 4/7] rockchip: spl-boot-order: Add SPI NAND support
2026-02-01 0:44 [PATCH 0/7] ARM: Add RV1103 Omega4 board support Fabio Estevam
` (2 preceding siblings ...)
2026-02-01 0:44 ` [PATCH 3/7] tools: rkcommon: Add rv1103 support Fabio Estevam
@ 2026-02-01 0:44 ` Fabio Estevam
2026-02-01 0:44 ` [PATCH 5/7] spl: Add SPI NAND support via MTD in SPL Fabio Estevam
` (3 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Fabio Estevam @ 2026-02-01 0:44 UTC (permalink / raw)
To: kever.yang; +Cc: trini, u-boot, Fabio Estevam
From: Fabio Estevam <festevam@nabladev.com>
Make spl-boot-order to accept booting from SPI NAND as well.
With this change, it is possible to specify spi_nand as the boot medium
like this:
u-boot,spl-boot-order = &spi_nand;
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
arch/arm/mach-rockchip/spl-boot-order.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c
index 6572dde29f65..e5897536934a 100644
--- a/arch/arm/mach-rockchip/spl-boot-order.c
+++ b/arch/arm/mach-rockchip/spl-boot-order.c
@@ -4,6 +4,7 @@
*/
#include <dm.h>
+#include <dm/device_compat.h>
#include <fdt_support.h>
#include <log.h>
#include <mmc.h>
@@ -75,6 +76,8 @@ static int spl_node_to_boot_device(int node)
*/
if (!uclass_find_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
return BOOT_DEVICE_SPI;
+ if (fdt_node_check_compatible(gd->fdt_blob, node, "spi-nand") == 0)
+ return BOOT_DEVICE_SPI;
return -1;
}
@@ -221,8 +224,12 @@ int spl_decode_boot_device(u32 boot_device, char *buf, size_t buflen)
ret = uclass_find_device_by_of_offset(UCLASS_SPI_FLASH, node, &dev);
if (ret) {
- debug("%s: could not find udevice for %s\n", __func__, conf);
- continue;
+ ret = uclass_find_device_by_of_offset(UCLASS_MTD, node, &dev);
+ if (ret || !device_is_compatible(dev, "spi-nand")) {
+ debug("%s: could not find udevice for %s\n",
+ __func__, conf);
+ continue;
+ }
}
return ofnode_get_path(dev_ofnode(dev), buf, buflen);
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 5/7] spl: Add SPI NAND support via MTD in SPL
2026-02-01 0:44 [PATCH 0/7] ARM: Add RV1103 Omega4 board support Fabio Estevam
` (3 preceding siblings ...)
2026-02-01 0:44 ` [PATCH 4/7] rockchip: spl-boot-order: Add SPI NAND support Fabio Estevam
@ 2026-02-01 0:44 ` Fabio Estevam
2026-02-01 0:44 ` [PATCH 6/7] ARM: dts: Add RV1103 Omega4 support Fabio Estevam
` (2 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Fabio Estevam @ 2026-02-01 0:44 UTC (permalink / raw)
To: kever.yang; +Cc: trini, u-boot, Fabio Estevam
From: Fabio Estevam <festevam@nabladev.com>
Add support for booting U-Boot SPL from SPI NAND devices
using the MTD subsystem.
- Introduce CONFIG_SPL_SPI_NAND_LOAD to enable SPL loading
from SPI NAND flash.
- Implement spl_spi_nand.c as a dedicated SPL loader that
reads the FIT image from SPI NAND via MTD.
- Update common/spl/Kconfig and Makefiles to include the
new loader in SPL builds.
- Adjust drivers/mtd/Makefile and drivers/mtd/nand/Makefile
to build the necessary SPI NAND MTD objects only when
CONFIG_SPL_SPI_NAND_LOAD is enabled, avoiding size impact
on other boards.
This allows boards like the Omega4 RV1103 to boot SPL directly
from SPI NAND, keeping the SPL small and avoiding unnecessary
inclusion of SPI NOR code.
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
common/spl/Kconfig | 10 ++++-
common/spl/Makefile | 1 +
common/spl/spl_spi_nand.c | 82 +++++++++++++++++++++++++++++++++++++++
drivers/mtd/Makefile | 1 +
drivers/mtd/nand/Makefile | 13 ++++++-
5 files changed, 105 insertions(+), 2 deletions(-)
create mode 100644 common/spl/spl_spi_nand.c
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 2998b7acb75f..126855b804ce 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -1576,13 +1576,21 @@ config SPL_SPI_LOAD
Enable support for loading next stage, U-Boot or otherwise, from
SPI NOR in U-Boot SPL.
+config SPL_SPI_NAND_LOAD
+ bool "Support loading from SPI NAND flash"
+ depends on SPL
+ depends on MTD && DM_MTD
+ help
+ Enable support for loading next stage, U-Boot or otherwise, from
+ SPI NAND in U-Boot SPL.
+
endif # SPL_SPI_FLASH_SUPPORT
config SYS_SPI_U_BOOT_OFFS
hex "address of u-boot payload in SPI flash"
default 0x8000 if ARCH_SUNXI
default 0x0
- depends on SPL_SPI_LOAD || SPL_SPI_SUNXI
+ depends on SPL_SPI_LOAD || SPL_SPI_NAND_LOAD || SPL_SPI_SUNXI
help
Address within SPI-Flash from where the u-boot payload is fetched
from.
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 4c9482bd3096..4628902e7e31 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_$(PHASE_)NVME) += spl_nvme.o
obj-$(CONFIG_$(PHASE_)SEMIHOSTING) += spl_semihosting.o
obj-$(CONFIG_$(PHASE_)DFU) += spl_dfu.o
obj-$(CONFIG_$(PHASE_)SPI_LOAD) += spl_spi.o
+obj-$(CONFIG_$(PHASE_)SPI_NAND_LOAD) += spl_spi_nand.o
obj-$(CONFIG_$(PHASE_)RAM_SUPPORT) += spl_ram.o
obj-$(CONFIG_$(PHASE_)USB_SDP_SUPPORT) += spl_sdp.o
endif
diff --git a/common/spl/spl_spi_nand.c b/common/spl/spl_spi_nand.c
new file mode 100644
index 000000000000..20b877f75a05
--- /dev/null
+++ b/common/spl/spl_spi_nand.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * SPL loader for SPI NAND devices using the MTD subsystem.
+ *
+ * Based on spl_spi.c, which is:
+ *
+ * Copyright (C) 2011 OMICRON electronics GmbH
+ *
+ * based on drivers/mtd/nand/raw/nand_spl_load.c
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+
+#include <config.h>
+#include <image.h>
+#include <log.h>
+#include <errno.h>
+#include <spl.h>
+#include <spl_load.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <dm/ofnode.h>
+#include <dm/uclass.h>
+#include <mtd.h>
+
+static struct mtd_info *spl_spi_nand_get_mtd(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ for (ret = uclass_first_device_err(UCLASS_MTD, &dev);
+ dev;
+ ret = uclass_next_device_err(&dev)) {
+ if (ret)
+ continue;
+ if (device_is_compatible(dev, "spi-nand"))
+ return dev_get_uclass_priv(dev);
+ }
+
+ return NULL;
+}
+
+static ulong spl_spinand_fit_read(struct spl_load_info *load, ulong offs,
+ ulong size, void *buf)
+{
+ struct mtd_info *mtd = load->priv;
+ size_t retlen = 0;
+ int ret;
+
+ ret = mtd_read(mtd, offs, size, &retlen, buf);
+ if (ret && ret != -EUCLEAN) {
+ printf("SPI NAND read failed offs=0x%lx size=0x%lx ret=%d\n",
+ offs, size, ret);
+ return 0;
+ }
+ if (retlen != size)
+ return 0;
+
+ return retlen;
+}
+
+static int spl_spinand_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ struct spl_load_info load;
+ struct mtd_info *mtd;
+
+ mtd = spl_spi_nand_get_mtd();
+ if (!mtd) {
+ puts("SPI NAND probe failed.\n");
+ return -ENODEV;
+ }
+
+ spl_load_init(&load, spl_spinand_fit_read, mtd, 1);
+
+ return spl_load(spl_image, bootdev, &load, 0, CONFIG_SYS_SPI_U_BOOT_OFFS);
+}
+
+/* Use priority 1 so that boards can override this */
+SPL_LOAD_IMAGE_METHOD("SPI NAND", 1, BOOT_DEVICE_SPI, spl_spinand_load_image);
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index ce05e206073d..a12d880a9e90 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -34,6 +34,7 @@ else
ifneq ($(mtd-y),)
obj-$(CONFIG_SPL_MTD) += mtd.o
endif
+obj-$(CONFIG_SPL_SPI_NAND_LOAD) += nand/
obj-$(CONFIG_$(PHASE_)NAND_SUPPORT) += nand/
obj-$(CONFIG_SPL_ONENAND_SUPPORT) += onenand/
obj-$(CONFIG_$(PHASE_)SPI_FLASH_SUPPORT) += spi/
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index c8169cf73902..7cd2a5f1af9b 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -1,10 +1,21 @@
# SPDX-License-Identifier: GPL-2.0+
-ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),)
nandcore-objs := core.o bbt.o
+
+ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),)
+
+# U-Boot proper
obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
obj-$(CONFIG_MTD_RAW_NAND) += raw/
obj-$(CONFIG_MTD_SPI_NAND) += spi/
+
else
+
+# SPL / XPL / TPL
+# SPL has no MTD_NAND_CORE symbol, so we must key off SPI NAND usage
+obj-$(CONFIG_SPL_SPI_NAND_LOAD) += nandcore.o
+obj-$(CONFIG_SPL_SPI_NAND_LOAD) += spi/
+
+# raw NAND still follows the normal SPL rule
obj-$(CONFIG_$(PHASE_)NAND_SUPPORT) += raw/
endif
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 6/7] ARM: dts: Add RV1103 Omega4 support
2026-02-01 0:44 [PATCH 0/7] ARM: Add RV1103 Omega4 board support Fabio Estevam
` (4 preceding siblings ...)
2026-02-01 0:44 ` [PATCH 5/7] spl: Add SPI NAND support via MTD in SPL Fabio Estevam
@ 2026-02-01 0:44 ` Fabio Estevam
2026-02-01 0:44 ` [PATCH 7/7] omega4-rv1103: Add initial support Fabio Estevam
2026-02-01 1:12 ` [PATCH 0/7] ARM: Add RV1103 Omega4 board support Jonas Karlman
7 siblings, 0 replies; 12+ messages in thread
From: Fabio Estevam @ 2026-02-01 0:44 UTC (permalink / raw)
To: kever.yang; +Cc: trini, u-boot, Fabio Estevam
From: Fabio Estevam <festevam@nabladev.com>
Add minimal devicetree support for the Onion RV1103 Omega4 board.
These devicetrees are currently not upstream in Linux. They allow U-Boot to
boot the board and progress with development, independent of the Linux RV1103
upstream process.
Once the RV1103 devicetrees are merged into the upstream Linux kernel,
he OF_UPSTREAM mechanism can be enabled to use the kernel-provided devicetree.
This patch enables the Onion's Omega4 board to be supported in U-Boot
without blocking other upstreaming efforts.
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
arch/arm/dts/rv1103-omega4-u-boot.dtsi | 11 +
arch/arm/dts/rv1103-omega4.dts | 40 ++++
arch/arm/dts/rv1103-u-boot.dtsi | 4 +
arch/arm/dts/rv1103.dtsi | 267 +++++++++++++++++++++++++
4 files changed, 322 insertions(+)
create mode 100644 arch/arm/dts/rv1103-omega4-u-boot.dtsi
create mode 100644 arch/arm/dts/rv1103-omega4.dts
create mode 100644 arch/arm/dts/rv1103-u-boot.dtsi
create mode 100644 arch/arm/dts/rv1103.dtsi
diff --git a/arch/arm/dts/rv1103-omega4-u-boot.dtsi b/arch/arm/dts/rv1103-omega4-u-boot.dtsi
new file mode 100644
index 000000000000..d838206af4af
--- /dev/null
+++ b/arch/arm/dts/rv1103-omega4-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+// (C) Copyright 2024 Rockchip Electronics Co., Ltd
+
+#include "rockchip-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart0;
+ u-boot,spl-boot-order = &spi_nand;
+ };
+};
diff --git a/arch/arm/dts/rv1103-omega4.dts b/arch/arm/dts/rv1103-omega4.dts
new file mode 100644
index 000000000000..ebedf9843934
--- /dev/null
+++ b/arch/arm/dts/rv1103-omega4.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+// (C) Copyright 2024 Rockchip Electronics Co., Ltd
+
+/dts-v1/;
+#include "rv1103.dtsi"
+
+/ {
+ model = "Onion RV1103 Omega4 board";
+ compatible = "onion,rv1103-omega4", "rockchip,rv1103";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&sfc {
+ bootph-all;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi_nand: flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <24000000>;
+ bootph-all;
+ };
+};
+
+&uart0 {
+ bootph-pre-ram;
+ status = "okay";
+};
+
+&wdt {
+ bootph-pre-ram;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rv1103-u-boot.dtsi b/arch/arm/dts/rv1103-u-boot.dtsi
new file mode 100644
index 000000000000..3b77dd31152f
--- /dev/null
+++ b/arch/arm/dts/rv1103-u-boot.dtsi
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+// (C) Copyright 2024 Rockchip Electronics Co., Ltd
+
+#include "rockchip-u-boot.dtsi"
diff --git a/arch/arm/dts/rv1103.dtsi b/arch/arm/dts/rv1103.dtsi
new file mode 100644
index 000000000000..8ac7658231b1
--- /dev/null
+++ b/arch/arm/dts/rv1103.dtsi
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/clock/rv1103-cru.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "rockchip,rv1103";
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clocks = <&cru ARMCLK>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ cru: clock-controller@20000000 {
+ compatible = "rockchip,rv1103-cru";
+ reg = <0x20000000 0x81000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ assigned-clocks = <&cru PLL_GPLL>, <&cru CLK_GPLL_DIV12>;
+ assigned-clock-rates = <1188000000>, <100000000>;
+ bootph-all;
+ };
+
+ grf: syscon@20100000 {
+ compatible = "rockchip,rv1103-grf", "syscon", "simple-mfd";
+ reg = <0x20100000 0x61000>;
+ bootph-all;
+ };
+
+ ioc: syscon@20170000 {
+ compatible = "rockchip,rv1103-ioc", "syscon";
+ reg = <0x20170000 0x60000>;
+ bootph-all;
+ };
+
+ gic: interrupt-controller@20411000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0x20411000 0x1000>,
+ <0x20412000 0x2000>,
+ <0x20414000 0x2000>,
+ <0x20416000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ uart0: serial@20540000 {
+ compatible = "rockchip,rv1103-uart", "snps,dw-apb-uart";
+ reg = <0x20540000 0x100>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m0_xfer_pins>;
+ status = "disabled";
+ };
+
+ uart1: serial@20870000 {
+ compatible = "rockchip,rv1103-uart", "snps,dw-apb-uart";
+ reg = <0x20870000 0x100>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer_pins>;
+ status = "disabled";
+ };
+
+ uart2: serial@20880000 {
+ compatible = "rockchip,rv1103-uart", "snps,dw-apb-uart";
+ reg = <0x20880000 0x100>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m0_xfer_pins>;
+ status = "disabled";
+ };
+
+ wdt: watchdog@208d0000 {
+ compatible = "rockchip,rv1103-wdt", "snps,dw-wdt";
+ reg = <0x208d0000 0x100>;
+ clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
+ clock-names = "tclk", "pclk";
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sfc: spi@20d40000 {
+ compatible = "rockchip,sfc";
+ reg = <0x20d40000 0x4000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC_2X>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ system_sram: sram@210f6000 {
+ compatible = "mmio-sram";
+ reg = <0x210f6000 0x8000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x210f6000 0x8000>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rv1103-pinctrl";
+ rockchip,grf = <&ioc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ bootph-all;
+
+ gpio0: gpio@20520000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20520000 0x200>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ bootph-pre-ram;
+ };
+
+ gpio1: gpio@20d80000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20d80000 0x200>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ bootph-pre-ram;
+ };
+
+ gpio2: gpio@20840000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20840000 0x200>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ bootph-pre-ram;
+ };
+
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ spi0 {
+ spi0m0_clk_pins: spi0m0-clk-pins {
+ rockchip,pins =
+ /* spi0_clk_m0 */
+ <2 RK_PB0 2 &pcfg_pull_none>,
+ /* spi0_miso_m0 */
+ <2 RK_PB3 2 &pcfg_pull_none>,
+ /* spi0_mosi_m0 */
+ <2 RK_PB1 2 &pcfg_pull_none>;
+ };
+
+ spi0m0_cs0_pins: spi0m0-cs0-pins {
+ rockchip,pins =
+ /* spi0_cs0n_m0 */
+ <2 RK_PB2 2 &pcfg_pull_none>;
+ };
+
+ spi0m0_cs1_pins: spi0m0-cs1-pins {
+ rockchip,pins =
+ /* spi0_cs1n_m0 */
+ <2 RK_PA7 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ uart0m0_xfer_pins: uart0m0-xfer-pins {
+ rockchip,pins =
+ /* uart0_rx_m0 */
+ <0 RK_PA6 1 &pcfg_pull_up>,
+ /* uart0_tx_m0 */
+ <0 RK_PA5 1 &pcfg_pull_up>;
+ };
+ };
+
+ uart1 {
+ uart1m0_xfer_pins: uart1m0-xfer-pins {
+ rockchip,pins =
+ /* uart1_rx_m0 */
+ <0 RK_PB2 2 &pcfg_pull_up>,
+ /* uart1_tx_m0 */
+ <0 RK_PB3 2 &pcfg_pull_up>;
+ };
+ };
+
+ uart2 {
+ uart2m0_xfer_pins: uart2m0-xfer-pins {
+ rockchip,pins =
+ /* uart2_rx_m0 */
+ <0 RK_PB1 2 &pcfg_pull_up>,
+ /* uart2_tx_m0 */
+ <0 RK_PB0 2 &pcfg_pull_up>;
+ };
+ };
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 7/7] omega4-rv1103: Add initial support
2026-02-01 0:44 [PATCH 0/7] ARM: Add RV1103 Omega4 board support Fabio Estevam
` (5 preceding siblings ...)
2026-02-01 0:44 ` [PATCH 6/7] ARM: dts: Add RV1103 Omega4 support Fabio Estevam
@ 2026-02-01 0:44 ` Fabio Estevam
2026-02-01 1:12 ` [PATCH 0/7] ARM: Add RV1103 Omega4 board support Jonas Karlman
7 siblings, 0 replies; 12+ messages in thread
From: Fabio Estevam @ 2026-02-01 0:44 UTC (permalink / raw)
To: kever.yang; +Cc: trini, u-boot, Fabio Estevam
From: Fabio Estevam <festevam@nabladev.com>
Add the initial support for Onion's Omega4 RV1103 board.
It boots from the SPI NAND.
Tested the boot of a 6.6 OpenWRT kernel.
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
arch/arm/include/asm/arch-rv1103/boot0.h | 11 +
arch/arm/mach-rockchip/Kconfig | 14 +
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rv1103/Kconfig | 23 +
arch/arm/mach-rockchip/rv1103/Makefile | 12 +
arch/arm/mach-rockchip/rv1103/boot0.h | 5 +
arch/arm/mach-rockchip/rv1103/clk_rv1103.c | 32 ++
arch/arm/mach-rockchip/rv1103/rv1103.c | 133 +++++
arch/arm/mach-rockchip/rv1103/syscon_rv1103.c | 19 +
board/onion/omega4_rv1103/Kconfig | 12 +
board/onion/omega4_rv1103/MAINTAINERS | 6 +
board/onion/omega4_rv1103/Makefile | 7 +
board/onion/omega4_rv1103/omega4_rv1103.c | 19 +
board/onion/omega4_rv1103/omega4_rv1103.env | 5 +
configs/omega4-rv1103_defconfig | 82 +++
doc/board/index.rst | 1 +
doc/board/onion/index.rst | 9 +
doc/board/onion/omega4-rv1103.rst | 56 ++
include/configs/omega4_rv1103.h | 11 +
include/configs/rv1103_common.h | 14 +
include/dt-bindings/clock/rv1103-cru.h | 489 ++++++++++++++++++
21 files changed, 961 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rv1103/boot0.h
create mode 100644 arch/arm/mach-rockchip/rv1103/Kconfig
create mode 100644 arch/arm/mach-rockchip/rv1103/Makefile
create mode 100644 arch/arm/mach-rockchip/rv1103/boot0.h
create mode 100644 arch/arm/mach-rockchip/rv1103/clk_rv1103.c
create mode 100644 arch/arm/mach-rockchip/rv1103/rv1103.c
create mode 100644 arch/arm/mach-rockchip/rv1103/syscon_rv1103.c
create mode 100644 board/onion/omega4_rv1103/Kconfig
create mode 100644 board/onion/omega4_rv1103/MAINTAINERS
create mode 100644 board/onion/omega4_rv1103/Makefile
create mode 100644 board/onion/omega4_rv1103/omega4_rv1103.c
create mode 100644 board/onion/omega4_rv1103/omega4_rv1103.env
create mode 100644 configs/omega4-rv1103_defconfig
create mode 100644 doc/board/onion/index.rst
create mode 100644 doc/board/onion/omega4-rv1103.rst
create mode 100644 include/configs/omega4_rv1103.h
create mode 100644 include/configs/rv1103_common.h
create mode 100644 include/dt-bindings/clock/rv1103-cru.h
diff --git a/arch/arm/include/asm/arch-rv1103/boot0.h b/arch/arm/include/asm/arch-rv1103/boot0.h
new file mode 100644
index 000000000000..2e78b074ade8
--- /dev/null
+++ b/arch/arm/include/asm/arch-rv1103/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 92bb4aa62f11..4aa2f6f39575 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -487,6 +487,19 @@ config ROCKCHIP_RK3588
SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet,
SDIO3.0 I2C, UART, SPI, GPIO and PWM.
+config ROCKCHIP_RV1103
+ bool "Support Rockchip RV1103"
+ select CPU_V7A
+ select SPL_ARMV7_SET_CORTEX_SMPEN
+ select SUPPORT_SPL
+ select SPL
+ imply ROCKCHIP_COMMON_BOARD
+
+ help
+ The Rockchip RV1103 is an ARM-based SoC with a single Cortex-A7
+ 32-bit core which integrates NEON and FPU.
+ It contains a built-in NPU for AI related applications.
+
config ROCKCHIP_RV1108
bool "Support Rockchip RV1108"
select CPU_V7A
@@ -749,6 +762,7 @@ source "arch/arm/mach-rockchip/rk3528/Kconfig"
source "arch/arm/mach-rockchip/rk3568/Kconfig"
source "arch/arm/mach-rockchip/rk3576/Kconfig"
source "arch/arm/mach-rockchip/rk3588/Kconfig"
+source "arch/arm/mach-rockchip/rv1103/Kconfig"
source "arch/arm/mach-rockchip/rv1108/Kconfig"
source "arch/arm/mach-rockchip/rv1126/Kconfig"
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 06fb527b21a0..ece2d3d83b51 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_ROCKCHIP_RK3528) += rk3528/
obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
obj-$(CONFIG_ROCKCHIP_RK3576) += rk3576/
obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
+obj-$(CONFIG_ROCKCHIP_RV1103) += rv1103/
obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
diff --git a/arch/arm/mach-rockchip/rv1103/Kconfig b/arch/arm/mach-rockchip/rv1103/Kconfig
new file mode 100644
index 000000000000..d275230536ca
--- /dev/null
+++ b/arch/arm/mach-rockchip/rv1103/Kconfig
@@ -0,0 +1,23 @@
+if ROCKCHIP_RV1103
+
+
+config TARGET_OMEGA4_RV1103
+ bool "OMEGA4_RV1103"
+ help
+ Support Onion's Omega4 RV1103 board.
+
+config ROCKCHIP_BOOT_MODE_REG
+ default 0x20160200
+
+config ROCKCHIP_STIMER_BASE
+ default 0x20500000
+
+config SYS_SOC
+ default "rv1103"
+
+config SYS_MALLOC_F_LEN
+ default 0x400
+
+source "board/onion/omega4_rv1103/Kconfig"
+
+endif
diff --git a/arch/arm/mach-rockchip/rv1103/Makefile b/arch/arm/mach-rockchip/rv1103/Makefile
new file mode 100644
index 000000000000..3d6a4c378460
--- /dev/null
+++ b/arch/arm/mach-rockchip/rv1103/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += rv1103.o
+obj-y += clk_rv1103.o
+
+ifndef CONFIG_XPL_BUILD
+obj-y += syscon_rv1103.o
+endif
diff --git a/arch/arm/mach-rockchip/rv1103/boot0.h b/arch/arm/mach-rockchip/rv1103/boot0.h
new file mode 100644
index 000000000000..7d2c975f6677
--- /dev/null
+++ b/arch/arm/mach-rockchip/rv1103/boot0.h
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Dummy boot0.h for RV1103 — SoC does not require special boot0 setup. */
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+#endif
diff --git a/arch/arm/mach-rockchip/rv1103/clk_rv1103.c b/arch/arm/mach-rockchip/rv1103/clk_rv1103.c
new file mode 100644
index 000000000000..889ad64b39ea
--- /dev/null
+++ b/arch/arm/mach-rockchip/rv1103/clk_rv1103.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ */
+
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rv1103.h>
+#include <linux/err.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(clk_rv1103), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ struct rv1103_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
diff --git a/arch/arm/mach-rockchip/rv1103/rv1103.c b/arch/arm/mach-rockchip/rv1103/rv1103.c
new file mode 100644
index 000000000000..c8fce6f19dfd
--- /dev/null
+++ b/arch/arm/mach-rockchip/rv1103/rv1103.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (c) 2024 Rockchip Electronics Co., Ltd
+
+#include <dm.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <image.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PERI_CRU_BASE 0x20000000
+#define PERICRU_PERISOFTRST_CON10 0x0a28
+
+#define PMU0_CRU_BASE 0x20070000
+#define PMUCRU_PMUSOFTRST_CON02 0x0a08
+
+#define GRF_SYS_BASE 0x20150000
+#define GRF_SYS_HPMCU_CACHE_MISC 0x0214
+
+#define GPIO0_IOC_BASE 0x201B0000
+#define GPIO0A_IOMUX_SEL_H 0x04
+#define GPIO0_BASE 0x20520000
+#define GPIO_SWPORT_DR_L 0x00
+#define GPIO_SWPORT_DDR_L 0x08
+
+#define GPIO1_IOC_BASE 0x20170000
+#define GPIO1A_IOMUX_SEL_0 0x20
+#define GPIO1A_IOMUX_SEL_1_0 0x24
+#define GPIO1A_IOMUX_SEL_1_1 0x10024
+#define GPIO1B_IOMUX_SEL_0 0x10028
+#define GPIO1B_IOMUX_SEL_1 0x1002c
+#define GPIO1_IOC_GPIO1A_PULL_0 0x210
+#define GPIO1_IOC_GPIO1A_PULL_1 0x10210
+#define GPIO1_IOC_GPIO1B_PULL 0x10214
+#define GPIO1_IOC_JTAG_M2_CON 0x10810
+
+#define GPIO2_IOC_BASE 0x20840000
+#define GPIO2A_IOMUX_SEL_1_1 0x44
+
+#define SGRF_SYS_BASE 0x20250000
+#define SGRF_SYS_SOC_CON2 0x0008
+#define SGRF_SYS_SOC_CON3 0x000c
+#define SGRF_SYS_OTP_CON 0x0018
+#define FIREWALL_CON0 0x0020
+#define FIREWALL_CON1 0x0024
+#define FIREWALL_CON2 0x0028
+#define FIREWALL_CON3 0x002c
+#define FIREWALL_CON4 0x0030
+#define FIREWALL_CON5 0x0034
+#define FIREWALL_CON7 0x003c
+#define SGRF_SYS_HPMCU_BOOT_DDR 0x0080
+
+#define SGRF_PMU_BASE 0x20260000
+#define SGRF_PMU_SOC_CON0 0x0000
+#define SGRF_PMU_PMUMCU_BOOT_ADDR 0x0020
+
+#define SYS_GRF_BASE 0x20150000
+#define GRF_SYS_PERI_CON2 0x08
+#define GRF_SYS_USBPHY_CON0 0x50
+
+#define TOP_CRU_BASE 0x20060000
+#define TOPCRU_CRU_GLB_RST_CON 0xc10
+
+#define USBPHY_APB_BASE 0x20e10000
+#define USBPHY_FSLS_DIFF_RECEIVER 0x0100
+
+#define RV1103_WDT_BASE 0x208d0000
+#define RV1103_WDT_CR 0x00
+
+void board_debug_uart_init(void)
+{
+ /* No need to change uart */
+}
+
+#ifdef CONFIG_SPL_BUILD
+void rockchip_stimer_init(void)
+{
+ /* If Timer already enabled, don't re-init it */
+ u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
+
+ if (reg & 0x1)
+ return;
+ writel(0x00010000, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
+
+ asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(CONFIG_COUNTER_FREQUENCY));
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
+ writel(0x00010001, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
+}
+#endif
+
+#ifndef CONFIG_TPL_BUILD
+int arch_cpu_init(void)
+{
+ /* Stop any watchdog left running by BootROM/Boot1. */
+ writel(0, RV1103_WDT_BASE + RV1103_WDT_CR);
+
+#if defined(CONFIG_SPL_BUILD)
+ /* Set all devices to Non-secure */
+ writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON0);
+ writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON1);
+ writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON2);
+ writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON3);
+ writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON4);
+ writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON5);
+ writel(0x01f00000, SGRF_SYS_BASE + FIREWALL_CON7);
+ /* Set OTP to none secure mode */
+ writel(0x00020000, SGRF_SYS_BASE + SGRF_SYS_OTP_CON);
+
+ /* no-secure WDT reset output will reset SoC system. */
+ writel(0x00010001, SYS_GRF_BASE + GRF_SYS_PERI_CON2);
+ /* secure WDT reset output will reset SoC system. */
+ writel(0x00010001, SGRF_SYS_BASE + SGRF_SYS_SOC_CON2);
+ /*
+ * enable tsadc trigger global reset and select first reset.
+ * enable global reset and wdt trigger pmu reset.
+ * select first reset trigger pmu reset.
+ */
+ writel(0x0000ffdf, TOP_CRU_BASE + TOPCRU_CRU_GLB_RST_CON);
+
+ /*
+ * Set the USB2 PHY in suspend mode and turn off the
+ * USB2 PHY FS/LS differential receiver to save power:
+ * VCC1V8_USB : reduce 3.8 mA
+ * VDD_0V9 : reduce 4.4 mA
+ */
+ writel(0x01ff01d1, SYS_GRF_BASE + GRF_SYS_USBPHY_CON0);
+ writel(0x00000000, USBPHY_APB_BASE + USBPHY_FSLS_DIFF_RECEIVER);
+#endif
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-rockchip/rv1103/syscon_rv1103.c b/arch/arm/mach-rockchip/rv1103/syscon_rv1103.c
new file mode 100644
index 000000000000..c7d7493a03ab
--- /dev/null
+++ b/arch/arm/mach-rockchip/rv1103/syscon_rv1103.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id rv1103_syscon_ids[] = {
+ { .compatible = "rockchip,rv1103-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_rv1103) = {
+ .name = "rv1103_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rv1103_syscon_ids,
+};
diff --git a/board/onion/omega4_rv1103/Kconfig b/board/onion/omega4_rv1103/Kconfig
new file mode 100644
index 000000000000..22f31fe0df9b
--- /dev/null
+++ b/board/onion/omega4_rv1103/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMEGA4_RV1103
+
+config SYS_BOARD
+ default "omega4_rv1103"
+
+config SYS_VENDOR
+ default "onion"
+
+config SYS_CONFIG_NAME
+ default "omega4_rv1103"
+
+endif
diff --git a/board/onion/omega4_rv1103/MAINTAINERS b/board/onion/omega4_rv1103/MAINTAINERS
new file mode 100644
index 000000000000..48aa5208b69f
--- /dev/null
+++ b/board/onion/omega4_rv1103/MAINTAINERS
@@ -0,0 +1,6 @@
+OMEGA4 RV1103
+M: Fabio Estevam <festevam@nabladev.com>
+S: Maintained
+F: board/onion/omega4_rv1103
+F: include/configs/omega4_rv1103.h
+F: configs/omega4-rv1103_defconfig
diff --git a/board/onion/omega4_rv1103/Makefile b/board/onion/omega4_rv1103/Makefile
new file mode 100644
index 000000000000..6bd28f82282b
--- /dev/null
+++ b/board/onion/omega4_rv1103/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2026 Fabio Estevam <festevam@nabladev.com>
+#
+
+obj-y += omega4_rv1103.o
diff --git a/board/onion/omega4_rv1103/omega4_rv1103.c b/board/onion/omega4_rv1103/omega4_rv1103.c
new file mode 100644
index 000000000000..9bdec3c396a8
--- /dev/null
+++ b/board/onion/omega4_rv1103/omega4_rv1103.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2026 Fabio Estevam <festevam@nabladev.com>
+
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = SZ_256M;
+
+ return 0;
+}
+
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
+{
+ return gd->ram_top;
+}
diff --git a/board/onion/omega4_rv1103/omega4_rv1103.env b/board/onion/omega4_rv1103/omega4_rv1103.env
new file mode 100644
index 000000000000..7ed232cab916
--- /dev/null
+++ b/board/onion/omega4_rv1103/omega4_rv1103.env
@@ -0,0 +1,5 @@
+kernel_addr_r=0x00800000
+fdt_addr_r=0x02000000
+ramdisk_addr_r=0x04000000
+bootargs=console=ttyS0,115200 mtdparts=spi1.0:256K(env),1M@256K(idblock),1M(uboot),8M(boot),-(ubi) ro rootwait ubi.mtd=ubi ubi.block=0,rootfs root=/dev/ubiblock0_0 rootfstype=squashfs
+bootcmd=mtd read spi-nand0 0x04000000 0x240000 0x800000;imxtract 0x04000000 kernel 0x00800000; imxtract 0x04000000 fdt 0x02000000; bootz 0x00800000 - 0x02000000
diff --git a/configs/omega4-rv1103_defconfig b/configs/omega4-rv1103_defconfig
new file mode 100644
index 000000000000..b9b017ccc75e
--- /dev/null
+++ b/configs/omega4-rv1103_defconfig
@@ -0,0 +1,82 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_SYS_ARCH_TIMER=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00200000
+CONFIG_SYS_MALLOC_F_LEN=0x80000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x00400000
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_DEFAULT_DEVICE_TREE="rv1103-omega4"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
+CONFIG_ROCKCHIP_RV1103=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_ROCKCHIP_EXTERNAL_TPL=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_OMEGA4_RV1103=y
+CONFIG_SYS_BOOTM_LEN=0x04000000
+CONFIG_SYS_LOAD_ADDR=0x00008000
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_DEBUG_UART_BASE=0x20540000
+CONFIG_DEBUG_UART_CLOCK=24000000
+# CONFIG_DEBUG_UART_BOARD_INIT is not set
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_CIPHER=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_BEST_MATCH=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_NO_BSS_LIMIT=y
+CONFIG_SPL_MTD=y
+CONFIG_SPL_SPI_NAND_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+CONFIG_NO_NET=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+# CONFIG_MMC is not set
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_ROCKCHIP_RV1103=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+# CONFIG_RSA is not set
+# CONFIG_SPL_SHA1 is not set
+# CONFIG_SPL_SHA256 is not set
+CONFIG_LZMA=y
+CONFIG_SPL_LZMA=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 7870f1bc2461..d859f8a22bfe 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -45,6 +45,7 @@ Board-specific doc
motorola/index
nvidia/index
nxp/index
+ onion/index
openpiton/index
ouya/index
pegatron/index
diff --git a/doc/board/onion/index.rst b/doc/board/onion/index.rst
new file mode 100644
index 000000000000..5dab233a861e
--- /dev/null
+++ b/doc/board/onion/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Onion
+=====
+
+.. toctree::
+ :maxdepth: 2
+
+ omega4-rv1103
diff --git a/doc/board/onion/omega4-rv1103.rst b/doc/board/onion/omega4-rv1103.rst
new file mode 100644
index 000000000000..942e7ae1b2ce
--- /dev/null
+++ b/doc/board/onion/omega4-rv1103.rst
@@ -0,0 +1,56 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Onion Omega4 RV1103 board
+=========================
+
+U-Boot for the Onion Omega4 RV1103 board
+
+Quick Start
+-----------
+
+- Get the DDR initialization binary
+- Build U-Boot
+- Flash U-Boot into the SPI NAND
+
+Get the DDR initialization binary
+---------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/rockchip-linux/rkbin.git
+
+The RV1103 DDR initialization is located at rkbin/bin/rv11/rv1103b_ddr_924MHz_v1.05.bin
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=arm-linux-gnueabihf-
+ $ export ROCKCHIP_TPL=<path-to-rkbin>/bin/rv11/rv1103b_ddr_924MHz_v1.05.bin
+ $ make omega4-rv1103_defconfig
+ $ make
+
+The idbloader-spi.img and u-boot.img are the binaries that need to be flashed
+into the SPI NAND.
+
+Flash U-Boot into the SPI NAND
+------------------------------
+
+Connect the USB OTG and UART console cables from the Omega4 board to
+the host PC.
+
+Press the BOOT button while applying power to the board.
+
+The string "RKUART" should appear on the console (115200,8N1).
+
+Install the rkdeveloptool from https://github.com/rockchip-linux/rkdeveloptool
+by following the instruction in the README file.
+
+.. code-block:: bash
+
+ $ sudo ./rkdeveloptool db download.bin
+ $ sudo ./rkdeveloptool wl 0x200 idbloader.img
+ $ sudo ./rkdeveloptool wl 0xa00 u-boot.img
+
+Power cycle the board and U-Boot output is seen on the console.
diff --git a/include/configs/omega4_rv1103.h b/include/configs/omega4_rv1103.h
new file mode 100644
index 000000000000..771e3fcf1ad0
--- /dev/null
+++ b/include/configs/omega4_rv1103.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/rv1103_common.h>
+
+#endif
diff --git a/include/configs/rv1103_common.h b/include/configs/rv1103_common.h
new file mode 100644
index 000000000000..14dea08d0fb5
--- /dev/null
+++ b/include/configs/rv1103_common.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+#ifndef __CONFIG_RV1103_COMMON_H
+#define __CONFIG_RV1103_COMMON_H
+
+#include "rockchip-common.h"
+#include <config_distro_bootcmd.h>
+
+#define CFG_IRAM_BASE 0x210f6000
+#define CFG_SYS_SDRAM_BASE 0x00000000
+
+#endif
diff --git a/include/dt-bindings/clock/rv1103-cru.h b/include/dt-bindings/clock/rv1103-cru.h
new file mode 100644
index 000000000000..8cc40d8a7c79
--- /dev/null
+++ b/include/dt-bindings/clock/rv1103-cru.h
@@ -0,0 +1,489 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_RV1103_CRU_H
+#define _DT_BINDINGS_CLK_RV1103_CRU_H
+
+/* pll clocks */
+#define PLL_GPLL 1
+#define ARMCLK 2
+
+/* clk (clocks) */
+#define XIN_OSC0_HALF 5
+#define CLK_GPLL_DIV24 6
+#define CLK_GPLL_DIV12 7
+#define CLK_GPLL_DIV6 8
+#define CLK_GPLL_DIV4 9
+#define CLK_GPLL_DIV3 10
+#define CLK_GPLL_DIV2P5 11
+#define CLK_GPLL_DIV2 12
+#define CLK_UART0_SRC 13
+#define CLK_UART1_SRC 14
+#define CLK_UART2_SRC 15
+#define CLK_UART0_FRAC 16
+#define CLK_UART1_FRAC 17
+#define CLK_UART2_FRAC 18
+#define CLK_SAI_SRC 19
+#define CLK_SAI_FRAC 20
+#define LSCLK_NPU_SRC 21
+#define CLK_NPU_SRC 22
+#define ACLK_VEPU_SRC 23
+#define CLK_VEPU_SRC 24
+#define ACLK_VI_SRC 25
+#define CLK_ISP_SRC 26
+#define DCLK_VICAP 27
+#define CCLK_EMMC 28
+#define CCLK_SDMMC0 29
+#define SCLK_SFC_2X 30
+#define LSCLK_PERI_SRC 31
+#define ACLK_PERI_SRC 32
+#define HCLK_HPMCU 33
+#define SCLK_UART0 34
+#define SCLK_UART1 35
+#define SCLK_UART2 36
+#define CLK_I2C_PMU 37
+#define CLK_I2C_PERI 38
+#define CLK_SPI0 39
+#define CLK_PWM0_SRC 40
+#define CLK_PWM1 41
+#define CLK_PWM2 42
+#define DCLK_DECOM_SRC 43
+#define CCLK_SDMMC1 44
+#define CLK_CORE_CRYPTO 45
+#define CLK_PKA_CRYPTO 46
+#define CLK_CORE_RGA 47
+#define MCLK_SAI_SRC 48
+#define CLK_FREQ_PWM0_SRC 49
+#define CLK_COUNTER_PWM0_SRC 50
+#define PCLK_TOP_ROOT 51
+#define CLK_REF_MIPI0 52
+#define CLK_MIPI0_OUT2IO 53
+#define CLK_REF_MIPI1 54
+#define CLK_MIPI1_OUT2IO 55
+#define MCLK_SAI_OUT2IO 56
+#define ACLK_NPU_ROOT 57
+#define HCLK_RKNN 58
+#define ACLK_RKNN 59
+#define LSCLK_VEPU_ROOT 60
+#define HCLK_VEPU 61
+#define ACLK_VEPU 62
+#define CLK_CORE_VEPU 63
+#define PCLK_IOC_VCCIO3 64
+#define PCLK_ACODEC 65
+#define PCLK_USBPHY 66
+#define LSCLK_VI_100M 67
+#define LSCLK_VI_ROOT 68
+#define HCLK_ISP 69
+#define ACLK_ISP 70
+#define CLK_CORE_ISP 71
+#define ACLK_VICAP 72
+#define HCLK_VICAP 73
+#define ISP0CLK_VICAP 74
+#define PCLK_CSI2HOST0 75
+#define PCLK_CSI2HOST1 76
+#define HCLK_EMMC 77
+#define HCLK_SFC 78
+#define HCLK_SFC_XIP 79
+#define HCLK_SDMMC0 80
+#define PCLK_CSIPHY 81
+#define PCLK_GPIO1 82
+#define DBCLK_GPIO1 83
+#define PCLK_IOC_VCCIO47 84
+#define LSCLK_DDR_ROOT 85
+#define CLK_TIMER_DDRMON 86
+#define LSCLK_PMU_ROOT 87
+#define PCLK_PMU 88
+#define XIN_RC_DIV 89
+#define CLK_32K 90
+#define PCLK_PMU_GPIO0 91
+#define DBCLK_PMU_GPIO0 92
+#define CLK_DDR_FAIL_SAFE 93
+#define PCLK_PMU_HP_TIMER 94
+#define CLK_PMU_32K_HP_TIMER 95
+#define PCLK_PWM0 96
+#define CLK_PWM0 97
+#define CLK_OSC_PWM0 98
+#define CLK_RC_PWM0 99
+#define CLK_FREQ_PWM0 100
+#define CLK_COUNTER_PWM0 101
+#define PCLK_I2C0 102
+#define CLK_I2C0 103
+#define PCLK_UART0 104
+#define PCLK_IOC_PMUIO0 105
+#define CLK_REFOUT 106
+#define CLK_PREROLL 107
+#define CLK_PREROLL_32K 108
+#define CLK_LPMCU_PMU 109
+#define PCLK_SPI2AHB 110
+#define HCLK_SPI2AHB 111
+#define SCLK_SPI2AHB 112
+#define PCLK_WDT_LPMCU 113
+#define TCLK_WDT_LPMCU 114
+#define HCLK_SFC_PMU1 115
+#define HCLK_SFC_XIP_PMU1 116
+#define SCLK_SFC_2X_PMU1 117
+#define CLK_LPMCU 118
+#define CLK_LPMCU_RTC 119
+#define PCLK_LPMCU_MAILBOX 120
+#define PCLK_IOC_PMUIO1 121
+#define PCLK_CRU_PMU1 122
+#define PCLK_PERI_ROOT 123
+#define PCLK_RTC_ROOT 124
+#define CLK_TIMER_ROOT 125
+#define PCLK_TIMER 126
+#define CLK_TIMER0 127
+#define CLK_TIMER1 128
+#define CLK_TIMER2 129
+#define CLK_TIMER3 130
+#define CLK_TIMER4 131
+#define CLK_TIMER5 132
+#define PCLK_STIMER 133
+#define CLK_STIMER0 134
+#define CLK_STIMER1 135
+#define PCLK_WDT_NS 136
+#define TCLK_WDT_NS 137
+#define PCLK_WDT_S 138
+#define TCLK_WDT_S 139
+#define PCLK_WDT_HPMCU 140
+#define TCLK_WDT_HPMCU 141
+#define PCLK_I2C1 142
+#define CLK_I2C1 143
+#define PCLK_I2C2 144
+#define CLK_I2C2 145
+#define PCLK_I2C3 146
+#define CLK_I2C3 147
+#define PCLK_I2C4 148
+#define CLK_I2C4 149
+#define PCLK_SPI0 150
+#define PCLK_PWM1 151
+#define CLK_OSC_PWM1 152
+#define PCLK_PWM2 153
+#define CLK_OSC_PWM2 154
+#define PCLK_UART2 155
+#define PCLK_UART1 156
+#define ACLK_RKDMA 157
+#define PCLK_TSADC 158
+#define CLK_TSADC 159
+#define CLK_TSADC_TSEN 160
+#define PCLK_SARADC 161
+#define CLK_SARADC 162
+#define PCLK_GPIO2 163
+#define DBCLK_GPIO2 164
+#define PCLK_IOC_VCCIO6 165
+#define ACLK_USBOTG 166
+#define CLK_REF_USBOTG 167
+#define HCLK_SDMMC1 168
+#define HCLK_SAI 169
+#define MCLK_SAI 170
+#define ACLK_CRYPTO 171
+#define HCLK_CRYPTO 172
+#define HCLK_RK_RNG_NS 173
+#define HCLK_RK_RNG_S 174
+#define PCLK_OTPC_NS 175
+#define CLK_OTPC_ROOT_NS 176
+#define CLK_SBPI_OTPC_NS 177
+#define CLK_USER_OTPC_NS 178
+#define PCLK_OTPC_S 179
+#define CLK_OTPC_ROOT_S 180
+#define CLK_SBPI_OTPC_S 181
+#define CLK_USER_OTPC_S 182
+#define CLK_OTPC_ARB 183
+#define PCLK_OTP_MASK 184
+#define HCLK_RGA 185
+#define ACLK_RGA 186
+#define ACLK_MAC 187
+#define PCLK_MAC 188
+#define CLK_MACPHY 189
+#define ACLK_SPINLOCK 190
+#define HCLK_CACHE 191
+#define PCLK_HPMCU_MAILBOX 192
+#define PCLK_HPMCU_INTMUX 193
+#define CLK_HPMCU 194
+#define CLK_HPMCU_RTC 195
+#define DCLK_DECOM 196
+#define ACLK_DECOM 197
+#define PCLK_DECOM 198
+#define ACLK_SYS_SRAM 199
+#define PCLK_DMA2DDR 200
+#define ACLK_DMA2DDR 201
+#define PCLK_DCF 202
+#define ACLK_DCF 203
+#define MCLK_ACODEC_TX 204
+#define SCLK_UART0_SRC 205
+#define SCLK_UART1_SRC 206
+#define SCLK_UART2_SRC 207
+#define XIN_RC_SRC 208
+#define CLK_UTMI_USBOTG 209
+#define CLK_REF_USBPHY 230
+
+#define CLK_NR_CLKS (CLK_REF_USBPHY + 1)
+
+// PERICRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_ARESETN_PERI_BIU 0x00000002
+#define SRST_HRESETN_HPMCU_BIU 0x00000003
+#define SRST_LSRESETN_PERI_BIU 0x00000004
+#define SRST_PRESETN_PERI_BIU 0x00000005
+#define SRST_PRESETN_RTC_BIU 0x00000006
+#define SRST_HRESETN_BOOTROM 0x00000007
+
+// PERICRU_SOFTRST_CON01(Offset:0xA04)
+#define SRST_PRESETN_TIMER 0x00000010
+#define SRST_RESETN_TIMER0 0x00000011
+#define SRST_RESETN_TIMER1 0x00000012
+#define SRST_RESETN_TIMER2 0x00000013
+#define SRST_RESETN_TIMER3 0x00000014
+#define SRST_RESETN_TIMER4 0x00000015
+#define SRST_RESETN_TIMER5 0x00000016
+#define SRST_PRESETN_STIMER 0x00000017
+#define SRST_RESETN_STIMER0 0x00000018
+#define SRST_RESETN_STIMER1 0x00000019
+
+// PERICRU_SOFTRST_CON02(Offset:0xA08)
+#define SRST_PRESETN_WDT_NS 0x00000020
+#define SRST_TRESETN_WDT_NS 0x00000021
+#define SRST_PRESETN_WDT_S 0x00000022
+#define SRST_TRESETN_WDT_S 0x00000023
+#define SRST_PRESETN_WDT_HPMCU 0x00000024
+#define SRST_TRESETN_WDT_HPMCU 0x00000025
+#define SRST_PRESETN_I2C1 0x00000026
+#define SRST_RESETN_I2C1 0x00000027
+#define SRST_PRESETN_I2C2 0x00000028
+#define SRST_RESETN_I2C2 0x00000029
+#define SRST_PRESETN_I2C3 0x0000002A
+#define SRST_RESETN_I2C3 0x0000002B
+#define SRST_PRESETN_I2C4 0x0000002C
+#define SRST_RESETN_I2C4 0x0000002D
+
+// PERICRU_SOFTRST_CON03(Offset:0xA0C)
+#define SRST_PRESETN_UART2 0x00000030
+#define SRST_SRESETN_UART2 0x00000031
+#define SRST_PRESETN_UART1 0x00000032
+#define SRST_SRESETN_UART1 0x00000033
+#define SRST_PRESETN_SPI0 0x0000003A
+#define SRST_RESETN_SPI0 0x0000003B
+
+// PERICRU_SOFTRST_CON04(Offset:0xA10)
+#define SRST_PRESETN_PWM1 0x00000046
+#define SRST_RESETN_PWM1 0x00000047
+#define SRST_PRESETN_PWM2 0x0000004C
+#define SRST_RESETN_PWM2 0x0000004D
+
+// PERICRU_SOFTRST_CON05(Offset:0xA14)
+#define SRST_ARESETN_RKDMA 0x00000058
+#define SRST_PRESETN_TSADC 0x00000059
+#define SRST_RESETN_TSADC 0x0000005A
+#define SRST_PRESETN_SARADC 0x0000005C
+#define SRST_RESETN_SARADC 0x0000005D
+
+// PERICRU_SOFTRST_CON06(Offset:0xA18)
+#define SRST_RESETN_SARADC_PHY 0x00000060
+#define SRST_PRESETN_RTC_TEST 0x00000061
+#define SRST_PRESETN_GPIO2 0x00000063
+#define SRST_DBRESETN_GPIO2 0x00000064
+#define SRST_PRESETN_IOC_VCCIO6 0x00000065
+#define SRST_PRESETN_PERI_SGRF 0x00000066
+#define SRST_PRESETN_PERI_GRF 0x00000067
+#define SRST_PRESETN_CRU_PERI 0x00000068
+#define SRST_ARESETN_USBOTG 0x00000069
+
+// PERICRU_SOFTRST_CON07(Offset:0xA1C)
+#define SRST_HRESETN_SDMMC1 0x00000070
+#define SRST_HRESETN_SAI 0x00000071
+#define SRST_MRESETN_SAI 0x00000072
+
+// PERICRU_SOFTRST_CON08(Offset:0xA20)
+#define SRST_RESETN_CORE_CRYPTO 0x00000080
+#define SRST_RESETN_PKA_CRYPTO 0x00000081
+#define SRST_ARESETN_CRYPTO 0x00000082
+#define SRST_HRESETN_CRYPTO 0x00000083
+#define SRST_HRESETN_RK_RNG_NS 0x00000084
+#define SRST_HRESETN_RK_RNG_S 0x00000085
+#define SRST_PRESETN_OTPC_NS 0x00000086
+#define SRST_RESETN_SBPI_OTPC_NS 0x00000088
+#define SRST_RESETN_USER_OTPC_NS 0x00000089
+#define SRST_PRESETN_OTPC_S 0x0000008A
+#define SRST_RESETN_SBPI_OTPC_S 0x0000008C
+#define SRST_RESETN_USER_OTPC_S 0x0000008D
+#define SRST_RESETN_OTPC_ARB 0x0000008E
+#define SRST_PRESETN_OTP_MASK 0x0000008F
+
+// PERICRU_SOFTRST_CON09(Offset:0xA24)
+#define SRST_HRESETN_RGA 0x00000090
+#define SRST_ARESETN_RGA 0x00000091
+#define SRST_RESETN_CORE_RGA 0x00000092
+#define SRST_ARESETN_MAC 0x00000093
+#define SRST_RESETN_MACPHY 0x0000009B
+
+// PERICRU_SOFTRST_CON10(Offset:0xA28)
+#define SRST_ARESETN_SPINLOCK 0x000000A0
+#define SRST_HRESETN_CACHE 0x000000A1
+#define SRST_PRESETN_HPMCU_MAILBOX 0x000000A2
+#define SRST_PRESETN_HPMCU_INTMUX 0x000000A3
+#define SRST_RESETN_HPMCU_FULL_CLUSTER 0x000000A4
+#define SRST_RESETN_HPMCU_PWUP 0x000000A5
+#define SRST_RESETN_HPMCU_ONLY_CORE 0x000000A6
+#define SRST_TRESETN_HPMCU_JTAG 0x000000A7
+
+// PERICRU_SOFTRST_CON11(Offset:0xA2C)
+#define SRST_DRESETN_DECOM 0x000000B0
+#define SRST_ARESETN_DECOM 0x000000B1
+#define SRST_PRESETN_DECOM 0x000000B2
+#define SRST_ARESETN_SYS_SRAM 0x000000B3
+#define SRST_PRESETN_DMA2DDR 0x000000B4
+#define SRST_ARESETN_DMA2DDR 0x000000B5
+#define SRST_PRESETN_DCF 0x000000B6
+#define SRST_ARESETN_DCF 0x000000B7
+#define SRST_RESETN_USBPHY_POR 0x000000BC
+#define SRST_RESETN_USBPHY_OTG 0x000000BD
+
+// ======================= VEPUCRU module definition bank=1 =======================
+// VEPUCRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_ARESETN_VEPU_BIU 0x00040001
+#define SRST_LSRESETN_VEPU_BIU 0x00040002
+#define SRST_RESETN_REF_PVTPLL_VEPU 0x00040003
+#define SRST_HRESETN_VEPU 0x00040004
+#define SRST_ARESETN_VEPU 0x00040005
+#define SRST_RESETN_CORE_VEPU 0x00040006
+#define SRST_PRESETN_VEPU_PVTPLL 0x00040007
+#define SRST_PRESETN_CRU_VEPU 0x00040008
+#define SRST_PRESETN_VEPU_GRF 0x0004000A
+#define SRST_PRESETN_IOC_VCCIO3 0x0004000B
+#define SRST_PRESETN_ACODEC 0x0004000D
+#define SRST_PRESETN_USBPHY 0x0004000E
+
+// ======================= NPUCRU module definition bank=2 ========================
+// NPUCRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_RESETN_REF_PVTPLL_NPU 0x00080000
+#define SRST_ARESETN_NPU_BIU 0x00080002
+#define SRST_LSRESETN_NPU_BIU 0x00080003
+#define SRST_HRESETN_RKNN 0x00080004
+#define SRST_ARESETN_RKNN 0x00080005
+#define SRST_PRESETN_NPU_PVTPLL 0x00080006
+#define SRST_PRESETN_CRU_NPU 0x00080007
+#define SRST_PRESETN_NPU_GRF 0x00080009
+
+// ======================== VICRU module definition bank=3 ========================
+// VICRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_LSRESETN_VI_BIU 0x000c0001
+#define SRST_ARESETN_VI_BIU 0x000c0002
+#define SRST_RESETN_REF_PVTPLL_ISP 0x000c0003
+#define SRST_RESETN_CORE_ISP 0x000c0006
+
+// VICRU_SOFTRST_CON01(Offset:0xA04)
+#define SRST_DRESETN_VICAP 0x000c0010
+#define SRST_ARESETN_VICAP 0x000c0012
+#define SRST_HRESETN_VICAP 0x000c0013
+#define SRST_ISP0RESETN_VICAP 0x000c0018
+#define SRST_PRESETN_CSI2HOST0 0x000c0019
+#define SRST_PRESETN_CSI2HOST1 0x000c001B
+#define SRST_SRESETN_SFC_2X 0x000c001C
+#define SRST_HRESETN_EMMC 0x000c001D
+#define SRST_HRESETN_SFC 0x000c001E
+#define SRST_HRESETN_SFC_XIP 0x000c001F
+
+// VICRU_SOFTRST_CON02(Offset:0xA08)
+#define SRST_HRESETN_SDMMC0 0x000c0020
+#define SRST_PRESETN_CSIPHY 0x000c0022
+#define SRST_PRESETN_GPIO1 0x000c0023
+#define SRST_DBRESETN_GPIO1 0x000c0024
+#define SRST_PRESETN_IOC_VCCIO47 0x000c0025
+#define SRST_PRESETN_VI_GRF 0x000c0026
+#define SRST_PRESETN_CRU_VI 0x000c0028
+#define SRST_PRESETN_VI_PVTPLL 0x000c0029
+
+// ======================= CORECRU module definition bank=4 =======================
+// CORECRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_RESETN_REF_PVTPLL_CORE 0x00100000
+#define SRST_NCOREPORESET 0x00100001
+#define SRST_NCORESET 0x00100002
+#define SRST_NDBGRESET 0x00100003
+#define SRST_NL2RESET 0x00100004
+#define SRST_ARESETN_CORE_BIU 0x00100005
+#define SRST_PRESETN_CORE_BIU 0x00100006
+#define SRST_HRESETN_CORE_BIU 0x00100007
+#define SRST_PRESETN_DBG 0x00100008
+#define SRST_POTRESETN_DBG 0x00100009
+#define SRST_NTRESETN_DBG 0x0010000A
+
+// ======================= DDRCRU module definition bank=5 ========================
+// DDRCRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_LSRESETN_DDR_BIU 0x00140001
+#define SRST_PRESETN_DDRC 0x00140002
+#define SRST_PRESETN_DDRMON 0x00140003
+#define SRST_RESETN_TIMER_DDRMON 0x00140004
+#define SRST_PRESETN_DFICTRL 0x00140005
+#define SRST_PRESETN_DDR_GRF 0x00140006
+#define SRST_PRESETN_CRU_DDR 0x00140007
+#define SRST_HRESETN_DDRPHY 0x00140008
+
+// ====================== SUBDDRCRU module definition bank=6 ======================
+// SUBDDRCRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_RESETN_DDR_BIU 0x00160001
+#define SRST_ARESETN_DDRSCH_CPU 0x00160002
+#define SRST_ARESETN_DDRSCH_VI 0x00160004
+#define SRST_ARESETN_DDRSCH_NPVD 0x00160005
+#define SRST_RESETN_CORE_DDRC 0x00160006
+#define SRST_RESETN_DDRMON 0x00160007
+#define SRST_RESETN_DFICTRL 0x00160008
+#define SRST_RESETN_DFI_SCRAMBLE 0x00160009
+
+// ======================= TOPCRU module definition bank=7 ========================
+// TOPCRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_PRESETN_CRU 0x00180000
+#define SRST_PRESETN_CRU_BIU 0x00180001
+#define SRST_RESETN_DDRPHY 0x0018000C
+
+//======================= PMUCRU module definition bank=8 ========================
+// PMUCRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_PRESETN_PMU_GPIO0 0x001c0004
+#define SRST_DBRESETN_PMU_GPIO0 0x001c0005
+#define SRST_RESETN_DDR_FAIL_SAFE 0x001c0008
+#define SRST_PRESETN_PMU_HP_TIMER 0x001c0009
+#define SRST_RESETN_PMU_HP_TIMER 0x001c000A
+#define SRST_RESETN_PMU_32K_HP_TIMER 0x001c000B
+#define SRST_PRESETN_I2C0 0x001c000C
+#define SRST_RESETN_I2C0 0x001c000D
+#define SRST_PRESETN_UART0 0x001c000E
+#define SRST_SRESETN_UART0 0x001c000F
+
+// PMUCRU_SOFTRST_CON01(Offset:0xA04)
+#define SRST_PRESETN_IOC_PMUIO0 0x001c0010
+#define SRST_PRESETN_CRU_PMU 0x001c0011
+#define SRST_PRESETN_PMU_GRF 0x001c0012
+#define SRST_PRESETN_PMU_SGRF 0x001c0013
+#define SRST_PRESETN_PMU_SGRF_REMAP 0x001c0014
+#define SRST_RESETN_PREROLL 0x001c0016
+#define SRST_RESETN_PREROLL_32K 0x001c0017
+#define SRST_HRESETN_PMU_SRAM 0x001c0018
+#define SRST_PRESETN_PWM0 0x001c0019
+#define SRST_RESETN_PWM0 0x001c001A
+
+// PMUCRU_SOFTRST_CON02(Offset:0xA08)
+#define SRST_RESETN_LPMCU 0x001c0020
+#define SRST_RESETN_LPMCU_PWRUP 0x001c0021
+#define SRST_RESETN_LPMCU_CPU 0x001c0022
+#define SRST_TRESETN_LPMCU_CPU 0x001c0023
+
+// ======================= PMU1CRU module definition bank=9 =======================
+// PMU1CRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_PRESETN_SPI2AHB 0x00200000
+#define SRST_HRESETN_SPI2AHB 0x00200001
+#define SRST_SRESETN_SPI2AHB 0x00200002
+#define SRST_LSRESETN_PMU_BIU 0x00200003
+#define SRST_PRESETN_WDT_LPMCU 0x00200009
+#define SRST_TRESETN_WDT_LPMCU 0x0020000A
+#define SRST_HRESETN_SFC_PMU1 0x0020000C
+#define SRST_HRESETN_SFC_XIP_PMU1 0x0020000D
+#define SRST_SRESETN_SFC_2X_PMU1 0x0020000E
+
+// PMU1CRU_SOFTRST_CON01(Offset:0xA04)
+#define SRST_PRESETN_LPMCU_MAILBOX 0x00200018
+#define SRST_PRESETN_IOC_PMUIO1 0x00200019
+#define SRST_PRESETN_CRU_PMU1 0x0020001A
+
+#define CLK_NR_SRST (SRST_PRESETN_CRU_PMU1 + 1)
+
+#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 0/7] ARM: Add RV1103 Omega4 board support
2026-02-01 0:44 [PATCH 0/7] ARM: Add RV1103 Omega4 board support Fabio Estevam
` (6 preceding siblings ...)
2026-02-01 0:44 ` [PATCH 7/7] omega4-rv1103: Add initial support Fabio Estevam
@ 2026-02-01 1:12 ` Jonas Karlman
2026-02-03 15:10 ` Fabio Estevam
7 siblings, 1 reply; 12+ messages in thread
From: Jonas Karlman @ 2026-02-01 1:12 UTC (permalink / raw)
To: Fabio Estevam, Fabio Estevam; +Cc: kever.yang, trini, u-boot
Hi Fabio,
On 2/1/2026 1:44 AM, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@nabladev.com>
>
> Hi,
>
> This patch series adds support for the Onion RV1103 Omega4 board to U-Boot.
> It covers SPL, SPI NAND boot, and the minimal board devicetree required to
> boot the board.
This series seem to handle the RV1103B variant and not the RV1106/RV1103
variant, please name parts as rv1103b to match vendor U-Boot or is the
rv1106/rv1103 and rv1103b fully compatible?
> Upstreaming the RV1103 devicetree in Linux is ongoing, but to avoid blocking
> U-Boot support, this series introduces board-specific devicetrees for now.
> Once the Linux RV1103 devicetrees are upstreamed, the OF_UPSTREAM mechanism
> can be enabled.
For the Rockchip platform we typically expect e.g. dt-bindings headers
for core parts to be upstreamed to Linux and picked from dts/upstream
for new SoC support.
Please at least send out clk and pinctrl dt-bindings and drivers for
Linux before a v2 of this series :-)
Regards,
Jonas
> Fabio Estevam (7):
> pinctrl: rockchip: Add support for RV1103
> clk: rockchip: Add support for RV1103
> tools: rkcommon: Add rv1103 support
> rockchip: spl-boot-order: Add SPI NAND support
> spl: Add SPI NAND support via MTD in SPL
> ARM: dts: Add RV1103 Omega4 support
> omega4-rv1103: Add initial support
>
> arch/arm/dts/rv1103-omega4-u-boot.dtsi | 11 +
> arch/arm/dts/rv1103-omega4.dts | 40 +
> arch/arm/dts/rv1103-u-boot.dtsi | 4 +
> arch/arm/dts/rv1103.dtsi | 267 +++++
> .../include/asm/arch-rockchip/cru_rv1103.h | 271 +++++
> .../include/asm/arch-rockchip/grf_rv1103.h | 31 +
> arch/arm/include/asm/arch-rv1103/boot0.h | 11 +
> arch/arm/mach-rockchip/Kconfig | 14 +
> arch/arm/mach-rockchip/Makefile | 1 +
> arch/arm/mach-rockchip/rv1103/Kconfig | 23 +
> arch/arm/mach-rockchip/rv1103/Makefile | 12 +
> arch/arm/mach-rockchip/rv1103/boot0.h | 5 +
> arch/arm/mach-rockchip/rv1103/clk_rv1103.c | 32 +
> arch/arm/mach-rockchip/rv1103/rv1103.c | 133 ++
> arch/arm/mach-rockchip/rv1103/syscon_rv1103.c | 19 +
> arch/arm/mach-rockchip/spl-boot-order.c | 11 +-
> board/onion/omega4_rv1103/Kconfig | 12 +
> board/onion/omega4_rv1103/MAINTAINERS | 6 +
> board/onion/omega4_rv1103/Makefile | 7 +
> board/onion/omega4_rv1103/omega4_rv1103.c | 19 +
> board/onion/omega4_rv1103/omega4_rv1103.env | 5 +
> common/spl/Kconfig | 10 +-
> common/spl/Makefile | 1 +
> common/spl/spl_spi_nand.c | 82 ++
> configs/omega4-rv1103_defconfig | 82 ++
> doc/board/index.rst | 1 +
> doc/board/onion/index.rst | 9 +
> doc/board/onion/omega4-rv1103.rst | 56 +
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk_rv1103.c | 1068 +++++++++++++++++
> drivers/mtd/Makefile | 1 +
> drivers/mtd/nand/Makefile | 13 +-
> drivers/pinctrl/Kconfig | 10 +
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl-rv1103.c | 411 +++++++
> include/configs/omega4_rv1103.h | 11 +
> include/configs/rv1103_common.h | 14 +
> include/dt-bindings/clock/rv1103-cru.h | 489 ++++++++
> tools/rkcommon.c | 1 +
> 39 files changed, 3191 insertions(+), 4 deletions(-)
> create mode 100644 arch/arm/dts/rv1103-omega4-u-boot.dtsi
> create mode 100644 arch/arm/dts/rv1103-omega4.dts
> create mode 100644 arch/arm/dts/rv1103-u-boot.dtsi
> create mode 100644 arch/arm/dts/rv1103.dtsi
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rv1103.h
> create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rv1103.h
> create mode 100644 arch/arm/include/asm/arch-rv1103/boot0.h
> create mode 100644 arch/arm/mach-rockchip/rv1103/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rv1103/Makefile
> create mode 100644 arch/arm/mach-rockchip/rv1103/boot0.h
> create mode 100644 arch/arm/mach-rockchip/rv1103/clk_rv1103.c
> create mode 100644 arch/arm/mach-rockchip/rv1103/rv1103.c
> create mode 100644 arch/arm/mach-rockchip/rv1103/syscon_rv1103.c
> create mode 100644 board/onion/omega4_rv1103/Kconfig
> create mode 100644 board/onion/omega4_rv1103/MAINTAINERS
> create mode 100644 board/onion/omega4_rv1103/Makefile
> create mode 100644 board/onion/omega4_rv1103/omega4_rv1103.c
> create mode 100644 board/onion/omega4_rv1103/omega4_rv1103.env
> create mode 100644 common/spl/spl_spi_nand.c
> create mode 100644 configs/omega4-rv1103_defconfig
> create mode 100644 doc/board/onion/index.rst
> create mode 100644 doc/board/onion/omega4-rv1103.rst
> create mode 100644 drivers/clk/rockchip/clk_rv1103.c
> create mode 100644 drivers/pinctrl/rockchip/pinctrl-rv1103.c
> create mode 100644 include/configs/omega4_rv1103.h
> create mode 100644 include/configs/rv1103_common.h
> create mode 100644 include/dt-bindings/clock/rv1103-cru.h
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 0/7] ARM: Add RV1103 Omega4 board support
2026-02-01 1:12 ` [PATCH 0/7] ARM: Add RV1103 Omega4 board support Jonas Karlman
@ 2026-02-03 15:10 ` Fabio Estevam
0 siblings, 0 replies; 12+ messages in thread
From: Fabio Estevam @ 2026-02-03 15:10 UTC (permalink / raw)
To: Jonas Karlman; +Cc: Fabio Estevam, kever.yang, trini, u-boot
Hi Jonas,
On Sat, Jan 31, 2026 at 10:12 PM Jonas Karlman <jonas@kwiboo.se> wrote:
> This series seem to handle the RV1103B variant and not the RV1106/RV1103
> variant, please name parts as rv1103b to match vendor U-Boot or is the
> rv1106/rv1103 and rv1103b fully compatible?
Thanks for your review. I appreciate it.
Initially, I was unaware of the differences between the RV1106/RV1103
and RV1103B.
After reading your message, I investigated Rockchip's SDK and
confirmed that RV1106/RV1103 are compatible, but RV1103B has a
completely different memory map.
For v2, I'll change the references to RV1103B accordingly.
> For the Rockchip platform we typically expect e.g. dt-bindings headers
> for core parts to be upstreamed to Linux and picked from dts/upstream
> for new SoC support.
> Please at least send out clk and pinctrl dt-bindings and drivers for
> Linux before a v2 of this series :-)
I'll work on upstreaming support for the RV1103B in Linux. I was able
to get some early kernel messages via earlycon, but the clock driver
is still not functional at the moment.
Thanks,
Fabio Estevam
^ permalink raw reply [flat|nested] 12+ messages in thread