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From: Tom Rini <trini@konsulko.com>
To: Greg Malysa <malysagreg@gmail.com>
Cc: u-boot@lists.denx.de, Brian Sune <briansune@gmail.com>,
	Phil Phil Sutter <phil@nwl.cc>,
	Richard Henderson <richard.henderson@linaro.org>,
	Ilias Apalodimas <ilias.apalodimas@linaro.org>,
	Marek Vasut <marek.vasut+renesas@mailbox.org>,
	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>,
	Nathan Barrett-Morrison <nathan.morrison@timesys.com>,
	Ian Roberts <ian.roberts@timesys.com>,
	Vasileios Bimpikas <vasileios.bimpikas@analog.com>,
	Utsav Agarwal <utsav.agarwal@analog.com>,
	Arturs Artamonovs <arturs.artamonovs@analog.com>,
	adsp-linux@analog.com
Subject: Re: [PATCH v2] arm: spl: Ensure 8 byte alignment of appended DTB without separate BSS
Date: Mon, 9 Feb 2026 08:30:05 -0600	[thread overview]
Message-ID: <20260209143005.GF2603314@bill-the-cat> (raw)
In-Reply-To: <CABdDSeWvfd2vK2ykQb12YrXreaq7oiuHDktgrCm+c94_6aj=Mg@mail.gmail.com>

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On Fri, Feb 06, 2026 at 07:02:07PM -0500, Greg Malysa wrote:
> Hi Tom,
> 
> On Thu, Feb 5, 2026 at 6:42 PM Tom Rini <trini@konsulko.com> wrote:
> >
> > Which means second, 64bit ARM platforms. With the exception of:
> > socfpga_agilex7m socfpga_n5x_atf socfpga_n5x_vab socfpga_stratix10_atf
> > all ARM64 SPL_FRAMEWORK using platforms use the
> > arch/arm/cpu/armv8/u-boot-spl.lds explicitly. These other ones set
> > CONFIG_SPL_LDSCRIPT to a non-existant file and then fall back to using
> > arch/arm/cpu/armv8/u-boot-spl.lds. There are only 4 platforms which
> > don't use a separate BSS section and so could trip up the above as well:
> > r8a779g0_whitehawk r8a779g3_sparrowhawk sc598-som-ezkit-spl sc598-som-ezlite-spl
> > I have inspected the Renesas platforms manually, and I'm a little unsure
> > how this case works on the two sc598 platforms.
> 
> Do you recommend using SPL_SEPARATE_BSS on our platform? After power
> on, the sc598 has 2 MB of SRAM available starting at 0x20000000 which
> we treat as just a single block of memory to use for all of SPL
> operation, so we don't have any requirement to do something like a
> bare bones DDR initialization before using it as our main memory for
> SPL, so it didn't seem necessary to enable. The boot ROM has some
> guidelines on where it will place its stack, so we restrict SPL to the
> first 192 KB currently but this can easily be expanded. I'm not sure
> if I should admit to it, but some decisions on Kconfigs were made 4
> years ago as an arbitrary choice during our initial bringup and then
> were not reviewed because things were working.
> 
> Either way, works for me on the sc598 + ezkit. There's no reason for
> it to fail on the ezlite in that case either.

So SPL_SEPARATE_BSS is for when the BSS can be easily put in SDRAM
instead. It's not better or worse than SRAM, it just depends on the
system constraints. I only called these two platforms out because I
don't actually see where the dtb comes from and so couldn't check the
alignment and location matched.

-- 
Tom

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  reply	other threads:[~2026-02-09 14:30 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-30 18:36 [PATCH] spl: Ensure final section before BSS is non-empty Tom Rini
2026-02-02 17:42 ` Sune Brian
2026-02-05 23:41 ` [PATCH v2] arm: spl: Ensure 8 byte alignment of appended DTB without separate BSS Tom Rini
2026-02-06  0:43   ` Phil Sutter
2026-02-06  1:14   ` Sune Brian
2026-02-06 17:09   ` Marek Vasut
2026-02-06 18:00     ` Tom Rini
2026-02-07  0:02   ` Greg Malysa
2026-02-09 14:30     ` Tom Rini [this message]
2026-02-09 20:41   ` Tom Rini

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