[PATCH RFC 0/3] Add clk and pinctrl drivers for SM6125 SoC

[PATCH RFC 0/3] Add clk and pinctrl drivers for SM6125 SoC

[Biswapriyo Nath]

This is still RFC because micro SD card does not work with u-boot but it
works in Linux. I do not know how to troubleshoot the issue. Any pointers
would be really helpful.

Changes:
- Add sm6125 clock driver.
- Enable sm6125 clock driver in qcom_defconfig.
- Add sm6125 pinctrl driver.

Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
---
Biswapriyo Nath (3):
      clk/qcom: Add SM6125 clock driver
      qcom_defconfig: Enable SM6125 clock driver
      drivers: pinctrl: Add Qualcomm SM6125 TLMM driver

 configs/qcom_defconfig                |   1 +
 drivers/clk/qcom/Kconfig              |   8 ++
 drivers/clk/qcom/Makefile             |   1 +
 drivers/clk/qcom/clock-sm6125.c       | 260 ++++++++++++++++++++++++++++++++++
 drivers/pinctrl/qcom/Kconfig          |   8 ++
 drivers/pinctrl/qcom/Makefile         |   1 +
 drivers/pinctrl/qcom/pinctrl-sm6125.c | 147 +++++++++++++++++++
 7 files changed, 426 insertions(+)
---
base-commit: a8d982e1f1726254ef27bbdf362f98954ee3feb7
change-id: 20260204-sm6125-clk-pinctrl-dc673c8148e5

Best regards,
-- 
Biswapriyo Nath <nathbappai@gmail.com>

[PATCH RFC 1/3] clk/qcom: Add SM6125 clock driver

[Biswapriyo Nath]

Add clock driver for the GCC block found in the SM6125 SoC.

Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
---
 drivers/clk/qcom/Kconfig        |   8 ++
 drivers/clk/qcom/Makefile       |   1 +
 drivers/clk/qcom/clock-sm6125.c | 260 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 269 insertions(+)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 8504ed5d6..eb0851ef1 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -103,6 +103,14 @@ config CLK_QCOM_SM6115
 	  on the Snapdragon SM6115 SoC. This driver supports the clocks
 	  and resets exposed by the GCC hardware block.
 
+config CLK_QCOM_SM6125
+	bool "Qualcomm SM6125 GCC"
+	select CLK_QCOM
+	help
+	  Say Y here to enable support for the Global Clock Controller
+	  on the Snapdragon SM6125 SoC. This driver supports the clocks
+	  and resets exposed by the GCC hardware block.
+
 config CLK_QCOM_SM6350
 	bool "Qualcomm SM6350 GCC"
 	select CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 82a5b1661..2a934688d 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_CLK_QCOM_QCS615) += clock-qcs615.o
 obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o
 obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o
 obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o
+obj-$(CONFIG_CLK_QCOM_SM6125) += clock-sm6125.o
 obj-$(CONFIG_CLK_QCOM_SM6350) += clock-sm6350.o
 obj-$(CONFIG_CLK_QCOM_SM7150) += clock-sm7150.o
 obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o
diff --git a/drivers/clk/qcom/clock-sm6125.c b/drivers/clk/qcom/clock-sm6125.c
new file mode 100644
index 000000000..1fd72d55e
--- /dev/null
+++ b/drivers/clk/qcom/clock-sm6125.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Clock drivers for Qualcomm sm6125
+ *
+ * (C) Copyright 2026 Biswapriyo Nath <nathbappai@gmail.com>
+ *
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/bug.h>
+#include <dt-bindings/clock/qcom,gcc-sm6125.h>
+
+#include "clock-qcom.h"
+
+#define GCC_BASE 0x01400000
+
+#define QUPV3_WRAP0_S4_CMD_RCGR 0x1f608
+#define SDCC1_APPS_CLK_CMD_RCGR 0x38028
+#define SDCC2_APPS_CLK_CMD_RCGR 0x1e00c
+
+#define GCC_GPLL0_MODE 0x0
+#define GCC_GPLL3_MODE 0x3000
+#define GCC_GPLL4_MODE 0x4000
+#define GCC_GPLL5_MODE 0x5000
+#define GCC_GPLL6_MODE 0x6000
+#define GCC_GPLL7_MODE 0x7000
+#define GCC_GPLL8_MODE 0x8000
+#define GCC_GPLL9_MODE 0x9000
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
+	F(7372800, CFG_CLK_SRC_GPLL0_AUX2, 1, 384, 15625),
+	F(14745600, CFG_CLK_SRC_GPLL0_AUX2, 1, 768, 15625),
+	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+	F(29491200, CFG_CLK_SRC_GPLL0_AUX2, 1, 1536, 15625),
+	F(32000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 75),
+	F(48000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 25),
+	F(64000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 16, 75),
+	F(75000000, CFG_CLK_SRC_GPLL0_AUX2, 4, 0, 0),
+	F(80000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 15),
+	F(96000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 25),
+	F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+	F(102400000, CFG_CLK_SRC_GPLL0_AUX2, 1, 128, 375),
+	F(112000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 28, 75),
+	F(117964800, CFG_CLK_SRC_GPLL0_AUX2, 1, 6144, 15625),
+	F(120000000, CFG_CLK_SRC_GPLL0_AUX2, 2.5, 0, 0),
+	F(128000000, CFG_CLK_SRC_GPLL6, 3, 0, 0),
+	{}
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
+	F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
+	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+	F(25000000, CFG_CLK_SRC_GPLL0_AUX2, 12, 0, 0),
+	F(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0),
+	F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0),
+	{}
+};
+
+static const struct pll_vote_clk gpll0_clk = {
+	.status = 0,
+	.status_bit = BIT(31),
+	.ena_vote = 0x79000,
+	.vote_bit = BIT(0),
+};
+
+static const struct gate_clk sm6125_clks[] = {
+	GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1a084, BIT(0)),
+	GATE_CLK(GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x7900c, BIT(9)),
+	GATE_CLK(GCC_QUPV3_WRAP0_CORE_CLK, 0x7900c, BIT(8)),
+	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x7900c, BIT(10)),
+	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x7900c, BIT(11)),
+	GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x7900c, BIT(12)),
+	GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x7900c, BIT(13)),
+	GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x7900c, BIT(14)),
+	GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x7900c, BIT(15)),
+	GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x7900c, BIT(6)),
+	GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x7900c, BIT(7)),
+	GATE_CLK(GCC_SDCC1_AHB_CLK, 0x38008, BIT(0)),
+	GATE_CLK(GCC_SDCC1_APPS_CLK, 0x38004, BIT(0)),
+	GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x3800c, BIT(0)),
+	GATE_CLK(GCC_SDCC2_AHB_CLK, 0x1e008, BIT(0)),
+	GATE_CLK(GCC_SDCC2_APPS_CLK, 0x1e004, BIT(0)),
+	GATE_CLK(GCC_SYS_NOC_CPUSS_AHB_CLK, 0x79004, BIT(0)),
+	GATE_CLK(GCC_SYS_NOC_UFS_PHY_AXI_CLK, 0x45098, BIT(0)),
+	GATE_CLK(GCC_SYS_NOC_USB3_PRIM_AXI_CLK, 0x1a080, BIT(0)),
+	GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x45014, BIT(0)),
+	GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x45010, BIT(0)),
+	GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x45044, BIT(0)),
+	GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x45078, BIT(0)),
+	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x4501c, BIT(0)),
+	GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x45018, BIT(0)),
+	GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x45040, BIT(0)),
+	GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1a010, BIT(0)),
+	GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1a018, BIT(0)),
+	GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1a014, BIT(0)),
+	GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x80278, BIT(0)),
+	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1a054, BIT(0)),
+	GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1a058, BIT(0)),
+	GATE_CLK(GCC_AHB2PHY_USB_CLK, 0x1d008, BIT(0)),
+	GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0)),
+};
+
+static ulong sm6125_set_rate(struct clk *clk, ulong rate)
+{
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct freq_tbl *freq;
+
+	debug("%s: clk %s rate %lu\n", __func__, sm6125_clks[clk->id].name,
+	      rate);
+
+	switch (clk->id) {
+	case GCC_QUPV3_WRAP0_S4_CLK:
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S4_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src,
+				     16);
+		return 0;
+	case GCC_SDCC2_APPS_CLK:
+		clk_enable_gpll0(priv->base, &gpll0_clk);
+		freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
+		WARN(freq->src != CFG_CLK_SRC_GPLL0,
+		     "SDCC2_APPS_CLK_SRC not set to GPLL0, requested rate %lu\n",
+		     rate);
+		clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src,
+				     8);
+		return freq->freq;
+	case GCC_SDCC1_APPS_CLK:
+		/* The firmware turns this on for us and always sets it to this rate */
+		return 384000000;
+	default:
+		return rate;
+	}
+}
+
+static int sm6125_enable(struct clk *clk)
+{
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+	if (priv->data->num_clks < clk->id) {
+		debug("%s: unknown clk id %lu\n", __func__, clk->id);
+		return 0;
+	}
+
+	debug("%s: clk %s\n", __func__, sm6125_clks[clk->id].name);
+
+	switch (clk->id) {
+	case GCC_USB30_PRIM_MASTER_CLK:
+		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
+		qcom_gate_clk_en(priv, GCC_USB3_PRIM_CLKREF_CLK);
+		break;
+	}
+
+	return qcom_gate_clk_en(priv, clk->id);
+}
+
+static const struct qcom_reset_map sm6125_gcc_resets[] = {
+	[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
+	[GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
+	[GCC_UFS_PHY_BCR] = { 0x45000 },
+	[GCC_USB30_PRIM_BCR] = { 0x1a000 },
+	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
+	[GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
+	[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
+	[GCC_CAMSS_MICRO_BCR] = { 0x560ac },
+};
+
+static const struct qcom_power_map sm6125_gdscs[] = {
+	[USB30_PRIM_GDSC] = { 0x1a004 },
+	[UFS_PHY_GDSC] = { 0x45004 },
+	[CAMSS_VFE0_GDSC] = { 0x54004 },
+	[CAMSS_VFE1_GDSC] = { 0x5403c },
+	[CAMSS_TOP_GDSC] = { 0x5607c },
+	[CAM_CPP_GDSC] = { 0x560bc },
+	[HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = { 0x7d060 },
+	[HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = { 0x80074 },
+	[HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = { 0x80084 },
+	[HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = { 0x80094 },
+};
+
+static const phys_addr_t sm6125_gpll_addrs[] = {
+	GCC_BASE + GCC_GPLL0_MODE, GCC_BASE + GCC_GPLL3_MODE,
+	GCC_BASE + GCC_GPLL4_MODE, GCC_BASE + GCC_GPLL5_MODE,
+	GCC_BASE + GCC_GPLL6_MODE, GCC_BASE + GCC_GPLL7_MODE,
+	GCC_BASE + GCC_GPLL8_MODE, GCC_BASE + GCC_GPLL9_MODE,
+};
+
+static const phys_addr_t sm6125_rcg_addrs[] = {
+	0x0141a01c, // GCC_USB30_PRIM_MASTER_CMD_RCGR
+	0x0141a034, // GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR
+	0x0141a060, // GCC_USB3_PRIM_PHY_AUX_CMD_RCGR
+	0x01438028, // GCC_SDCC1_APPS_CMD_RCGR
+	0x0141e00c, // GCC_SDCC2_APPS_CMD_RCGR
+	0x0141f148, // GCC_QUPV3_WRAP0_S0_CMD_RCGR
+	0x0141f278, // GCC_QUPV3_WRAP0_S1_CMD_RCGR
+	0x0141f3a8, // GCC_QUPV3_WRAP0_S2_CMD_RCGR
+	0x0141f4d8, // GCC_QUPV3_WRAP0_S3_CMD_RCGR
+	0x0141f608, // GCC_QUPV3_WRAP0_S4_CMD_RCGR
+	0x0141f738, // GCC_QUPV3_WRAP0_S5_CMD_RCGR
+	0x01445020, // GCC_UFS_PHY_AXI_CMD_RCGR
+	0x01445048, // GCC_UFS_PHY_ICE_CORE_CMD_RCGR
+	0x01445060, // GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR
+	0x0144507c, // GCC_UFS_PHY_PHY_AUX_CMD_RCGR
+};
+
+static const char *const sm6125_rcg_names[] = {
+	"GCC_USB30_PRIM_MASTER_CMD_RCGR",
+	"GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR",
+	"GCC_USB3_PRIM_PHY_AUX_CMD_RCGR",
+	"GCC_SDCC1_APPS_CMD_RCGR",
+	"GCC_SDCC2_APPS_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S0_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S1_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S2_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S3_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S4_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S5_CMD_RCGR",
+	"GCC_UFS_PHY_AXI_CMD_RCGR",
+	"GCC_UFS_PHY_ICE_CORE_CMD_RCGR",
+	"GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR",
+	"GCC_UFS_PHY_PHY_AUX_CMD_RCGR",
+};
+
+static struct msm_clk_data sm6125_gcc_data = {
+	.resets = sm6125_gcc_resets,
+	.num_resets = ARRAY_SIZE(sm6125_gcc_resets),
+	.clks = sm6125_clks,
+	.num_clks = ARRAY_SIZE(sm6125_clks),
+	.power_domains = sm6125_gdscs,
+	.num_power_domains = ARRAY_SIZE(sm6125_gdscs),
+
+	.enable = sm6125_enable,
+	.set_rate = sm6125_set_rate,
+
+	.dbg_pll_addrs = sm6125_gpll_addrs,
+	.num_plls = ARRAY_SIZE(sm6125_gpll_addrs),
+	.dbg_rcg_addrs = sm6125_rcg_addrs,
+	.num_rcgs = ARRAY_SIZE(sm6125_rcg_addrs),
+	.dbg_rcg_names = sm6125_rcg_names,
+};
+
+static const struct udevice_id gcc_sm6125_of_match[] = {
+	{
+		.compatible = "qcom,gcc-sm6125",
+		.data = (ulong)&sm6125_gcc_data,
+	},
+	{}
+};
+
+U_BOOT_DRIVER(gcc_sm6125) = {
+	.name = "gcc_sm6125",
+	.id = UCLASS_NOP,
+	.of_match = gcc_sm6125_of_match,
+	.bind = qcom_cc_bind,
+	.flags = DM_FLAG_PRE_RELOC,
+};

-- 
2.53.0

[PATCH RFC 2/3] qcom_defconfig: Enable SM6125 clock driver

[Biswapriyo Nath]

Enable the driver so that SM6125 devices can boot with qcom_defconfig.

Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
---
 configs/qcom_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index fe5880de1..fc21aa5fd 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -63,6 +63,7 @@ CONFIG_CLK_QCOM_QCS8300=y
 CONFIG_CLK_QCOM_SA8775P=y
 CONFIG_CLK_QCOM_SDM845=y
 CONFIG_CLK_QCOM_SM6115=y
+CONFIG_CLK_QCOM_SM6125=y
 CONFIG_CLK_QCOM_SM6350=y
 CONFIG_CLK_QCOM_SM7150=y
 CONFIG_CLK_QCOM_SM8150=y

-- 
2.53.0

[PATCH RFC 3/3] drivers: pinctrl: Add Qualcomm SM6125 TLMM driver

[Biswapriyo Nath]

Add support for TLMM pin controller block (Top Level Mode Multiplexer)
on SM6125 SoC, with support for special pins.

Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
---
 drivers/pinctrl/qcom/Kconfig          |   8 ++
 drivers/pinctrl/qcom/Makefile         |   1 +
 drivers/pinctrl/qcom/pinctrl-sm6125.c | 147 ++++++++++++++++++++++++++++++++++
 3 files changed, 156 insertions(+)

diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 580308621..d1c762891 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -125,6 +125,14 @@ config PINCTRL_QCOM_SM6115
 	  Say Y here to enable support for pinctrl on the Snapdragon SM6115 SoC,
 	  as well as the associated GPIO driver.
 
+config PINCTRL_QCOM_SM6125
+	bool "Qualcomm SM6125 Pinctrl"
+	default y if PINCTRL_QCOM_GENERIC
+	select PINCTRL_QCOM
+	help
+	  Say Y here to enable support for pinctrl on the Snapdragon SM6125 SoC,
+	  as well as the associated GPIO driver.
+
 config PINCTRL_QCOM_SM6350
 	bool "Qualcomm SM6350 Pinctrl"
 	default y if PINCTRL_QCOM_GENERIC
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index b5a111605..1844f37ed 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SDM660) += pinctrl-sdm660.o
 obj-$(CONFIG_PINCTRL_QCOM_SDM670) += pinctrl-sdm670.o
 obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
 obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o
+obj-$(CONFIG_PINCTRL_QCOM_SM6125) += pinctrl-sm6125.o
 obj-$(CONFIG_PINCTRL_QCOM_SM6350) += pinctrl-sm6350.o
 obj-$(CONFIG_PINCTRL_QCOM_SM7150) += pinctrl-sm7150.o
 obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sm6125.c b/drivers/pinctrl/qcom/pinctrl-sm6125.c
new file mode 100644
index 000000000..82f8972ff
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sm6125.c
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Pinctrl driver for Qualcomm SM6125
+ *
+ * (C) Copyright 2026 Biswapriyo Nath <nathbappai@gmail.com>
+ *
+ * Based on Linux Kernel driver
+ */
+
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define TLMM_BASE 0x00500000
+#define WEST (0x00500000 - TLMM_BASE) /* 0x0 */
+#define SOUTH (0x00900000 - TLMM_BASE) /* 0x400000 */
+#define EAST (0x00d00000 - TLMM_BASE) /* 0x800000 */
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	{ "qup04", 1 },
+	{ "gpio", 0 },
+};
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+	{                                          \
+		.name = pg_name,                   \
+		.ctl_reg = ctl,                    \
+		.io_reg = 0,                       \
+		.pull_bit = pull,                  \
+		.drv_bit = drv,                    \
+		.oe_bit = -1,                      \
+		.in_bit = -1,                      \
+		.out_bit = -1,                     \
+	}
+
+#define UFS_RESET(pg_name, offset)      \
+	{                               \
+		.name = pg_name,        \
+		.ctl_reg = offset,      \
+		.io_reg = offset + 0x4, \
+		.pull_bit = 3,          \
+		.drv_bit = 0,           \
+		.oe_bit = -1,           \
+		.in_bit = -1,           \
+		.out_bit = 0,           \
+	}
+
+static const struct msm_special_pin_data msm_special_pins_data[] = {
+	[0] = UFS_RESET("ufs_reset", 0x190000),
+	[1] = SDC_QDSD_PINGROUP("sdc1_rclk", WEST + 0x18d000, 15, 0),
+	[2] = SDC_QDSD_PINGROUP("sdc1_clk", WEST + 0x18d000, 13, 6),
+	[3] = SDC_QDSD_PINGROUP("sdc1_cmd", WEST + 0x18d000, 11, 3),
+	[4] = SDC_QDSD_PINGROUP("sdc1_data", WEST + 0x18d000, 9, 0),
+	[5] = SDC_QDSD_PINGROUP("sdc2_clk", SOUTH + 0x58b000, 14, 6),
+	[6] = SDC_QDSD_PINGROUP("sdc2_cmd", SOUTH + 0x58b000, 11, 3),
+	[7] = SDC_QDSD_PINGROUP("sdc2_data", SOUTH + 0x58b000, 9, 0),
+};
+
+static const unsigned int sm6125_pin_offsets[] = {
+	[0] = WEST,    [1] = WEST,    [2] = WEST,    [3] = WEST,
+	[4] = WEST,    [5] = WEST,    [6] = WEST,    [7] = WEST,
+	[8] = WEST,    [9] = WEST,    [10] = EAST,   [11] = EAST,
+	[12] = EAST,   [13] = EAST,   [14] = WEST,   [15] = WEST,
+	[16] = WEST,   [17] = WEST,   [18] = EAST,   [19] = EAST,
+	[20] = EAST,   [21] = EAST,   [22] = WEST,   [23] = WEST,
+	[24] = WEST,   [25] = WEST,   [26] = WEST,   [27] = WEST,
+	[28] = WEST,   [29] = WEST,   [30] = WEST,   [31] = WEST,
+	[32] = WEST,   [33] = WEST,   [34] = SOUTH,  [35] = SOUTH,
+	[36] = SOUTH,  [37] = SOUTH,  [38] = EAST,   [39] = EAST,
+	[40] = EAST,   [41] = EAST,   [42] = EAST,   [43] = EAST,
+	[44] = SOUTH,  [45] = SOUTH,  [46] = SOUTH,  [47] = SOUTH,
+	[48] = SOUTH,  [49] = SOUTH,  [50] = SOUTH,  [51] = SOUTH,
+	[52] = SOUTH,  [53] = SOUTH,  [54] = SOUTH,  [55] = SOUTH,
+	[56] = SOUTH,  [57] = SOUTH,  [58] = SOUTH,  [59] = SOUTH,
+	[60] = SOUTH,  [61] = SOUTH,  [62] = SOUTH,  [63] = SOUTH,
+	[64] = SOUTH,  [65] = SOUTH,  [66] = SOUTH,  [67] = SOUTH,
+	[68] = SOUTH,  [69] = SOUTH,  [70] = SOUTH,  [71] = SOUTH,
+	[72] = SOUTH,  [73] = SOUTH,  [74] = SOUTH,  [75] = SOUTH,
+	[76] = SOUTH,  [77] = SOUTH,  [78] = SOUTH,  [79] = SOUTH,
+	[80] = SOUTH,  [81] = SOUTH,  [82] = SOUTH,  [83] = SOUTH,
+	[84] = SOUTH,  [85] = SOUTH,  [86] = SOUTH,  [87] = WEST,
+	[88] = WEST,   [89] = WEST,   [90] = WEST,   [91] = WEST,
+	[92] = WEST,   [93] = WEST,   [94] = SOUTH,  [95] = SOUTH,
+	[96] = SOUTH,  [97] = SOUTH,  [98] = SOUTH,  [99] = SOUTH,
+	[100] = SOUTH, [101] = SOUTH, [102] = SOUTH, [103] = SOUTH,
+	[104] = EAST,  [105] = EAST,  [106] = EAST,  [107] = EAST,
+	[108] = EAST,  [109] = EAST,  [110] = EAST,  [111] = EAST,
+	[112] = EAST,  [113] = EAST,  [114] = EAST,  [115] = EAST,
+	[116] = EAST,  [117] = SOUTH, [118] = SOUTH, [119] = SOUTH,
+	[120] = SOUTH, [121] = EAST,  [122] = EAST,  [123] = EAST,
+	[124] = EAST,  [125] = EAST,  [126] = EAST,  [127] = EAST,
+	[128] = EAST,  [129] = SOUTH, [130] = SOUTH, [131] = SOUTH,
+	[132] = SOUTH,
+};
+
+static const char *sm6125_get_function_name(struct udevice *dev,
+					    unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *sm6125_get_pin_name(struct udevice *dev,
+				       unsigned int selector)
+{
+	if (selector >= 133 && selector <= 140)
+		snprintf(pin_name, MAX_PIN_NAME_LEN,
+			 msm_special_pins_data[selector - 133].name);
+	else
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+
+	return pin_name;
+}
+
+static int sm6125_get_function_mux(__maybe_unused unsigned int pin,
+				   unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].val;
+}
+
+static struct msm_pinctrl_data sm6125_data = {
+	.pin_data = {
+		.pin_offsets = sm6125_pin_offsets,
+		.pin_count = 141,
+		.special_pins_start = 133,
+		.special_pins_data = msm_special_pins_data,
+	},
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = sm6125_get_function_name,
+	.get_function_mux = sm6125_get_function_mux,
+	.get_pin_name = sm6125_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+	{ .compatible = "qcom,sm6125-tlmm", .data = (ulong)&sm6125_data },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(pinctrl_sm6125) = {
+	.name = "pinctrl_sm6125",
+	.id = UCLASS_NOP,
+	.of_match = msm_pinctrl_ids,
+	.ops = &msm_pinctrl_ops,
+	.bind = msm_pinctrl_bind,
+};

-- 
2.53.0

Re: [PATCH RFC 0/3] Add clk and pinctrl drivers for SM6125 SoC

[Biswapriyo Nath]

On Wed, 04 Feb 2026 16:10:51 +0000 Biswapriyo Nath <nathbappai@gmail.com> wrote:

> This is still RFC because micro SD card does not work with u-boot but it
> works in Linux. I do not know how to troubleshoot the issue. Any pointers
> would be really helpful.

I forgot to add the error message. Here is the output from USB serial.

=> mmc list
mmc@4744000: 0 (eMMC)
mmc@4784000: 1
=> mmc dev 1
Card did not respond to voltage select! : -110

Thanks.

Re: [PATCH RFC 1/3] clk/qcom: Add SM6125 clock driver

[Casey Connolly]

Hi Biswapriyo,

On 04/02/2026 17:10, Biswapriyo Nath wrote:
> Add clock driver for the GCC block found in the SM6125 SoC.
> 
> Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>

Super clean patch, and all the goodies for debugging too! Thanks a lot
for sending this.

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>


> ---
>  drivers/clk/qcom/Kconfig        |   8 ++
>  drivers/clk/qcom/Makefile       |   1 +
>  drivers/clk/qcom/clock-sm6125.c | 260 ++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 269 insertions(+)
> 
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 8504ed5d6..eb0851ef1 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -103,6 +103,14 @@ config CLK_QCOM_SM6115
>  	  on the Snapdragon SM6115 SoC. This driver supports the clocks
>  	  and resets exposed by the GCC hardware block.
>  
> +config CLK_QCOM_SM6125
> +	bool "Qualcomm SM6125 GCC"
> +	select CLK_QCOM
> +	help
> +	  Say Y here to enable support for the Global Clock Controller
> +	  on the Snapdragon SM6125 SoC. This driver supports the clocks
> +	  and resets exposed by the GCC hardware block.
> +
>  config CLK_QCOM_SM6350
>  	bool "Qualcomm SM6350 GCC"
>  	select CLK_QCOM
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 82a5b1661..2a934688d 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_CLK_QCOM_QCS615) += clock-qcs615.o
>  obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o
>  obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o
>  obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o
> +obj-$(CONFIG_CLK_QCOM_SM6125) += clock-sm6125.o
>  obj-$(CONFIG_CLK_QCOM_SM6350) += clock-sm6350.o
>  obj-$(CONFIG_CLK_QCOM_SM7150) += clock-sm7150.o
>  obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o
> diff --git a/drivers/clk/qcom/clock-sm6125.c b/drivers/clk/qcom/clock-sm6125.c
> new file mode 100644
> index 000000000..1fd72d55e
> --- /dev/null
> +++ b/drivers/clk/qcom/clock-sm6125.c
> @@ -0,0 +1,260 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Clock drivers for Qualcomm sm6125
> + *
> + * (C) Copyright 2026 Biswapriyo Nath <nathbappai@gmail.com>
> + *
> + */
> +
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <linux/delay.h>
> +#include <asm/io.h>
> +#include <linux/bitops.h>
> +#include <linux/bug.h>
> +#include <dt-bindings/clock/qcom,gcc-sm6125.h>
> +
> +#include "clock-qcom.h"
> +
> +#define GCC_BASE 0x01400000
> +
> +#define QUPV3_WRAP0_S4_CMD_RCGR 0x1f608
> +#define SDCC1_APPS_CLK_CMD_RCGR 0x38028
> +#define SDCC2_APPS_CLK_CMD_RCGR 0x1e00c
> +
> +#define GCC_GPLL0_MODE 0x0
> +#define GCC_GPLL3_MODE 0x3000
> +#define GCC_GPLL4_MODE 0x4000
> +#define GCC_GPLL5_MODE 0x5000
> +#define GCC_GPLL6_MODE 0x6000
> +#define GCC_GPLL7_MODE 0x7000
> +#define GCC_GPLL8_MODE 0x8000
> +#define GCC_GPLL9_MODE 0x9000
> +
> +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
> +	F(7372800, CFG_CLK_SRC_GPLL0_AUX2, 1, 384, 15625),
> +	F(14745600, CFG_CLK_SRC_GPLL0_AUX2, 1, 768, 15625),
> +	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
> +	F(29491200, CFG_CLK_SRC_GPLL0_AUX2, 1, 1536, 15625),
> +	F(32000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 75),
> +	F(48000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 25),
> +	F(64000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 16, 75),
> +	F(75000000, CFG_CLK_SRC_GPLL0_AUX2, 4, 0, 0),
> +	F(80000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 15),
> +	F(96000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 25),
> +	F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
> +	F(102400000, CFG_CLK_SRC_GPLL0_AUX2, 1, 128, 375),
> +	F(112000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 28, 75),
> +	F(117964800, CFG_CLK_SRC_GPLL0_AUX2, 1, 6144, 15625),
> +	F(120000000, CFG_CLK_SRC_GPLL0_AUX2, 2.5, 0, 0),
> +	F(128000000, CFG_CLK_SRC_GPLL6, 3, 0, 0),
> +	{}
> +};
> +
> +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
> +	F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
> +	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
> +	F(25000000, CFG_CLK_SRC_GPLL0_AUX2, 12, 0, 0),
> +	F(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0),
> +	F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0),
> +	{}
> +};
> +
> +static const struct pll_vote_clk gpll0_clk = {
> +	.status = 0,
> +	.status_bit = BIT(31),
> +	.ena_vote = 0x79000,
> +	.vote_bit = BIT(0),
> +};
> +
> +static const struct gate_clk sm6125_clks[] = {
> +	GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1a084, BIT(0)),
> +	GATE_CLK(GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x7900c, BIT(9)),
> +	GATE_CLK(GCC_QUPV3_WRAP0_CORE_CLK, 0x7900c, BIT(8)),
> +	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x7900c, BIT(10)),
> +	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x7900c, BIT(11)),
> +	GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x7900c, BIT(12)),
> +	GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x7900c, BIT(13)),
> +	GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x7900c, BIT(14)),
> +	GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x7900c, BIT(15)),
> +	GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x7900c, BIT(6)),
> +	GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x7900c, BIT(7)),
> +	GATE_CLK(GCC_SDCC1_AHB_CLK, 0x38008, BIT(0)),
> +	GATE_CLK(GCC_SDCC1_APPS_CLK, 0x38004, BIT(0)),
> +	GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x3800c, BIT(0)),
> +	GATE_CLK(GCC_SDCC2_AHB_CLK, 0x1e008, BIT(0)),
> +	GATE_CLK(GCC_SDCC2_APPS_CLK, 0x1e004, BIT(0)),
> +	GATE_CLK(GCC_SYS_NOC_CPUSS_AHB_CLK, 0x79004, BIT(0)),
> +	GATE_CLK(GCC_SYS_NOC_UFS_PHY_AXI_CLK, 0x45098, BIT(0)),
> +	GATE_CLK(GCC_SYS_NOC_USB3_PRIM_AXI_CLK, 0x1a080, BIT(0)),
> +	GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x45014, BIT(0)),
> +	GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x45010, BIT(0)),
> +	GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x45044, BIT(0)),
> +	GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x45078, BIT(0)),
> +	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x4501c, BIT(0)),
> +	GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x45018, BIT(0)),
> +	GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x45040, BIT(0)),
> +	GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1a010, BIT(0)),
> +	GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1a018, BIT(0)),
> +	GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1a014, BIT(0)),
> +	GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x80278, BIT(0)),
> +	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1a054, BIT(0)),
> +	GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1a058, BIT(0)),
> +	GATE_CLK(GCC_AHB2PHY_USB_CLK, 0x1d008, BIT(0)),
> +	GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0)),
> +};
> +
> +static ulong sm6125_set_rate(struct clk *clk, ulong rate)
> +{
> +	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> +	const struct freq_tbl *freq;
> +
> +	debug("%s: clk %s rate %lu\n", __func__, sm6125_clks[clk->id].name,
> +	      rate);
> +
> +	switch (clk->id) {
> +	case GCC_QUPV3_WRAP0_S4_CLK:
> +		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
> +		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S4_CMD_RCGR,
> +				     freq->pre_div, freq->m, freq->n, freq->src,
> +				     16);
> +		return 0;
> +	case GCC_SDCC2_APPS_CLK:
> +		clk_enable_gpll0(priv->base, &gpll0_clk);
> +		freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
> +		WARN(freq->src != CFG_CLK_SRC_GPLL0,
> +		     "SDCC2_APPS_CLK_SRC not set to GPLL0, requested rate %lu\n",
> +		     rate);
> +		clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR,
> +				     freq->pre_div, freq->m, freq->n, freq->src,
> +				     8);
> +		return freq->freq;
> +	case GCC_SDCC1_APPS_CLK:
> +		/* The firmware turns this on for us and always sets it to this rate */
> +		return 384000000;
> +	default:
> +		return rate;
> +	}
> +}
> +
> +static int sm6125_enable(struct clk *clk)
> +{
> +	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> +
> +	if (priv->data->num_clks < clk->id) {
> +		debug("%s: unknown clk id %lu\n", __func__, clk->id);
> +		return 0;
> +	}
> +
> +	debug("%s: clk %s\n", __func__, sm6125_clks[clk->id].name);
> +
> +	switch (clk->id) {
> +	case GCC_USB30_PRIM_MASTER_CLK:
> +		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
> +		qcom_gate_clk_en(priv, GCC_USB3_PRIM_CLKREF_CLK);
> +		break;
> +	}
> +
> +	return qcom_gate_clk_en(priv, clk->id);
> +}
> +
> +static const struct qcom_reset_map sm6125_gcc_resets[] = {
> +	[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
> +	[GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
> +	[GCC_UFS_PHY_BCR] = { 0x45000 },
> +	[GCC_USB30_PRIM_BCR] = { 0x1a000 },
> +	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
> +	[GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
> +	[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
> +	[GCC_CAMSS_MICRO_BCR] = { 0x560ac },
> +};
> +
> +static const struct qcom_power_map sm6125_gdscs[] = {
> +	[USB30_PRIM_GDSC] = { 0x1a004 },
> +	[UFS_PHY_GDSC] = { 0x45004 },
> +	[CAMSS_VFE0_GDSC] = { 0x54004 },
> +	[CAMSS_VFE1_GDSC] = { 0x5403c },
> +	[CAMSS_TOP_GDSC] = { 0x5607c },
> +	[CAM_CPP_GDSC] = { 0x560bc },
> +	[HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = { 0x7d060 },
> +	[HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = { 0x80074 },
> +	[HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = { 0x80084 },
> +	[HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = { 0x80094 },
> +};
> +
> +static const phys_addr_t sm6125_gpll_addrs[] = {
> +	GCC_BASE + GCC_GPLL0_MODE, GCC_BASE + GCC_GPLL3_MODE,
> +	GCC_BASE + GCC_GPLL4_MODE, GCC_BASE + GCC_GPLL5_MODE,
> +	GCC_BASE + GCC_GPLL6_MODE, GCC_BASE + GCC_GPLL7_MODE,
> +	GCC_BASE + GCC_GPLL8_MODE, GCC_BASE + GCC_GPLL9_MODE,
> +};
> +
> +static const phys_addr_t sm6125_rcg_addrs[] = {
> +	0x0141a01c, // GCC_USB30_PRIM_MASTER_CMD_RCGR
> +	0x0141a034, // GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR
> +	0x0141a060, // GCC_USB3_PRIM_PHY_AUX_CMD_RCGR
> +	0x01438028, // GCC_SDCC1_APPS_CMD_RCGR
> +	0x0141e00c, // GCC_SDCC2_APPS_CMD_RCGR
> +	0x0141f148, // GCC_QUPV3_WRAP0_S0_CMD_RCGR
> +	0x0141f278, // GCC_QUPV3_WRAP0_S1_CMD_RCGR
> +	0x0141f3a8, // GCC_QUPV3_WRAP0_S2_CMD_RCGR
> +	0x0141f4d8, // GCC_QUPV3_WRAP0_S3_CMD_RCGR
> +	0x0141f608, // GCC_QUPV3_WRAP0_S4_CMD_RCGR
> +	0x0141f738, // GCC_QUPV3_WRAP0_S5_CMD_RCGR
> +	0x01445020, // GCC_UFS_PHY_AXI_CMD_RCGR
> +	0x01445048, // GCC_UFS_PHY_ICE_CORE_CMD_RCGR
> +	0x01445060, // GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR
> +	0x0144507c, // GCC_UFS_PHY_PHY_AUX_CMD_RCGR
> +};
> +
> +static const char *const sm6125_rcg_names[] = {
> +	"GCC_USB30_PRIM_MASTER_CMD_RCGR",
> +	"GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR",
> +	"GCC_USB3_PRIM_PHY_AUX_CMD_RCGR",
> +	"GCC_SDCC1_APPS_CMD_RCGR",
> +	"GCC_SDCC2_APPS_CMD_RCGR",
> +	"GCC_QUPV3_WRAP0_S0_CMD_RCGR",
> +	"GCC_QUPV3_WRAP0_S1_CMD_RCGR",
> +	"GCC_QUPV3_WRAP0_S2_CMD_RCGR",
> +	"GCC_QUPV3_WRAP0_S3_CMD_RCGR",
> +	"GCC_QUPV3_WRAP0_S4_CMD_RCGR",
> +	"GCC_QUPV3_WRAP0_S5_CMD_RCGR",
> +	"GCC_UFS_PHY_AXI_CMD_RCGR",
> +	"GCC_UFS_PHY_ICE_CORE_CMD_RCGR",
> +	"GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR",
> +	"GCC_UFS_PHY_PHY_AUX_CMD_RCGR",
> +};
> +
> +static struct msm_clk_data sm6125_gcc_data = {
> +	.resets = sm6125_gcc_resets,
> +	.num_resets = ARRAY_SIZE(sm6125_gcc_resets),
> +	.clks = sm6125_clks,
> +	.num_clks = ARRAY_SIZE(sm6125_clks),
> +	.power_domains = sm6125_gdscs,
> +	.num_power_domains = ARRAY_SIZE(sm6125_gdscs),
> +
> +	.enable = sm6125_enable,
> +	.set_rate = sm6125_set_rate,
> +
> +	.dbg_pll_addrs = sm6125_gpll_addrs,
> +	.num_plls = ARRAY_SIZE(sm6125_gpll_addrs),
> +	.dbg_rcg_addrs = sm6125_rcg_addrs,
> +	.num_rcgs = ARRAY_SIZE(sm6125_rcg_addrs),
> +	.dbg_rcg_names = sm6125_rcg_names,
> +};
> +
> +static const struct udevice_id gcc_sm6125_of_match[] = {
> +	{
> +		.compatible = "qcom,gcc-sm6125",
> +		.data = (ulong)&sm6125_gcc_data,
> +	},
> +	{}
> +};
> +
> +U_BOOT_DRIVER(gcc_sm6125) = {
> +	.name = "gcc_sm6125",
> +	.id = UCLASS_NOP,
> +	.of_match = gcc_sm6125_of_match,
> +	.bind = qcom_cc_bind,
> +	.flags = DM_FLAG_PRE_RELOC,
> +};
> 

-- 
// Casey (she/her)

Re: [PATCH RFC 2/3] qcom_defconfig: Enable SM6125 clock driver

[Casey Connolly]

On 04/02/2026 17:10, Biswapriyo Nath wrote:
> Enable the driver so that SM6125 devices can boot with qcom_defconfig.
> 
> Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>

> ---
>  configs/qcom_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
> index fe5880de1..fc21aa5fd 100644
> --- a/configs/qcom_defconfig
> +++ b/configs/qcom_defconfig
> @@ -63,6 +63,7 @@ CONFIG_CLK_QCOM_QCS8300=y
>  CONFIG_CLK_QCOM_SA8775P=y
>  CONFIG_CLK_QCOM_SDM845=y
>  CONFIG_CLK_QCOM_SM6115=y
> +CONFIG_CLK_QCOM_SM6125=y
>  CONFIG_CLK_QCOM_SM6350=y
>  CONFIG_CLK_QCOM_SM7150=y
>  CONFIG_CLK_QCOM_SM8150=y
> 

-- 
// Casey (she/her)

Re: [PATCH RFC 3/3] drivers: pinctrl: Add Qualcomm SM6125 TLMM driver

[Casey Connolly]

On 04/02/2026 17:10, Biswapriyo Nath wrote:
> Add support for TLMM pin controller block (Top Level Mode Multiplexer)
> on SM6125 SoC, with support for special pins.
> 
> Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>

> ---
>  drivers/pinctrl/qcom/Kconfig          |   8 ++
>  drivers/pinctrl/qcom/Makefile         |   1 +
>  drivers/pinctrl/qcom/pinctrl-sm6125.c | 147 ++++++++++++++++++++++++++++++++++
>  3 files changed, 156 insertions(+)
> 
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 580308621..d1c762891 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -125,6 +125,14 @@ config PINCTRL_QCOM_SM6115
>  	  Say Y here to enable support for pinctrl on the Snapdragon SM6115 SoC,
>  	  as well as the associated GPIO driver.
>  
> +config PINCTRL_QCOM_SM6125
> +	bool "Qualcomm SM6125 Pinctrl"
> +	default y if PINCTRL_QCOM_GENERIC
> +	select PINCTRL_QCOM
> +	help
> +	  Say Y here to enable support for pinctrl on the Snapdragon SM6125 SoC,
> +	  as well as the associated GPIO driver.
> +
>  config PINCTRL_QCOM_SM6350
>  	bool "Qualcomm SM6350 Pinctrl"
>  	default y if PINCTRL_QCOM_GENERIC
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index b5a111605..1844f37ed 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SDM660) += pinctrl-sdm660.o
>  obj-$(CONFIG_PINCTRL_QCOM_SDM670) += pinctrl-sdm670.o
>  obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
>  obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o
> +obj-$(CONFIG_PINCTRL_QCOM_SM6125) += pinctrl-sm6125.o
>  obj-$(CONFIG_PINCTRL_QCOM_SM6350) += pinctrl-sm6350.o
>  obj-$(CONFIG_PINCTRL_QCOM_SM7150) += pinctrl-sm7150.o
>  obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm6125.c b/drivers/pinctrl/qcom/pinctrl-sm6125.c
> new file mode 100644
> index 000000000..82f8972ff
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-sm6125.c
> @@ -0,0 +1,147 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Pinctrl driver for Qualcomm SM6125
> + *
> + * (C) Copyright 2026 Biswapriyo Nath <nathbappai@gmail.com>
> + *
> + * Based on Linux Kernel driver
> + */
> +
> +#include <dm.h>
> +
> +#include "pinctrl-qcom.h"
> +
> +#define TLMM_BASE 0x00500000
> +#define WEST (0x00500000 - TLMM_BASE) /* 0x0 */
> +#define SOUTH (0x00900000 - TLMM_BASE) /* 0x400000 */
> +#define EAST (0x00d00000 - TLMM_BASE) /* 0x800000 */
> +
> +#define MAX_PIN_NAME_LEN 32
> +static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
> +
> +static const struct pinctrl_function msm_pinctrl_functions[] = {
> +	{ "qup04", 1 },
> +	{ "gpio", 0 },
> +};
> +
> +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
> +	{                                          \
> +		.name = pg_name,                   \
> +		.ctl_reg = ctl,                    \
> +		.io_reg = 0,                       \
> +		.pull_bit = pull,                  \
> +		.drv_bit = drv,                    \
> +		.oe_bit = -1,                      \
> +		.in_bit = -1,                      \
> +		.out_bit = -1,                     \
> +	}
> +
> +#define UFS_RESET(pg_name, offset)      \
> +	{                               \
> +		.name = pg_name,        \
> +		.ctl_reg = offset,      \
> +		.io_reg = offset + 0x4, \
> +		.pull_bit = 3,          \
> +		.drv_bit = 0,           \
> +		.oe_bit = -1,           \
> +		.in_bit = -1,           \
> +		.out_bit = 0,           \
> +	}
> +
> +static const struct msm_special_pin_data msm_special_pins_data[] = {
> +	[0] = UFS_RESET("ufs_reset", 0x190000),
> +	[1] = SDC_QDSD_PINGROUP("sdc1_rclk", WEST + 0x18d000, 15, 0),
> +	[2] = SDC_QDSD_PINGROUP("sdc1_clk", WEST + 0x18d000, 13, 6),
> +	[3] = SDC_QDSD_PINGROUP("sdc1_cmd", WEST + 0x18d000, 11, 3),
> +	[4] = SDC_QDSD_PINGROUP("sdc1_data", WEST + 0x18d000, 9, 0),
> +	[5] = SDC_QDSD_PINGROUP("sdc2_clk", SOUTH + 0x58b000, 14, 6),
> +	[6] = SDC_QDSD_PINGROUP("sdc2_cmd", SOUTH + 0x58b000, 11, 3),
> +	[7] = SDC_QDSD_PINGROUP("sdc2_data", SOUTH + 0x58b000, 9, 0),
> +};
> +
> +static const unsigned int sm6125_pin_offsets[] = {
> +	[0] = WEST,    [1] = WEST,    [2] = WEST,    [3] = WEST,
> +	[4] = WEST,    [5] = WEST,    [6] = WEST,    [7] = WEST,
> +	[8] = WEST,    [9] = WEST,    [10] = EAST,   [11] = EAST,
> +	[12] = EAST,   [13] = EAST,   [14] = WEST,   [15] = WEST,
> +	[16] = WEST,   [17] = WEST,   [18] = EAST,   [19] = EAST,
> +	[20] = EAST,   [21] = EAST,   [22] = WEST,   [23] = WEST,
> +	[24] = WEST,   [25] = WEST,   [26] = WEST,   [27] = WEST,
> +	[28] = WEST,   [29] = WEST,   [30] = WEST,   [31] = WEST,
> +	[32] = WEST,   [33] = WEST,   [34] = SOUTH,  [35] = SOUTH,
> +	[36] = SOUTH,  [37] = SOUTH,  [38] = EAST,   [39] = EAST,
> +	[40] = EAST,   [41] = EAST,   [42] = EAST,   [43] = EAST,
> +	[44] = SOUTH,  [45] = SOUTH,  [46] = SOUTH,  [47] = SOUTH,
> +	[48] = SOUTH,  [49] = SOUTH,  [50] = SOUTH,  [51] = SOUTH,
> +	[52] = SOUTH,  [53] = SOUTH,  [54] = SOUTH,  [55] = SOUTH,
> +	[56] = SOUTH,  [57] = SOUTH,  [58] = SOUTH,  [59] = SOUTH,
> +	[60] = SOUTH,  [61] = SOUTH,  [62] = SOUTH,  [63] = SOUTH,
> +	[64] = SOUTH,  [65] = SOUTH,  [66] = SOUTH,  [67] = SOUTH,
> +	[68] = SOUTH,  [69] = SOUTH,  [70] = SOUTH,  [71] = SOUTH,
> +	[72] = SOUTH,  [73] = SOUTH,  [74] = SOUTH,  [75] = SOUTH,
> +	[76] = SOUTH,  [77] = SOUTH,  [78] = SOUTH,  [79] = SOUTH,
> +	[80] = SOUTH,  [81] = SOUTH,  [82] = SOUTH,  [83] = SOUTH,
> +	[84] = SOUTH,  [85] = SOUTH,  [86] = SOUTH,  [87] = WEST,
> +	[88] = WEST,   [89] = WEST,   [90] = WEST,   [91] = WEST,
> +	[92] = WEST,   [93] = WEST,   [94] = SOUTH,  [95] = SOUTH,
> +	[96] = SOUTH,  [97] = SOUTH,  [98] = SOUTH,  [99] = SOUTH,
> +	[100] = SOUTH, [101] = SOUTH, [102] = SOUTH, [103] = SOUTH,
> +	[104] = EAST,  [105] = EAST,  [106] = EAST,  [107] = EAST,
> +	[108] = EAST,  [109] = EAST,  [110] = EAST,  [111] = EAST,
> +	[112] = EAST,  [113] = EAST,  [114] = EAST,  [115] = EAST,
> +	[116] = EAST,  [117] = SOUTH, [118] = SOUTH, [119] = SOUTH,
> +	[120] = SOUTH, [121] = EAST,  [122] = EAST,  [123] = EAST,
> +	[124] = EAST,  [125] = EAST,  [126] = EAST,  [127] = EAST,
> +	[128] = EAST,  [129] = SOUTH, [130] = SOUTH, [131] = SOUTH,
> +	[132] = SOUTH,
> +};
> +
> +static const char *sm6125_get_function_name(struct udevice *dev,
> +					    unsigned int selector)
> +{
> +	return msm_pinctrl_functions[selector].name;
> +}
> +
> +static const char *sm6125_get_pin_name(struct udevice *dev,
> +				       unsigned int selector)
> +{
> +	if (selector >= 133 && selector <= 140)
> +		snprintf(pin_name, MAX_PIN_NAME_LEN,
> +			 msm_special_pins_data[selector - 133].name);
> +	else
> +		snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
> +
> +	return pin_name;
> +}
> +
> +static int sm6125_get_function_mux(__maybe_unused unsigned int pin,
> +				   unsigned int selector)
> +{
> +	return msm_pinctrl_functions[selector].val;
> +}
> +
> +static struct msm_pinctrl_data sm6125_data = {
> +	.pin_data = {
> +		.pin_offsets = sm6125_pin_offsets,
> +		.pin_count = 141,
> +		.special_pins_start = 133,
> +		.special_pins_data = msm_special_pins_data,
> +	},
> +	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
> +	.get_function_name = sm6125_get_function_name,
> +	.get_function_mux = sm6125_get_function_mux,
> +	.get_pin_name = sm6125_get_pin_name,
> +};
> +
> +static const struct udevice_id msm_pinctrl_ids[] = {
> +	{ .compatible = "qcom,sm6125-tlmm", .data = (ulong)&sm6125_data },
> +	{ /* sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(pinctrl_sm6125) = {
> +	.name = "pinctrl_sm6125",
> +	.id = UCLASS_NOP,
> +	.of_match = msm_pinctrl_ids,
> +	.ops = &msm_pinctrl_ops,
> +	.bind = msm_pinctrl_bind,
> +};
> 

-- 
// Casey (she/her)

Re: [PATCH RFC 0/3] Add clk and pinctrl drivers for SM6125 SoC

[Casey Connolly]

On 04/02/2026 17:10, Biswapriyo Nath wrote:
> This is still RFC because micro SD card does not work with u-boot but it
> works in Linux. I do not know how to troubleshoot the issue. Any pointers
> would be really helpful.

Firstly, thanks a lot for sending this series and getting this platform
running in general, and a belated congrats on your first U-Boot
contributions.

I think the sdcard issue also happens on SM6115, I don't remember if it
got resolved there or if it was root-caused. There can be issues with
different brands of sdcard, and cards that falsely advertise supporting
the wrong speeds, so I'd recommend trying cards from a few brands.

That's the best I can think of otoomh, but in any case sdcard support
not being functional yet isn't a blocker for me to pick this series up.

Kind regards,

> 
> Changes:
> - Add sm6125 clock driver.
> - Enable sm6125 clock driver in qcom_defconfig.
> - Add sm6125 pinctrl driver.
> 
> Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
> ---
> Biswapriyo Nath (3):
>       clk/qcom: Add SM6125 clock driver
>       qcom_defconfig: Enable SM6125 clock driver
>       drivers: pinctrl: Add Qualcomm SM6125 TLMM driver
> 
>  configs/qcom_defconfig                |   1 +
>  drivers/clk/qcom/Kconfig              |   8 ++
>  drivers/clk/qcom/Makefile             |   1 +
>  drivers/clk/qcom/clock-sm6125.c       | 260 ++++++++++++++++++++++++++++++++++
>  drivers/pinctrl/qcom/Kconfig          |   8 ++
>  drivers/pinctrl/qcom/Makefile         |   1 +
>  drivers/pinctrl/qcom/pinctrl-sm6125.c | 147 +++++++++++++++++++
>  7 files changed, 426 insertions(+)
> ---
> base-commit: a8d982e1f1726254ef27bbdf362f98954ee3feb7
> change-id: 20260204-sm6125-clk-pinctrl-dc673c8148e5
> 
> Best regards,

-- 
// Casey (she/her)

Re: [PATCH RFC 0/3] Add clk and pinctrl drivers for SM6125 SoC

[Sumit Garg]

Hi,

On Sat, Feb 07, 2026 at 09:28:38AM +0000, Biswapriyo Nath wrote:
> On Wed, 04 Feb 2026 16:10:51 +0000 Biswapriyo Nath <nathbappai@gmail.com> wrote:
> 
> > This is still RFC because micro SD card does not work with u-boot but it
> > works in Linux. I do not know how to troubleshoot the issue. Any pointers
> > would be really helpful.
> 
> I forgot to add the error message. Here is the output from USB serial.
> 
> => mmc list
> mmc@4744000: 0 (eMMC)
> mmc@4784000: 1
> => mmc dev 1
> Card did not respond to voltage select! : -110
> 

Can you check if recent SD/eMMC fixes merged [1] are included in your tree?

[1] https://lore.kernel.org/all/20251210155454.1561611-1-loic.poulain@oss.qualcomm.com/

-Sumit

Re: [PATCH RFC 0/3] Add clk and pinctrl drivers for SM6125 SoC

[Alexey Minnekhanov]

On 07.02.2026 12:28, Biswapriyo Nath via groups.io wrote:
> On Wed, 04 Feb 2026 16:10:51 +0000 Biswapriyo Nath <nathbappai@gmail.com> wrote:
> 
>> This is still RFC because micro SD card does not work with u-boot but it
>> works in Linux. I do not know how to troubleshoot the issue. Any pointers
>> would be really helpful.
> 
> I forgot to add the error message. Here is the output from USB serial.
> 
> => mmc list
> mmc@4744000: 0 (eMMC)
> mmc@4784000: 1
> => mmc dev 1
> Card did not respond to voltage select! : -110
> 
> Thanks.
> 

Hi!

Is card detect GPIO set correctly for board?

Maybe you can verfy card detect is working by repeating the command:

  gpio status socXX

(where XX is your cd-gpio) while inserting/removing the SD card.

--
Regards,
Alexey Minnekhanov

Re: [PATCH RFC 0/3] Add clk and pinctrl drivers for SM6125 SoC

[Biswapriyo Nath]

On Tue, 10 Feb 2026 10:56:18 +0530 Sumit Garg <sumit.garg@kernel.org> wrote:

> 
> Can you check if recent SD/eMMC fixes merged [1] are included in your tree?
> 
> [1] https://lore.kernel.org/all/20251210155454.1561611-1-loic.poulain@oss.qualcomm.com/
> 
> -Sumit
> 

I am using this[1] repository with latest commit as of Feb 03, 2026
and have verified that that fixes are present in this C files.
Similar to that change, I have tried to add the sdcc1 clocks but
the sd card is still not detected.

[1]: https://gitlab.postmarketos.org/tauchgang/u-boot

Thanks.

Re: [PATCH RFC 0/3] Add clk and pinctrl drivers for SM6125 SoC

[Biswapriyo Nath]

On Tue, 10 Feb 2026 15:42:58 +0300 Alexey Minnekhanov <alexeymin@minlexx.ru> wrote:

> Hi!
> 
> Is card detect GPIO set correctly for board?
> 
> Maybe you can verfy card detect is working by repeating the command:
> 
>   gpio status socXX
> 
> (where XX is your cd-gpio) while inserting/removing the SD card.
> 
> --
> Regards,
> Alexey Minnekhanov
> 

I have verified that card detect is working. Here are the outputs.

* with sd card:

=> gpio status
Bank soc:
soc98: input: 1 [x] mmc@4784000.cd-gpios

* without sd card:

=> gpio status
Bank soc:
soc98: input: 0 [x] mmc@4784000.cd-gpios

Thanks.