* [PATCH v3 0/6] boards: mediatek: initial support for Genio 720 EVK
@ 2026-03-23 20:16 David Lechner
2026-03-23 20:16 ` [PATCH v3 1/6] clk: mediatek: mt8189: add some VLP clocks David Lechner
` (6 more replies)
0 siblings, 7 replies; 15+ messages in thread
From: David Lechner @ 2026-03-23 20:16 UTC (permalink / raw)
To: Tom Rini, Ryder Lee, Weijie Gao, Chunfeng Yun, Igor Belwon,
GSS_MTK_Uboot_upstream, Macpaul Lin, Lukasz Majewski
Cc: Julien Stephan, u-boot, David Lechner, Chris-QJ Chen, Cathy Xu
These patches along with the listed prerequisites are enough to get the
MediaTek Genio 720 EVK board to boot into Linux from the eMMC (with a
bit of extra config that isn't included here because it isn't generic.)
This is currently being upstreamed in Linux as well, so we just have
some minimal devicetree files here to hold us over for a while until we
can switch to the upstream ones.
This depends on the pinctrl and all MediaTek clock patches from be
currently under review.
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
Changes in v3:
- Adapt clock patch to changes in dependency.
- Fix bugs found in init.c.
- Fix typo in commit message.
- Link to v2: https://patch.msgid.link/20260310-mtk-mt8391-initial-support-v2-0-1dc862d58532@baylibre.com
Changes in v2:
- New clock driver patch to add required clocks for PMIC.
- Added pinctrl nodes to both dts patches.
- Added "mediatek,mt8189-vlpckgen" clock controller node.
- Added "mt6359.dtsi" include and associated regulator changes.
- New patch with macros to support the change above.
- Fixed wrong CONFIG_PINCTRL_MT8391 in defconfig.
- Added defconfig and dts for virtually identical Genio 520 EVK.
- Enabled more config options for things that have already been merged.
- Link to v1: https://lore.kernel.org/r/20260209-mtk-mt8391-initial-support-v1-0-b23ab9d0b9bc@baylibre.com
---
Cathy Xu (1):
arm: dts: mediatek: mt8189: Add pinmux macro header file
Chris-QJ Chen (4):
arm: mediatek: add support of MT8189 SoC family
arm: dts: mediatek: Add MediaTek MT8189 dtsi file
arm: dts: mediatek: Add MediaTek Genio 520/720 EVK DTS
board: mediatek: Add Genio 520/720 EVK defconfigs
David Lechner (1):
clk: mediatek: mt8189: add some VLP clocks
arch/arm/dts/Makefile | 2 +
arch/arm/dts/mt8189-pinfunc.h | 1125 ++++++++++++++++++++++++++++++++
arch/arm/dts/mt8189.dtsi | 301 +++++++++
arch/arm/dts/mt8371-genio-520-evk.dts | 11 +
arch/arm/dts/mt8371-genio-common.dtsi | 176 +++++
arch/arm/dts/mt8391-genio-720-evk.dts | 11 +
arch/arm/mach-mediatek/Kconfig | 11 +-
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt8189/Makefile | 3 +
arch/arm/mach-mediatek/mt8189/init.c | 41 ++
board/mediatek/MAINTAINERS | 7 +
configs/mt8189.config | 34 +
configs/mt8371_genio_520_evk_defconfig | 4 +
configs/mt8391_genio_720_evk_defconfig | 4 +
drivers/clk/mediatek/clk-mt8189.c | 289 ++++++++
15 files changed, 2019 insertions(+), 1 deletion(-)
---
base-commit: eb00c710508d09b2a3b9aca75dd18280f1304703
change-id: 20260202-mtk-mt8391-initial-support-8ccdd761918b
prerequisite-message-id: <20260317-clk-mtk-unify-mux-parents-v3-0-a4760f5b0a80@baylibre.com>
prerequisite-patch-id: eaacb54acebe803c95a4416f9839632caa8bbe36
prerequisite-patch-id: 291f87bf8033440b0c79a03055cec7e1317216e2
prerequisite-patch-id: d3ff487de22ca508a65613bebf8cbe0e61005a31
prerequisite-patch-id: edb2b9a5644e0deb0b846cb6365957e8cdd9e9d8
prerequisite-patch-id: 14723a8815ed459c3995ba2682344f8c6813da74
prerequisite-patch-id: 5c528aa9c92e9d79fe406bca97192624f0267db9
prerequisite-patch-id: c5a12abe7b61f253d13966fc6b257995f085c7b0
prerequisite-patch-id: b4f5a8dafda57305a07cfc3783d7154558f515a6
prerequisite-patch-id: 9a33fdfe476f6dc0e9e314755073d308c6a61a1e
prerequisite-patch-id: 2daeb61c75b459c5c790266c329439a0fec5f50c
prerequisite-patch-id: 29f06542d7c519b8995bcebd04b800508cf32d1d
prerequisite-patch-id: 2d8a751c3012596e64b93e5361c7a50c8ac0a303
prerequisite-patch-id: 85f6c9b692293d482d04bb3661fb51dfb5533ef0
prerequisite-patch-id: 0700411359ab89ebd24c4c3d17a5864e41289547
prerequisite-patch-id: 688b2021a1585ae037c15081cf43e62d95e7c286
prerequisite-patch-id: 10f08bad47e8a2e6953c59540264dfa9ba433c1f
prerequisite-message-id: <20260303-mtk-clk-8365-drop-map-v1-1-17f81c375290@baylibre.com>
prerequisite-patch-id: 625ea8b616208d1c8a412ae514d8e94a3c13a6ff
prerequisite-message-id: <20260309-clk-mtk-mt8188-drop-extra-top-clocks-v1-0-6ee4743a8465@baylibre.com>
prerequisite-patch-id: 63670888fcc3abb762a182a7354216e2700a201a
prerequisite-patch-id: d8e4fd450697687889673ea835578739387d612a
prerequisite-message-id: <20260310-clk-mtk-parent-cleanup-v1-0-66175ca8f637@baylibre.com>
prerequisite-patch-id: 7d34eacfb07b05743fdb6bc7f2e9eaf9412652ef
prerequisite-patch-id: 4e840545a5c629bb437265dadc3278ec7896af31
prerequisite-patch-id: c8207aef95f4fe0e7035f2b568243c2897b47d5a
prerequisite-patch-id: d15f4c079134f0e0c8d7521473553f55ddbf6dd8
prerequisite-patch-id: 8c3bac0b04e5662fda9520bb1c5903973e383c66
prerequisite-patch-id: 09064d21f1d8db557f5cb42dd309a71d540ec16d
prerequisite-patch-id: c4353fb375d509fc658dae60611dd2058d2c50c1
prerequisite-patch-id: 5a8dbab74fc01b66fa5e644603a7026d7b6fb392
prerequisite-patch-id: c918d85e92db8e23718728d9f1c236bbf6dd4624
prerequisite-patch-id: 640dad8f1295f5705873dd1727d819dbd69a590d
prerequisite-patch-id: 053e35bb1e211602195bebe16a5995d42513d904
prerequisite-patch-id: da039a34a16a3aa95c8dd06d9af08034f04bdf5e
prerequisite-patch-id: f143e3daade6b31a725f4001a22cde49511ced90
prerequisite-patch-id: 5c229cbb3c52f65cdcee9c49182461ad70c81156
prerequisite-patch-id: 81df2ad9f9ee0f14b2d286cba72e863a9f7bfbeb
prerequisite-patch-id: 979df31ce215fedc030fed831060a07a15e672d8
prerequisite-message-id: <20260313-pinctrl-mtk-fix-mt8189-v1-0-607dd37fde37@baylibre.com>
prerequisite-patch-id: 7c53e753d42d5c9bc0c804e448f44a38da849133
prerequisite-patch-id: 6ab8dac0c634a91d74a3cc470caa5310e0796e2c
prerequisite-patch-id: aed7fb93e30e9eb9037a13777026d2bf134a582d
prerequisite-patch-id: e5471470a7ca7c30b62189a59c2a79a7d45a7db8
Best regards,
--
David Lechner <dlechner@baylibre.com>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 1/6] clk: mediatek: mt8189: add some VLP clocks
2026-03-23 20:16 [PATCH v3 0/6] boards: mediatek: initial support for Genio 720 EVK David Lechner
@ 2026-03-23 20:16 ` David Lechner
2026-03-23 20:23 ` Tom Rini
2026-03-23 20:16 ` [PATCH v3 2/6] arm: mediatek: add support of MT8189 SoC family David Lechner
` (5 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: David Lechner @ 2026-03-23 20:16 UTC (permalink / raw)
To: Tom Rini, Ryder Lee, Weijie Gao, Chunfeng Yun, Igor Belwon,
GSS_MTK_Uboot_upstream, Macpaul Lin, Lukasz Majewski
Cc: Julien Stephan, u-boot, David Lechner
Add some VLP clocks needed by the PMIC on MT8189 and similar SoCs.
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
drivers/clk/mediatek/clk-mt8189.c | 289 ++++++++++++++++++++++++++++++++++++++
1 file changed, 289 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c
index fec908728c0..9e640059f11 100644
--- a/drivers/clk/mediatek/clk-mt8189.c
+++ b/drivers/clk/mediatek/clk-mt8189.c
@@ -287,12 +287,16 @@ enum {
CLK_PAD_CLK32K,
CLK_PAD_CLK26M,
CLK_PAD_ULPOSC,
+ CLK_PAD_CLK13M,
+ CLK_PAD_AUD_ADC_EXT,
};
static ulong ext_clock_rates[] = {
[CLK_PAD_CLK32K] = 32000,
[CLK_PAD_CLK26M] = 26 * MHZ,
[CLK_PAD_ULPOSC] = 260 * MHZ,
+ [CLK_PAD_CLK13M] = 13 * MHZ,
+ [CLK_PAD_AUD_ADC_EXT] = 260 * MHZ,
};
#define MT8189_PLL_FMAX (3800UL * MHZ)
@@ -1637,6 +1641,258 @@ static const struct mtk_gate mminfra_config_clks[] = {
GATE_MMINFRA_CONFIG1(CLK_MMINFRA_GCE_26M, CLK_TOP_MMINFRA_SEL, 17),
};
+static const struct mtk_parent vlp_26m_oscd10_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+};
+
+static const struct mtk_parent vlp_vadsp_vowpll_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_VOWPLL),
+};
+
+static const struct mtk_parent vlp_sspm_ulposc_parents[] = {
+ EXT_PARENT(CLK_PAD_ULPOSC),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+};
+
+static const struct mtk_parent vlp_aud_adc_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_VOWPLL),
+ EXT_PARENT(CLK_PAD_AUD_ADC_EXT),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+};
+
+static const struct mtk_parent vlp_scp_iic_spi_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_MAINPLL_D5_D4),
+ TOP_PARENT(CLK_TOP_MAINPLL_D7_D2),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+};
+
+static const struct mtk_parent vlp_vadsp_uarthub_b_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2),
+};
+
+static const struct mtk_parent vlp_axi_kp_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+ TOP_PARENT(CLK_TOP_OSC_D2),
+ TOP_PARENT(CLK_TOP_MAINPLL_D7_D4),
+ TOP_PARENT(CLK_TOP_MAINPLL_D7_D2),
+};
+
+static const struct mtk_parent vlp_sspm_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+ TOP_PARENT(CLK_TOP_MAINPLL_D5_D2),
+ EXT_PARENT(CLK_PAD_ULPOSC),
+ TOP_PARENT(CLK_TOP_MAINPLL_D6),
+};
+
+static const struct mtk_parent vlp_pwm_vlp_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_OSC_D4),
+ EXT_PARENT(CLK_PAD_CLK32K),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+ TOP_PARENT(CLK_TOP_MAINPLL_D4_D8),
+};
+
+static const struct mtk_parent vlp_pwrap_ulposc_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+ TOP_PARENT(CLK_TOP_OSC_D7),
+ TOP_PARENT(CLK_TOP_OSC_D8),
+ TOP_PARENT(CLK_TOP_OSC_D16),
+ TOP_PARENT(CLK_TOP_MAINPLL_D7_D8),
+};
+
+static const struct mtk_parent vlp_vadsp_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_OSC_D20),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+ TOP_PARENT(CLK_TOP_OSC_D2),
+ EXT_PARENT(CLK_PAD_ULPOSC),
+ TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+};
+
+static const struct mtk_parent vlp_scp_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D4),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D3),
+ TOP_PARENT(CLK_TOP_MAINPLL_D3),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D6),
+ APMIXED_PARENT(CLK_APMIXED_APLL1),
+ TOP_PARENT(CLK_TOP_MAINPLL_D4),
+ TOP_PARENT(CLK_TOP_MAINPLL_D6),
+ TOP_PARENT(CLK_TOP_MAINPLL_D7),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+};
+
+static const struct mtk_parent vlp_spmi_p_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_F26M_CK_D2),
+ TOP_PARENT(CLK_TOP_OSC_D8),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+ TOP_PARENT(CLK_TOP_OSC_D16),
+ TOP_PARENT(CLK_TOP_OSC_D7),
+ EXT_PARENT(CLK_PAD_CLK32K),
+ TOP_PARENT(CLK_TOP_MAINPLL_D7_D8),
+ TOP_PARENT(CLK_TOP_MAINPLL_D6_D8),
+ TOP_PARENT(CLK_TOP_MAINPLL_D5_D8),
+};
+
+static const struct mtk_parent vlp_camtg_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8),
+ TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4),
+ TOP_PARENT(CLK_TOP_OSC_D16),
+ TOP_PARENT(CLK_TOP_OSC_D20),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D6_D16),
+ TOP_PARENT(CLK_TOP_TVDPLL1_D16),
+ TOP_PARENT(CLK_TOP_F26M_CK_D2),
+ TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10),
+ TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16),
+ TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32),
+};
+
+static const struct mtk_composite vlp_ck_muxes[] = {
+ /* VLP_CLK_CFG_0 */
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_SCP_SEL, vlp_scp_parents,
+ 0x008, 0x00c, 0x010, 0, 4, 7, 0x04, 0),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_PWRAP_ULPOSC_SEL, vlp_pwrap_ulposc_parents,
+ 0x008, 0x00c, 0x010, 8, 3, 0x04, 1),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SPMI_P_MST_SEL, vlp_spmi_p_parents,
+ 0x008, 0x00c, 0x010, 16, 4, 0x04, 2),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_DVFSRC_SEL, vlp_26m_oscd10_parents,
+ 0x008, 0x00c, 0x010, 24, 1, 0x04, 3),
+ /* VLP_CLK_CFG_1 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_PWM_VLP_SEL, vlp_pwm_vlp_parents,
+ 0x014, 0x018, 0x01c, 0, 3, 0x04, 4),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_AXI_VLP_SEL, vlp_axi_kp_parents,
+ 0x014, 0x018, 0x01c, 8, 3, 0x04, 5),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SYSTIMER_26M_SEL, vlp_26m_oscd10_parents,
+ 0x014, 0x018, 0x01c, 16, 1, 0x04, 6),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_SEL, vlp_sspm_parents,
+ 0x014, 0x018, 0x01c, 24, 3, 0x04, 7),
+ /* VLP_CLK_CFG_2 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_F26M_SEL, vlp_26m_oscd10_parents,
+ 0x020, 0x024, 0x028, 0, 1, 0x04, 8),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SRCK_SEL, vlp_26m_oscd10_parents,
+ 0x020, 0x024, 0x028, 8, 1, 0x04, 9),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_SPI_SEL, vlp_scp_iic_spi_parents,
+ 0x020, 0x024, 0x028, 16, 2, 0x04, 10),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_IIC_SEL, vlp_scp_iic_spi_parents,
+ 0x020, 0x024, 0x028, 24, 2, 0x04, 11),
+ /* VLP_CLK_CFG_3 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL,
+ vlp_scp_iic_spi_parents,
+ 0x02c, 0x030, 0x034, 0, 2, 0x04, 12),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL,
+ vlp_scp_iic_spi_parents,
+ 0x02c, 0x030, 0x034, 8, 2, 0x04, 13),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_ULPOSC_SEL, vlp_sspm_ulposc_parents,
+ 0x02c, 0x030, 0x034, 16, 2, 0x04, 14),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_APXGPT_26M_SEL, vlp_26m_oscd10_parents,
+ 0x02c, 0x030, 0x034, 24, 1, 0x04, 15),
+ /* VLP_CLK_CFG_4 */
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_SEL, vlp_vadsp_parents,
+ 0x038, 0x03c, 0x040, 0, 3, 7, 0x04, 16),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_VOWPLL_SEL,
+ vlp_vadsp_vowpll_parents,
+ 0x038, 0x03c, 0x040, 8, 1, 15, 0x04, 17),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_UARTHUB_BCLK_SEL,
+ vlp_vadsp_uarthub_b_parents,
+ 0x038, 0x03c, 0x040, 16, 2, 23, 0x04, 18),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG0_SEL, vlp_camtg_parents,
+ 0x038, 0x03c, 0x040, 24, 4, 31, 0x04, 19),
+ /* VLP_CLK_CFG_5 */
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG1_SEL, vlp_camtg_parents,
+ 0x044, 0x048, 0x04c, 0, 4, 7, 0x04, 20),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG2_SEL, vlp_camtg_parents,
+ 0x044, 0x048, 0x04c, 8, 4, 15, 0x04, 21),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_AUD_ADC_SEL, vlp_aud_adc_parents,
+ 0x044, 0x048, 0x04c, 16, 2, 23, 0x04, 22),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_KP_IRQ_GEN_SEL, vlp_axi_kp_parents,
+ 0x044, 0x048, 0x04c, 24, 3, 31, 0x04, 23),
+};
+
+static const struct mtk_gate_regs vlp_ck_gate_regs = {
+ .set_ofs = 0x1f4,
+ .clr_ofs = 0x1f8,
+ .sta_ofs = 0x1f0,
+};
+
+#define GATE_VLP_CK(id, parent, shift, flags) \
+ GATE_FLAGS(id, parent, &vlp_ck_gate_regs, shift, flags | CLK_GATE_NO_SETCLR_INV)
+
+#define GATE_VLP_CK_EXT(id, parent, shift) \
+ GATE_VLP_CK(id, parent, shift, CLK_PARENT_EXT)
+
+#define GATE_VLP_CK_TOP(id, parent, shift) \
+ GATE_VLP_CK(id, parent, shift, CLK_PARENT_TOPCKGEN)
+
+static const struct mtk_gate vlp_ck_gates[] = {
+ GATE_VLP_CK_EXT(CLK_VLP_CK_VADSYS_VLP_26M_EN, CLK_PAD_CLK26M, 1),
+ GATE_VLP_CK_EXT(CLK_VLP_CK_SEJ_13M_EN, CLK_PAD_CLK13M, 4),
+ GATE_VLP_CK_EXT(CLK_VLP_CK_SEJ_26M_EN, CLK_PAD_CLK26M, 5),
+ GATE_VLP_CK_TOP(CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN, CLK_TOP_OSC_D10, 11),
+};
+
+static const struct mtk_gate_regs vlpcfg_ao_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x4,
+};
+
+/*
+ * REVISIT: this is currently the only clock tree using the infrasys ops so we
+ * are using it instead of introducing a new parent in the core code. Instead,
+ * we should eventually rework the core code to do a better job of supporting
+ * arbitrary parent trees.
+ */
+#define CLK_PARENT_VLP_CK CLK_PARENT_INFRASYS
+
+#define GATE_VLPCFG_AO(id, parent, shift, flags) \
+ GATE_FLAGS(id, parent, &vlpcfg_ao_regs, shift, flags | CLK_GATE_NO_SETCLR_INV)
+
+#define GATE_VLPCFG_AO_EXT(id, parent, shift) \
+ GATE_VLPCFG_AO(id, parent, shift, CLK_PARENT_EXT)
+
+#define GATE_VLPCFG_AO_TOP(id, parent, shift) \
+ GATE_VLPCFG_AO(id, parent, shift, CLK_PARENT_TOPCKGEN)
+
+#define GATE_VLPCFG_AO_VLP(id, parent, shift) \
+ GATE_VLPCFG_AO(id, parent, shift, CLK_PARENT_VLP_CK)
+
+static const struct mtk_gate vlpcfg_ao_clks[] = {
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SCP, CLK_VLP_CK_SCP_SEL, 28),
+ GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_RG_R_APXGPT_26M, CLK_PAD_CLK26M, 24),
+ GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_DPMSRCK_TEST, CLK_PAD_CLK26M, 23),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_RG_DPMSRRTC_TEST, CLK_PAD_CLK32K, 22),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_DPMSRULP_TEST, CLK_TOP_OSC_D10, 21),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SPMI_P_MST, CLK_VLP_CK_SPMI_P_MST_SEL, 20),
+ GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_SPMI_P_MST_32K, CLK_PAD_CLK32K, 18),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_P_SYS, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 13),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_P_TMR, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 12),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_M_SYS, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 11),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_M_TMR, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 10),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_DVFSRC, CLK_VLP_CK_DVFSRC_SEL, 9),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PWM_VLP, CLK_VLP_CK_PWM_VLP_SEL, 8),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SRCK, CLK_VLP_CK_SRCK_SEL, 7),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SSPM_F26M, CLK_VLP_CK_SSPM_F26M_SEL, 4),
+ GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_SSPM_F32K, CLK_PAD_CLK32K, 3),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SSPM_ULPOSC, CLK_VLP_CK_SSPM_ULPOSC_SEL, 2),
+ GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_VLP_32K_COM, CLK_PAD_CLK32K, 1),
+ GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_VLP_26M_COM, CLK_PAD_CLK26M, 0),
+};
+
static const struct mtk_clk_tree mt8189_apmixedsys_clk_tree = {
.pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
.ext_clk_rates = ext_clock_rates,
@@ -1659,6 +1915,17 @@ static const struct mtk_clk_tree mt8189_topckgen_clk_tree = {
.num_gates = ARRAY_SIZE(top_gates),
};
+static const struct mtk_clk_tree mt8189_vlpckgen_clk_tree = {
+ .ext_clk_rates = ext_clock_rates,
+ .num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+ .muxes_offs = CLK_VLP_CK_SCP_SEL,
+ .gates_offs = CLK_VLP_CK_VADSYS_VLP_26M_EN,
+ .muxes = vlp_ck_muxes,
+ .gates = vlp_ck_gates,
+ .num_muxes = ARRAY_SIZE(vlp_ck_muxes),
+ .num_gates = ARRAY_SIZE(vlp_ck_gates),
+};
+
static const struct udevice_id mt8189_apmixed[] = {
{ .compatible = "mediatek,mt8189-apmixedsys", },
{ }
@@ -1669,6 +1936,11 @@ static const struct udevice_id mt8189_topckgen_compat[] = {
{ }
};
+static const struct udevice_id mt8189_vlpckgen[] = {
+ { .compatible = "mediatek,mt8189-vlpckgen", },
+ { }
+};
+
struct mt8189_gate_clk_data {
const struct mtk_gate *gates;
int num_gates;
@@ -1683,12 +1955,14 @@ GATE_CLK_DATA(perao_clks);
GATE_CLK_DATA(imp_clks);
GATE_CLK_DATA(mm_clks);
GATE_CLK_DATA(mminfra_config_clks);
+GATE_CLK_DATA(vlpcfg_ao_clks);
static const struct udevice_id of_match_mt8189_clk_gate[] = {
{ .compatible = "mediatek,mt8189-peri-ao", .data = (ulong)&perao_clks_data },
{ .compatible = "mediatek,mt8189-iic-wrap", .data = (ulong)&imp_clks_data },
{ .compatible = "mediatek,mt8189-dispsys", .data = (ulong)&mm_clks_data },
{ .compatible = "mediatek,mt8189-mm-infra", .data = (ulong)&mminfra_config_clks_data },
+ { .compatible = "mediatek,mt8189-vlpcfg-ao", .data = (ulong)&vlpcfg_ao_clks_data },
{ }
};
@@ -1702,6 +1976,11 @@ static int mt8189_topckgen_probe(struct udevice *dev)
return mtk_common_clk_init(dev, &mt8189_topckgen_clk_tree);
}
+static int mt8189_infrasys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_infrasys_init(dev, &mt8189_vlpckgen_clk_tree);
+}
+
static int mt8189_clk_gate_probe(struct udevice *dev)
{
struct mt8189_gate_clk_data *data;
@@ -1733,6 +2012,16 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = {
.flags = DM_FLAG_PRE_RELOC,
};
+U_BOOT_DRIVER(mtk_clk_vlpckgen) = {
+ .name = "mt8189-vlpckgen",
+ .id = UCLASS_CLK,
+ .of_match = mt8189_vlpckgen,
+ .probe = mt8189_infrasys_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_infrasys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
U_BOOT_DRIVER(mtk_clk_gate) = {
.name = "mt8189-gate-clk",
.id = UCLASS_CLK,
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 2/6] arm: mediatek: add support of MT8189 SoC family
2026-03-23 20:16 [PATCH v3 0/6] boards: mediatek: initial support for Genio 720 EVK David Lechner
2026-03-23 20:16 ` [PATCH v3 1/6] clk: mediatek: mt8189: add some VLP clocks David Lechner
@ 2026-03-23 20:16 ` David Lechner
2026-03-23 20:16 ` [PATCH v3 3/6] arm: dts: mediatek: mt8189: Add pinmux macro header file David Lechner
` (4 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: David Lechner @ 2026-03-23 20:16 UTC (permalink / raw)
To: Tom Rini, Ryder Lee, Weijie Gao, Chunfeng Yun, Igor Belwon,
GSS_MTK_Uboot_upstream, Macpaul Lin, Lukasz Majewski
Cc: Julien Stephan, u-boot, David Lechner, Chris-QJ Chen
From: Chris-QJ Chen <chris-qj.chen@mediatek.com>
Add TARGET_MT8189 for MT8189 and similar SoCs.
Signed-off-by: Chris-QJ Chen <chris-qj.chen@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
arch/arm/mach-mediatek/Kconfig | 11 ++++++++-
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt8189/Makefile | 3 +++
arch/arm/mach-mediatek/mt8189/init.c | 41 ++++++++++++++++++++++++++++++++++
4 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 671a6cb1cad..b5b06f4e5b2 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -93,6 +93,15 @@ config TARGET_MT8188
USB3.0 dual role, SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and
several LPDDR3 and LPDDR4 options.
+config TARGET_MT8189
+ bool "MediaTek MT8189 SoC"
+ select ARM64
+ help
+ The MediaTek MT8189 is a ARM64-based SoC with a dual-core Cortex-A78 and
+ a six-core Cortex-A55. It is including UART, SPI, USB3.0 dual role,
+ SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR4x
+ and LPDDR5x options.
+
config TARGET_MT8195
bool "MediaTek MT8195 SoC"
select ARM64
@@ -201,7 +210,7 @@ config SYS_CONFIG_NAME
config MTK_BROM_HEADER_INFO
string
default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629
- default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8188 || TARGET_MT8195
+ default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8188 || TARGET_MT8189 || TARGET_MT8195
default "lk=1" if TARGET_MT7623
config MTK_TZ_MOVABLE
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index d1f64d61ab9..35f748a70d6 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_TARGET_MT7987) += mt7987/
obj-$(CONFIG_TARGET_MT7988) += mt7988/
obj-$(CONFIG_TARGET_MT8183) += mt8183/
obj-$(CONFIG_TARGET_MT8188) += mt8188/
+obj-$(CONFIG_TARGET_MT8189) += mt8189/
obj-$(CONFIG_TARGET_MT8195) += mt8195/
obj-$(CONFIG_TARGET_MT8365) += mt8365/
obj-$(CONFIG_TARGET_MT8512) += mt8512/
diff --git a/arch/arm/mach-mediatek/mt8189/Makefile b/arch/arm/mach-mediatek/mt8189/Makefile
new file mode 100644
index 00000000000..886ab7e4eb9
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8189/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
diff --git a/arch/arm/mach-mediatek/mt8189/init.c b/arch/arm/mach-mediatek/mt8189/init.c
new file mode 100644
index 00000000000..648c17ac305
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8189/init.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 MediaTek Inc.
+ * Author: Chris-QJ Chen <chris-qj.chen@mediatek.com>
+ */
+
+#include <fdtdec.h>
+#include <stdio.h>
+#include <asm/global_data.h>
+#include <asm/system.h>
+#include <linux/kernel.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ /*
+ * Limit gd->ram_top not exceeding SZ_4G. Because some peripherals like
+ * MMC requires DMA buffer allocated below SZ_4G.
+ */
+ return min(SZ_4G - gd->ram_base, gd->ram_size);
+}
+
+void reset_cpu(ulong addr)
+{
+ if (!CONFIG_IS_ENABLED(SYSRESET))
+ psci_system_reset();
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT8189\n");
+
+ return 0;
+}
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 3/6] arm: dts: mediatek: mt8189: Add pinmux macro header file
2026-03-23 20:16 [PATCH v3 0/6] boards: mediatek: initial support for Genio 720 EVK David Lechner
2026-03-23 20:16 ` [PATCH v3 1/6] clk: mediatek: mt8189: add some VLP clocks David Lechner
2026-03-23 20:16 ` [PATCH v3 2/6] arm: mediatek: add support of MT8189 SoC family David Lechner
@ 2026-03-23 20:16 ` David Lechner
2026-03-23 20:16 ` [PATCH v3 4/6] arm: dts: mediatek: Add MediaTek MT8189 dtsi file David Lechner
` (3 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: David Lechner @ 2026-03-23 20:16 UTC (permalink / raw)
To: Tom Rini, Ryder Lee, Weijie Gao, Chunfeng Yun, Igor Belwon,
GSS_MTK_Uboot_upstream, Macpaul Lin, Lukasz Majewski
Cc: Julien Stephan, u-boot, David Lechner, Cathy Xu
From: Cathy Xu <ot_cathy.xu@mediatek.com>
Add the pinctrl header file on MediaTek mt8189.
Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
This is in the process of being upstreamed. Taken from latest
submission [1]. The plan is remove this when it has been upstreamed
and that makes it back in to U-Boot. Then we can change all mt8189-based
boards to OF_UPSTREAM.
[1]: https://lore.kernel.org/linux-mediatek/20251205064357.13591-1-ot_cathy.xu@mediatek.com/
---
arch/arm/dts/mt8189-pinfunc.h | 1125 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 1125 insertions(+)
diff --git a/arch/arm/dts/mt8189-pinfunc.h b/arch/arm/dts/mt8189-pinfunc.h
new file mode 100644
index 00000000000..df69f50c267
--- /dev/null
+++ b/arch/arm/dts/mt8189-pinfunc.h
@@ -0,0 +1,1125 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) 2025 MediaTek Inc.
+ * Author: Lei Xue <lei.xue@mediatek.com>
+ * Cathy Xu <ot_cathy.xu@mediatek.com>
+ */
+
+#ifndef __MT8189_PINFUNC_H
+#define __MT8189_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 1)
+#define PINMUX_GPIO0__FUNC_SPIM3_A_CSB (MTK_PIN_NO(0) | 2)
+#define PINMUX_GPIO0__FUNC_I2SOUT0_MCK (MTK_PIN_NO(0) | 3)
+#define PINMUX_GPIO0__FUNC_SCP_SPI0_CS (MTK_PIN_NO(0) | 4)
+#define PINMUX_GPIO0__FUNC_CONN_BPI_BUS6 (MTK_PIN_NO(0) | 6)
+#define PINMUX_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7)
+
+#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 1)
+#define PINMUX_GPIO1__FUNC_SPIM3_A_CLK (MTK_PIN_NO(1) | 2)
+#define PINMUX_GPIO1__FUNC_I2SOUT0_BCK (MTK_PIN_NO(1) | 3)
+#define PINMUX_GPIO1__FUNC_SCP_SPI0_CK (MTK_PIN_NO(1) | 4)
+#define PINMUX_GPIO1__FUNC_CONN_BPI_BUS7 (MTK_PIN_NO(1) | 6)
+#define PINMUX_GPIO1__FUNC_DBG_MON_A1 (MTK_PIN_NO(1) | 7)
+
+#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 1)
+#define PINMUX_GPIO2__FUNC_SPIM3_A_MO (MTK_PIN_NO(2) | 2)
+#define PINMUX_GPIO2__FUNC_I2SOUT0_LRCK (MTK_PIN_NO(2) | 3)
+#define PINMUX_GPIO2__FUNC_SCP_SPI0_MO (MTK_PIN_NO(2) | 4)
+#define PINMUX_GPIO2__FUNC_CONN_BPI_BUS8 (MTK_PIN_NO(2) | 6)
+#define PINMUX_GPIO2__FUNC_DBG_MON_A2 (MTK_PIN_NO(2) | 7)
+
+#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 1)
+#define PINMUX_GPIO3__FUNC_SPIM3_A_MI (MTK_PIN_NO(3) | 2)
+#define PINMUX_GPIO3__FUNC_I2SOUT0_DO (MTK_PIN_NO(3) | 3)
+#define PINMUX_GPIO3__FUNC_SCP_SPI0_MI (MTK_PIN_NO(3) | 4)
+#define PINMUX_GPIO3__FUNC_CONN_BPI_BUS9 (MTK_PIN_NO(3) | 6)
+#define PINMUX_GPIO3__FUNC_DBG_MON_A3 (MTK_PIN_NO(3) | 7)
+
+#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 1)
+#define PINMUX_GPIO4__FUNC_SPIM4_A_CSB (MTK_PIN_NO(4) | 2)
+#define PINMUX_GPIO4__FUNC_I2SIN0_DI (MTK_PIN_NO(4) | 3)
+#define PINMUX_GPIO4__FUNC_SCP_SPI1_CS (MTK_PIN_NO(4) | 4)
+#define PINMUX_GPIO4__FUNC_CONN_BPI_BUS10 (MTK_PIN_NO(4) | 6)
+#define PINMUX_GPIO4__FUNC_DBG_MON_A4 (MTK_PIN_NO(4) | 7)
+
+#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 1)
+#define PINMUX_GPIO5__FUNC_SPIM4_A_CLK (MTK_PIN_NO(5) | 2)
+#define PINMUX_GPIO5__FUNC_I2SIN0_BCK (MTK_PIN_NO(5) | 3)
+#define PINMUX_GPIO5__FUNC_SCP_SPI1_CK (MTK_PIN_NO(5) | 4)
+#define PINMUX_GPIO5__FUNC_CONN_BPI_BUS11_OLAT0 (MTK_PIN_NO(5) | 6)
+#define PINMUX_GPIO5__FUNC_DBG_MON_A5 (MTK_PIN_NO(5) | 7)
+
+#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 1)
+#define PINMUX_GPIO6__FUNC_SPIM4_A_MO (MTK_PIN_NO(6) | 2)
+#define PINMUX_GPIO6__FUNC_I2SIN0_LRCK (MTK_PIN_NO(6) | 3)
+#define PINMUX_GPIO6__FUNC_SCP_SPI1_MO (MTK_PIN_NO(6) | 4)
+#define PINMUX_GPIO6__FUNC_CONN_BPI_BUS12_OLAT1 (MTK_PIN_NO(6) | 6)
+#define PINMUX_GPIO6__FUNC_DBG_MON_A6 (MTK_PIN_NO(6) | 7)
+
+#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 1)
+#define PINMUX_GPIO7__FUNC_SPIM4_A_MI (MTK_PIN_NO(7) | 2)
+#define PINMUX_GPIO7__FUNC_I2SIN0_MCK (MTK_PIN_NO(7) | 3)
+#define PINMUX_GPIO7__FUNC_SCP_SPI1_MI (MTK_PIN_NO(7) | 4)
+#define PINMUX_GPIO7__FUNC_CONN_BPI_BUS13_OLAT2 (MTK_PIN_NO(7) | 6)
+#define PINMUX_GPIO7__FUNC_DBG_MON_A7 (MTK_PIN_NO(7) | 7)
+
+#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define PINMUX_GPIO8__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(8) | 1)
+#define PINMUX_GPIO8__FUNC_SPIM5_A_CSB (MTK_PIN_NO(8) | 2)
+#define PINMUX_GPIO8__FUNC_I2SOUT1_MCK (MTK_PIN_NO(8) | 3)
+#define PINMUX_GPIO8__FUNC_VADSP_UTXD0 (MTK_PIN_NO(8) | 4)
+#define PINMUX_GPIO8__FUNC_CONN_BPI_BUS14_OLAT3 (MTK_PIN_NO(8) | 6)
+#define PINMUX_GPIO8__FUNC_DBG_MON_A8 (MTK_PIN_NO(8) | 7)
+
+#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define PINMUX_GPIO9__FUNC_TP_URXD1_VLP (MTK_PIN_NO(9) | 1)
+#define PINMUX_GPIO9__FUNC_SPIM5_A_CLK (MTK_PIN_NO(9) | 2)
+#define PINMUX_GPIO9__FUNC_I2SOUT1_BCK (MTK_PIN_NO(9) | 3)
+#define PINMUX_GPIO9__FUNC_VADSP_URXD0 (MTK_PIN_NO(9) | 4)
+#define PINMUX_GPIO9__FUNC_CONN_BPI_BUS15_OLAT4 (MTK_PIN_NO(9) | 6)
+#define PINMUX_GPIO9__FUNC_DBG_MON_A9 (MTK_PIN_NO(9) | 7)
+
+#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define PINMUX_GPIO10__FUNC_TP_UCTS1_VLP (MTK_PIN_NO(10) | 1)
+#define PINMUX_GPIO10__FUNC_SPIM5_A_MO (MTK_PIN_NO(10) | 2)
+#define PINMUX_GPIO10__FUNC_I2SOUT1_LRCK (MTK_PIN_NO(10) | 3)
+#define PINMUX_GPIO10__FUNC_SRCLKENAI0 (MTK_PIN_NO(10) | 4)
+#define PINMUX_GPIO10__FUNC_CONN_BPI_BUS16_OLAT5 (MTK_PIN_NO(10) | 6)
+#define PINMUX_GPIO10__FUNC_DBG_MON_A10 (MTK_PIN_NO(10) | 7)
+
+#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define PINMUX_GPIO11__FUNC_TP_URTS1_VLP (MTK_PIN_NO(11) | 1)
+#define PINMUX_GPIO11__FUNC_SPIM5_A_MI (MTK_PIN_NO(11) | 2)
+#define PINMUX_GPIO11__FUNC_I2SOUT1_DO (MTK_PIN_NO(11) | 3)
+#define PINMUX_GPIO11__FUNC_SRCLKENAI1 (MTK_PIN_NO(11) | 4)
+#define PINMUX_GPIO11__FUNC_PWM_vlp (MTK_PIN_NO(11) | 5)
+#define PINMUX_GPIO11__FUNC_DBG_MON_A11 (MTK_PIN_NO(11) | 7)
+
+#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define PINMUX_GPIO12__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(12) | 1)
+#define PINMUX_GPIO12__FUNC_UTXD3 (MTK_PIN_NO(12) | 2)
+#define PINMUX_GPIO12__FUNC_CLKM0 (MTK_PIN_NO(12) | 3)
+#define PINMUX_GPIO12__FUNC_CMFLASH0 (MTK_PIN_NO(12) | 4)
+#define PINMUX_GPIO12__FUNC_ANT_SEL0 (MTK_PIN_NO(12) | 6)
+#define PINMUX_GPIO12__FUNC_DBG_MON_B20 (MTK_PIN_NO(12) | 7)
+
+#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define PINMUX_GPIO13__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(13) | 1)
+#define PINMUX_GPIO13__FUNC_URXD3 (MTK_PIN_NO(13) | 2)
+#define PINMUX_GPIO13__FUNC_CLKM1 (MTK_PIN_NO(13) | 3)
+#define PINMUX_GPIO13__FUNC_CMFLASH1 (MTK_PIN_NO(13) | 4)
+#define PINMUX_GPIO13__FUNC_ANT_SEL1 (MTK_PIN_NO(13) | 6)
+#define PINMUX_GPIO13__FUNC_DBG_MON_B21 (MTK_PIN_NO(13) | 7)
+
+#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define PINMUX_GPIO14__FUNC_TP_UCTS1_VCORE (MTK_PIN_NO(14) | 1)
+#define PINMUX_GPIO14__FUNC_UCTS3 (MTK_PIN_NO(14) | 2)
+#define PINMUX_GPIO14__FUNC_CLKM2 (MTK_PIN_NO(14) | 3)
+#define PINMUX_GPIO14__FUNC_CMFLASH2 (MTK_PIN_NO(14) | 4)
+#define PINMUX_GPIO14__FUNC_ANT_SEL2 (MTK_PIN_NO(14) | 6)
+#define PINMUX_GPIO14__FUNC_DBG_MON_B22 (MTK_PIN_NO(14) | 7)
+
+#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define PINMUX_GPIO15__FUNC_TP_URTS1_VCORE (MTK_PIN_NO(15) | 1)
+#define PINMUX_GPIO15__FUNC_URTS3 (MTK_PIN_NO(15) | 2)
+#define PINMUX_GPIO15__FUNC_CLKM3 (MTK_PIN_NO(15) | 3)
+#define PINMUX_GPIO15__FUNC_CMVREF0 (MTK_PIN_NO(15) | 4)
+#define PINMUX_GPIO15__FUNC_ANT_SEL3 (MTK_PIN_NO(15) | 6)
+#define PINMUX_GPIO15__FUNC_DBG_MON_B23 (MTK_PIN_NO(15) | 7)
+
+#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
+#define PINMUX_GPIO16__FUNC_PWM_0 (MTK_PIN_NO(16) | 1)
+#define PINMUX_GPIO16__FUNC_UCTS2 (MTK_PIN_NO(16) | 2)
+#define PINMUX_GPIO16__FUNC_DP_TX_HPD (MTK_PIN_NO(16) | 3)
+#define PINMUX_GPIO16__FUNC_CMVREF1 (MTK_PIN_NO(16) | 4)
+#define PINMUX_GPIO16__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(16) | 5)
+#define PINMUX_GPIO16__FUNC_ANT_SEL4 (MTK_PIN_NO(16) | 6)
+#define PINMUX_GPIO16__FUNC_DBG_MON_B24 (MTK_PIN_NO(16) | 7)
+
+#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
+#define PINMUX_GPIO17__FUNC_PWM_1 (MTK_PIN_NO(17) | 1)
+#define PINMUX_GPIO17__FUNC_URTS2 (MTK_PIN_NO(17) | 2)
+#define PINMUX_GPIO17__FUNC_EDP_TX_HPD (MTK_PIN_NO(17) | 3)
+#define PINMUX_GPIO17__FUNC_CMVREF2 (MTK_PIN_NO(17) | 4)
+#define PINMUX_GPIO17__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(17) | 5)
+#define PINMUX_GPIO17__FUNC_PMSR_SMAP (MTK_PIN_NO(17) | 6)
+#define PINMUX_GPIO17__FUNC_DBG_MON_B25 (MTK_PIN_NO(17) | 7)
+
+#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define PINMUX_GPIO18__FUNC_CMFLASH0 (MTK_PIN_NO(18) | 1)
+#define PINMUX_GPIO18__FUNC_CMVREF3 (MTK_PIN_NO(18) | 2)
+#define PINMUX_GPIO18__FUNC_UTXD2 (MTK_PIN_NO(18) | 3)
+#define PINMUX_GPIO18__FUNC_DISP_PWM1 (MTK_PIN_NO(18) | 4)
+#define PINMUX_GPIO18__FUNC_I2SIN1_MCK (MTK_PIN_NO(18) | 5)
+#define PINMUX_GPIO18__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(18) | 6)
+#define PINMUX_GPIO18__FUNC_DBG_MON_A12 (MTK_PIN_NO(18) | 7)
+
+#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define PINMUX_GPIO19__FUNC_CMFLASH1 (MTK_PIN_NO(19) | 1)
+#define PINMUX_GPIO19__FUNC_CMVREF2 (MTK_PIN_NO(19) | 2)
+#define PINMUX_GPIO19__FUNC_URXD2 (MTK_PIN_NO(19) | 3)
+#define PINMUX_GPIO19__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(19) | 4)
+#define PINMUX_GPIO19__FUNC_I2SIN1_BCK (MTK_PIN_NO(19) | 5)
+#define PINMUX_GPIO19__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(19) | 6)
+#define PINMUX_GPIO19__FUNC_DBG_MON_A13 (MTK_PIN_NO(19) | 7)
+
+#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define PINMUX_GPIO20__FUNC_CMFLASH2 (MTK_PIN_NO(20) | 1)
+#define PINMUX_GPIO20__FUNC_CMVREF1 (MTK_PIN_NO(20) | 2)
+#define PINMUX_GPIO20__FUNC_UCTS2 (MTK_PIN_NO(20) | 3)
+#define PINMUX_GPIO20__FUNC_PERSTN (MTK_PIN_NO(20) | 4)
+#define PINMUX_GPIO20__FUNC_I2SIN1_LRCK (MTK_PIN_NO(20) | 5)
+#define PINMUX_GPIO20__FUNC_DMIC0_DAT1 (MTK_PIN_NO(20) | 6)
+#define PINMUX_GPIO20__FUNC_DBG_MON_A14 (MTK_PIN_NO(20) | 7)
+
+#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define PINMUX_GPIO21__FUNC_CMFLASH3 (MTK_PIN_NO(21) | 1)
+#define PINMUX_GPIO21__FUNC_CMVREF0 (MTK_PIN_NO(21) | 2)
+#define PINMUX_GPIO21__FUNC_URTS2 (MTK_PIN_NO(21) | 3)
+#define PINMUX_GPIO21__FUNC_CLKREQN (MTK_PIN_NO(21) | 4)
+#define PINMUX_GPIO21__FUNC_I2SIN1_DI (MTK_PIN_NO(21) | 5)
+#define PINMUX_GPIO21__FUNC_DMIC1_DAT1 (MTK_PIN_NO(21) | 6)
+#define PINMUX_GPIO21__FUNC_DBG_MON_A15 (MTK_PIN_NO(21) | 7)
+
+#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define PINMUX_GPIO22__FUNC_CMMCLK0 (MTK_PIN_NO(22) | 1)
+#define PINMUX_GPIO22__FUNC_TP_GPIO4_AO (MTK_PIN_NO(22) | 2)
+
+#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define PINMUX_GPIO23__FUNC_CMMCLK1 (MTK_PIN_NO(23) | 1)
+#define PINMUX_GPIO23__FUNC_TP_GPIO5_AO (MTK_PIN_NO(23) | 2)
+#define PINMUX_GPIO23__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(23) | 3)
+#define PINMUX_GPIO23__FUNC_PWM_vlp (MTK_PIN_NO(23) | 4)
+#define PINMUX_GPIO23__FUNC_SRCLKENAI0 (MTK_PIN_NO(23) | 6)
+
+#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define PINMUX_GPIO24__FUNC_CMMCLK2 (MTK_PIN_NO(24) | 1)
+#define PINMUX_GPIO24__FUNC_TP_GPIO6_AO (MTK_PIN_NO(24) | 2)
+#define PINMUX_GPIO24__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(24) | 3)
+#define PINMUX_GPIO24__FUNC_WAKEN (MTK_PIN_NO(24) | 4)
+#define PINMUX_GPIO24__FUNC_SPMI_P_TRIG_FLAG (MTK_PIN_NO(24) | 5)
+#define PINMUX_GPIO24__FUNC_SRCLKENAI1 (MTK_PIN_NO(24) | 6)
+
+#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define PINMUX_GPIO25__FUNC_LCM_RST (MTK_PIN_NO(25) | 1)
+#define PINMUX_GPIO25__FUNC_DP_TX_HPD (MTK_PIN_NO(25) | 2)
+#define PINMUX_GPIO25__FUNC_CMFLASH3 (MTK_PIN_NO(25) | 3)
+#define PINMUX_GPIO25__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(25) | 4)
+#define PINMUX_GPIO25__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(25) | 5)
+
+#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define PINMUX_GPIO26__FUNC_DSI_TE (MTK_PIN_NO(26) | 1)
+#define PINMUX_GPIO26__FUNC_EDP_TX_HPD (MTK_PIN_NO(26) | 2)
+#define PINMUX_GPIO26__FUNC_CMVREF3 (MTK_PIN_NO(26) | 3)
+#define PINMUX_GPIO26__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(26) | 4)
+#define PINMUX_GPIO26__FUNC_USB_DRVVBUS_3P (MTK_PIN_NO(26) | 5)
+
+#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define PINMUX_GPIO27__FUNC_DP_TX_HPD (MTK_PIN_NO(27) | 1)
+#define PINMUX_GPIO27__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(27) | 2)
+#define PINMUX_GPIO27__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(27) | 3)
+#define PINMUX_GPIO27__FUNC_TP_UCTS1_VCORE (MTK_PIN_NO(27) | 4)
+#define PINMUX_GPIO27__FUNC_CMVREF4 (MTK_PIN_NO(27) | 5)
+#define PINMUX_GPIO27__FUNC_EXTIF0_ACT (MTK_PIN_NO(27) | 6)
+#define PINMUX_GPIO27__FUNC_ANT_SEL0 (MTK_PIN_NO(27) | 7)
+
+#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define PINMUX_GPIO28__FUNC_EDP_TX_HPD (MTK_PIN_NO(28) | 1)
+#define PINMUX_GPIO28__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(28) | 2)
+#define PINMUX_GPIO28__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(28) | 3)
+#define PINMUX_GPIO28__FUNC_TP_URTS1_VCORE (MTK_PIN_NO(28) | 4)
+#define PINMUX_GPIO28__FUNC_EXTIF0_PRI (MTK_PIN_NO(28) | 6)
+#define PINMUX_GPIO28__FUNC_ANT_SEL1 (MTK_PIN_NO(28) | 7)
+
+#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define PINMUX_GPIO29__FUNC_DISP_PWM0 (MTK_PIN_NO(29) | 1)
+#define PINMUX_GPIO29__FUNC_MD32_1_TXD (MTK_PIN_NO(29) | 2)
+#define PINMUX_GPIO29__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(29) | 3)
+#define PINMUX_GPIO29__FUNC_USB_DRVVBUS_4P (MTK_PIN_NO(29) | 5)
+
+#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
+#define PINMUX_GPIO30__FUNC_DISP_PWM1 (MTK_PIN_NO(30) | 1)
+#define PINMUX_GPIO30__FUNC_MD32_1_RXD (MTK_PIN_NO(30) | 2)
+#define PINMUX_GPIO30__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(30) | 3)
+#define PINMUX_GPIO30__FUNC_PMSR_SMAP (MTK_PIN_NO(30) | 5)
+#define PINMUX_GPIO30__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(30) | 6)
+#define PINMUX_GPIO30__FUNC_ANT_SEL2 (MTK_PIN_NO(30) | 7)
+
+#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
+#define PINMUX_GPIO31__FUNC_UTXD0 (MTK_PIN_NO(31) | 1)
+#define PINMUX_GPIO31__FUNC_MD32_0_TXD (MTK_PIN_NO(31) | 2)
+
+#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
+#define PINMUX_GPIO32__FUNC_URXD0 (MTK_PIN_NO(32) | 1)
+#define PINMUX_GPIO32__FUNC_MD32_0_RXD (MTK_PIN_NO(32) | 2)
+
+#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define PINMUX_GPIO33__FUNC_UTXD1 (MTK_PIN_NO(33) | 1)
+#define PINMUX_GPIO33__FUNC_VADSP_UTXD0 (MTK_PIN_NO(33) | 2)
+#define PINMUX_GPIO33__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(33) | 3)
+#define PINMUX_GPIO33__FUNC_MD32_1_TXD (MTK_PIN_NO(33) | 4)
+#define PINMUX_GPIO33__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(33) | 5)
+#define PINMUX_GPIO33__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(33) | 6)
+
+#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define PINMUX_GPIO34__FUNC_URXD1 (MTK_PIN_NO(34) | 1)
+#define PINMUX_GPIO34__FUNC_VADSP_URXD0 (MTK_PIN_NO(34) | 2)
+#define PINMUX_GPIO34__FUNC_TP_URXD1_VLP (MTK_PIN_NO(34) | 3)
+#define PINMUX_GPIO34__FUNC_MD32_1_RXD (MTK_PIN_NO(34) | 4)
+#define PINMUX_GPIO34__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(34) | 5)
+
+#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define PINMUX_GPIO35__FUNC_UTXD2 (MTK_PIN_NO(35) | 1)
+#define PINMUX_GPIO35__FUNC_UCTS1 (MTK_PIN_NO(35) | 2)
+#define PINMUX_GPIO35__FUNC_TP_UCTS1_VLP (MTK_PIN_NO(35) | 3)
+#define PINMUX_GPIO35__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(35) | 4)
+#define PINMUX_GPIO35__FUNC_VADSP_UTXD0 (MTK_PIN_NO(35) | 5)
+#define PINMUX_GPIO35__FUNC_CONN_BT_TXD (MTK_PIN_NO(35) | 6)
+
+#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define PINMUX_GPIO36__FUNC_URXD2 (MTK_PIN_NO(36) | 1)
+#define PINMUX_GPIO36__FUNC_URTS1 (MTK_PIN_NO(36) | 2)
+#define PINMUX_GPIO36__FUNC_TP_URTS1_VLP (MTK_PIN_NO(36) | 3)
+#define PINMUX_GPIO36__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(36) | 4)
+#define PINMUX_GPIO36__FUNC_VADSP_URXD0 (MTK_PIN_NO(36) | 5)
+
+#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define PINMUX_GPIO37__FUNC_UTXD3 (MTK_PIN_NO(37) | 1)
+#define PINMUX_GPIO37__FUNC_UCTS0 (MTK_PIN_NO(37) | 2)
+#define PINMUX_GPIO37__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(37) | 3)
+#define PINMUX_GPIO37__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(37) | 4)
+#define PINMUX_GPIO37__FUNC_MD32_0_TXD (MTK_PIN_NO(37) | 6)
+#define PINMUX_GPIO37__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(37) | 7)
+
+#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
+#define PINMUX_GPIO38__FUNC_URXD3 (MTK_PIN_NO(38) | 1)
+#define PINMUX_GPIO38__FUNC_URTS0 (MTK_PIN_NO(38) | 2)
+#define PINMUX_GPIO38__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(38) | 3)
+#define PINMUX_GPIO38__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(38) | 4)
+#define PINMUX_GPIO38__FUNC_MD32_0_RXD (MTK_PIN_NO(38) | 6)
+#define PINMUX_GPIO38__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(38) | 7)
+
+#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define PINMUX_GPIO39__FUNC_JTMS_SEL1 (MTK_PIN_NO(39) | 1)
+
+#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define PINMUX_GPIO40__FUNC_JTCK_SEL1 (MTK_PIN_NO(40) | 1)
+
+#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define PINMUX_GPIO41__FUNC_JTDI_SEL1 (MTK_PIN_NO(41) | 1)
+
+#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define PINMUX_GPIO42__FUNC_JTDO_SEL1 (MTK_PIN_NO(42) | 1)
+
+#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define PINMUX_GPIO43__FUNC_JTRSTn_SEL1 (MTK_PIN_NO(43) | 1)
+
+#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define PINMUX_GPIO44__FUNC_KPCOL0 (MTK_PIN_NO(44) | 1)
+
+#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define PINMUX_GPIO45__FUNC_KPCOL1 (MTK_PIN_NO(45) | 1)
+#define PINMUX_GPIO45__FUNC_TP_GPIO0_AO (MTK_PIN_NO(45) | 2)
+#define PINMUX_GPIO45__FUNC_SRCLKENAI1 (MTK_PIN_NO(45) | 3)
+#define PINMUX_GPIO45__FUNC_DBG_MON_A31 (MTK_PIN_NO(45) | 7)
+
+#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define PINMUX_GPIO46__FUNC_KPROW0 (MTK_PIN_NO(46) | 1)
+#define PINMUX_GPIO46__FUNC_TP_GPIO1_AO (MTK_PIN_NO(46) | 2)
+
+#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define PINMUX_GPIO47__FUNC_KPROW1 (MTK_PIN_NO(47) | 1)
+#define PINMUX_GPIO47__FUNC_TP_GPIO2_AO (MTK_PIN_NO(47) | 2)
+#define PINMUX_GPIO47__FUNC_SRCLKENAI0 (MTK_PIN_NO(47) | 3)
+#define PINMUX_GPIO47__FUNC_DBG_MON_A32 (MTK_PIN_NO(47) | 7)
+
+#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define PINMUX_GPIO48__FUNC_WAKEN (MTK_PIN_NO(48) | 1)
+#define PINMUX_GPIO48__FUNC_TP_GPIO3_AO (MTK_PIN_NO(48) | 2)
+#define PINMUX_GPIO48__FUNC_SPMI_P_TRIG_FLAG (MTK_PIN_NO(48) | 3)
+
+#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define PINMUX_GPIO49__FUNC_PERSTN (MTK_PIN_NO(49) | 1)
+#define PINMUX_GPIO49__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(49) | 2)
+#define PINMUX_GPIO49__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(49) | 3)
+#define PINMUX_GPIO49__FUNC_ANT_SEL3 (MTK_PIN_NO(49) | 7)
+
+#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
+#define PINMUX_GPIO50__FUNC_CLKREQN (MTK_PIN_NO(50) | 1)
+#define PINMUX_GPIO50__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(50) | 2)
+#define PINMUX_GPIO50__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(50) | 3)
+#define PINMUX_GPIO50__FUNC_ANT_SEL4 (MTK_PIN_NO(50) | 7)
+
+#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
+#define PINMUX_GPIO51__FUNC_SCP_SCL0 (MTK_PIN_NO(51) | 1)
+#define PINMUX_GPIO51__FUNC_SCL0 (MTK_PIN_NO(51) | 2)
+
+#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
+#define PINMUX_GPIO52__FUNC_SCP_SDA0 (MTK_PIN_NO(52) | 1)
+#define PINMUX_GPIO52__FUNC_SDA0 (MTK_PIN_NO(52) | 2)
+
+#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define PINMUX_GPIO53__FUNC_SCP_SCL1 (MTK_PIN_NO(53) | 1)
+#define PINMUX_GPIO53__FUNC_SCL1 (MTK_PIN_NO(53) | 2)
+
+#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define PINMUX_GPIO54__FUNC_SCP_SDA1 (MTK_PIN_NO(54) | 1)
+#define PINMUX_GPIO54__FUNC_SDA1 (MTK_PIN_NO(54) | 2)
+
+#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define PINMUX_GPIO55__FUNC_SCL2 (MTK_PIN_NO(55) | 1)
+#define PINMUX_GPIO55__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(55) | 2)
+#define PINMUX_GPIO55__FUNC_SSUSB_U2SIF_SCL (MTK_PIN_NO(55) | 3)
+
+#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define PINMUX_GPIO56__FUNC_SDA2 (MTK_PIN_NO(56) | 1)
+#define PINMUX_GPIO56__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(56) | 2)
+#define PINMUX_GPIO56__FUNC_SSUSB_U2SIF_SDA (MTK_PIN_NO(56) | 3)
+
+#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define PINMUX_GPIO57__FUNC_SCL3 (MTK_PIN_NO(57) | 1)
+#define PINMUX_GPIO57__FUNC_PCIE_PHY_I2C_SCL (MTK_PIN_NO(57) | 2)
+#define PINMUX_GPIO57__FUNC_SSUSB_U2SIF_SCL_1P (MTK_PIN_NO(57) | 3)
+
+#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define PINMUX_GPIO58__FUNC_SDA3 (MTK_PIN_NO(58) | 1)
+#define PINMUX_GPIO58__FUNC_PCIE_PHY_I2C_SDA (MTK_PIN_NO(58) | 2)
+#define PINMUX_GPIO58__FUNC_SSUSB_U2SIF_SDA_1P (MTK_PIN_NO(58) | 3)
+
+#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
+#define PINMUX_GPIO59__FUNC_SCL4 (MTK_PIN_NO(59) | 1)
+#define PINMUX_GPIO59__FUNC_SSUSB_U3PHY_I2C_SCL (MTK_PIN_NO(59) | 2)
+
+#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define PINMUX_GPIO60__FUNC_SDA4 (MTK_PIN_NO(60) | 1)
+#define PINMUX_GPIO60__FUNC_SSUSB_U3PHY_I2C_SDA (MTK_PIN_NO(60) | 2)
+
+#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define PINMUX_GPIO61__FUNC_SCL5 (MTK_PIN_NO(61) | 1)
+#define PINMUX_GPIO61__FUNC_SSPXTP_U3PHY_I2C_SCL (MTK_PIN_NO(61) | 2)
+
+#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define PINMUX_GPIO62__FUNC_SDA5 (MTK_PIN_NO(62) | 1)
+#define PINMUX_GPIO62__FUNC_SSPXTP_U3PHY_I2C_SDA (MTK_PIN_NO(62) | 2)
+
+#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define PINMUX_GPIO63__FUNC_SCL6 (MTK_PIN_NO(63) | 1)
+
+#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define PINMUX_GPIO64__FUNC_SDA6 (MTK_PIN_NO(64) | 1)
+
+#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define PINMUX_GPIO65__FUNC_SCL7 (MTK_PIN_NO(65) | 1)
+
+#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define PINMUX_GPIO66__FUNC_SDA7 (MTK_PIN_NO(66) | 1)
+
+#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define PINMUX_GPIO67__FUNC_SCL8 (MTK_PIN_NO(67) | 1)
+
+#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define PINMUX_GPIO68__FUNC_SDA8 (MTK_PIN_NO(68) | 1)
+
+#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define PINMUX_GPIO69__FUNC_SPIM0_CSB (MTK_PIN_NO(69) | 1)
+#define PINMUX_GPIO69__FUNC_SCP_SPI0_CS (MTK_PIN_NO(69) | 2)
+#define PINMUX_GPIO69__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(69) | 3)
+#define PINMUX_GPIO69__FUNC_VADSP_JTAG0_TMS (MTK_PIN_NO(69) | 4)
+#define PINMUX_GPIO69__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(69) | 5)
+#define PINMUX_GPIO69__FUNC_SSPM_JTAG_TMS_VLP (MTK_PIN_NO(69) | 6)
+#define PINMUX_GPIO69__FUNC_SCP_JTAG0_TMS_VLP (MTK_PIN_NO(69) | 7)
+
+#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define PINMUX_GPIO70__FUNC_SPIM0_CLK (MTK_PIN_NO(70) | 1)
+#define PINMUX_GPIO70__FUNC_SCP_SPI0_CK (MTK_PIN_NO(70) | 2)
+#define PINMUX_GPIO70__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(70) | 3)
+#define PINMUX_GPIO70__FUNC_VADSP_JTAG0_TCK (MTK_PIN_NO(70) | 4)
+#define PINMUX_GPIO70__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(70) | 5)
+#define PINMUX_GPIO70__FUNC_SSPM_JTAG_TCK_VLP (MTK_PIN_NO(70) | 6)
+#define PINMUX_GPIO70__FUNC_SCP_JTAG0_TCK_VLP (MTK_PIN_NO(70) | 7)
+
+#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define PINMUX_GPIO71__FUNC_SPIM0_MO (MTK_PIN_NO(71) | 1)
+#define PINMUX_GPIO71__FUNC_SCP_SPI0_MO (MTK_PIN_NO(71) | 2)
+#define PINMUX_GPIO71__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(71) | 3)
+#define PINMUX_GPIO71__FUNC_VADSP_JTAG0_TDI (MTK_PIN_NO(71) | 4)
+#define PINMUX_GPIO71__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(71) | 5)
+#define PINMUX_GPIO71__FUNC_SSPM_JTAG_TDI_VLP (MTK_PIN_NO(71) | 6)
+#define PINMUX_GPIO71__FUNC_SCP_JTAG0_TDI_VLP (MTK_PIN_NO(71) | 7)
+
+#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define PINMUX_GPIO72__FUNC_SPIM0_MI (MTK_PIN_NO(72) | 1)
+#define PINMUX_GPIO72__FUNC_SCP_SPI0_MI (MTK_PIN_NO(72) | 2)
+#define PINMUX_GPIO72__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(72) | 3)
+#define PINMUX_GPIO72__FUNC_VADSP_JTAG0_TDO (MTK_PIN_NO(72) | 4)
+#define PINMUX_GPIO72__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(72) | 5)
+#define PINMUX_GPIO72__FUNC_SSPM_JTAG_TDO_VLP (MTK_PIN_NO(72) | 6)
+#define PINMUX_GPIO72__FUNC_SCP_JTAG0_TDO_VLP (MTK_PIN_NO(72) | 7)
+
+#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define PINMUX_GPIO73__FUNC_SPIM1_CSB (MTK_PIN_NO(73) | 1)
+#define PINMUX_GPIO73__FUNC_SCP_SPI1_CS (MTK_PIN_NO(73) | 2)
+#define PINMUX_GPIO73__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(73) | 3)
+#define PINMUX_GPIO73__FUNC_VADSP_JTAG0_TRSTN (MTK_PIN_NO(73) | 4)
+#define PINMUX_GPIO73__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(73) | 5)
+#define PINMUX_GPIO73__FUNC_SSPM_JTAG_TRSTN_VLP (MTK_PIN_NO(73) | 6)
+#define PINMUX_GPIO73__FUNC_SCP_JTAG0_TRSTN_VLP (MTK_PIN_NO(73) | 7)
+
+#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define PINMUX_GPIO74__FUNC_SPIM1_CLK (MTK_PIN_NO(74) | 1)
+#define PINMUX_GPIO74__FUNC_SCP_SPI1_CK (MTK_PIN_NO(74) | 2)
+
+#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define PINMUX_GPIO75__FUNC_SPIM1_MO (MTK_PIN_NO(75) | 1)
+#define PINMUX_GPIO75__FUNC_SCP_SPI1_MO (MTK_PIN_NO(75) | 2)
+
+#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define PINMUX_GPIO76__FUNC_SPIM1_MI (MTK_PIN_NO(76) | 1)
+#define PINMUX_GPIO76__FUNC_SCP_SPI1_MI (MTK_PIN_NO(76) | 2)
+
+#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define PINMUX_GPIO77__FUNC_SPIM2_CSB (MTK_PIN_NO(77) | 1)
+#define PINMUX_GPIO77__FUNC_PCM0_SYNC (MTK_PIN_NO(77) | 2)
+#define PINMUX_GPIO77__FUNC_SSUSB_U2SIF_SCL (MTK_PIN_NO(77) | 3)
+#define PINMUX_GPIO77__FUNC_DBG_MON_A27 (MTK_PIN_NO(77) | 7)
+
+#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define PINMUX_GPIO78__FUNC_SPIM2_CLK (MTK_PIN_NO(78) | 1)
+#define PINMUX_GPIO78__FUNC_PCM0_CLK (MTK_PIN_NO(78) | 2)
+#define PINMUX_GPIO78__FUNC_SSUSB_U2SIF_SDA (MTK_PIN_NO(78) | 3)
+#define PINMUX_GPIO78__FUNC_DBG_MON_A28 (MTK_PIN_NO(78) | 7)
+
+#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define PINMUX_GPIO79__FUNC_SPIM2_MO (MTK_PIN_NO(79) | 1)
+#define PINMUX_GPIO79__FUNC_PCM0_DO (MTK_PIN_NO(79) | 2)
+#define PINMUX_GPIO79__FUNC_SSUSB_U2SIF_SCL_1P (MTK_PIN_NO(79) | 3)
+#define PINMUX_GPIO79__FUNC_DBG_MON_A29 (MTK_PIN_NO(79) | 7)
+
+#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define PINMUX_GPIO80__FUNC_SPIM2_MI (MTK_PIN_NO(80) | 1)
+#define PINMUX_GPIO80__FUNC_PCM0_DI (MTK_PIN_NO(80) | 2)
+#define PINMUX_GPIO80__FUNC_SSUSB_U2SIF_SDA_1P (MTK_PIN_NO(80) | 3)
+#define PINMUX_GPIO80__FUNC_DBG_MON_A30 (MTK_PIN_NO(80) | 7)
+
+#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define PINMUX_GPIO81__FUNC_IDDIG (MTK_PIN_NO(81) | 1)
+#define PINMUX_GPIO81__FUNC_DBG_MON_B32 (MTK_PIN_NO(81) | 7)
+
+#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define PINMUX_GPIO82__FUNC_USB_DRVVBUS (MTK_PIN_NO(82) | 1)
+
+#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define PINMUX_GPIO83__FUNC_VBUSVALID (MTK_PIN_NO(83) | 1)
+
+#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define PINMUX_GPIO84__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(84) | 1)
+#define PINMUX_GPIO84__FUNC_DBG_MON_A16 (MTK_PIN_NO(84) | 7)
+
+#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
+#define PINMUX_GPIO85__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(85) | 1)
+#define PINMUX_GPIO85__FUNC_DBG_MON_A17 (MTK_PIN_NO(85) | 7)
+
+#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
+#define PINMUX_GPIO86__FUNC_USB_DRVVBUS_3P (MTK_PIN_NO(86) | 1)
+#define PINMUX_GPIO86__FUNC_DBG_MON_A18 (MTK_PIN_NO(86) | 7)
+
+#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
+#define PINMUX_GPIO87__FUNC_USB_DRVVBUS_4P (MTK_PIN_NO(87) | 1)
+#define PINMUX_GPIO87__FUNC_CMVREF4 (MTK_PIN_NO(87) | 6)
+#define PINMUX_GPIO87__FUNC_DBG_MON_A19 (MTK_PIN_NO(87) | 7)
+
+#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
+#define PINMUX_GPIO88__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(88) | 1)
+
+#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
+#define PINMUX_GPIO89__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(89) | 1)
+
+#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
+#define PINMUX_GPIO90__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(90) | 1)
+
+#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
+#define PINMUX_GPIO91__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(91) | 1)
+
+#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
+#define PINMUX_GPIO92__FUNC_SRCLKENA0 (MTK_PIN_NO(92) | 1)
+
+#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
+#define PINMUX_GPIO93__FUNC_SRCLKENA1 (MTK_PIN_NO(93) | 1)
+
+#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
+#define PINMUX_GPIO94__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(94) | 1)
+
+#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define PINMUX_GPIO95__FUNC_RTC32K_CK (MTK_PIN_NO(95) | 1)
+
+#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define PINMUX_GPIO96__FUNC_WATCHDOG (MTK_PIN_NO(96) | 1)
+
+#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define PINMUX_GPIO97__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(97) | 1)
+
+#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define PINMUX_GPIO98__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(98) | 1)
+
+#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define PINMUX_GPIO99__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(99) | 1)
+
+#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define PINMUX_GPIO100__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(100) | 1)
+
+#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define PINMUX_GPIO101__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(101) | 1)
+
+#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define PINMUX_GPIO102__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(102) | 1)
+
+#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define PINMUX_GPIO103__FUNC_I2SIN0_MCK (MTK_PIN_NO(103) | 1)
+#define PINMUX_GPIO103__FUNC_SPIM3_B_CSB (MTK_PIN_NO(103) | 2)
+#define PINMUX_GPIO103__FUNC_APU_JTAG_TMS (MTK_PIN_NO(103) | 3)
+#define PINMUX_GPIO103__FUNC_SCP_JTAG0_TMS_VCORE (MTK_PIN_NO(103) | 4)
+#define PINMUX_GPIO103__FUNC_CONN_WF_MCU_TMS (MTK_PIN_NO(103) | 5)
+#define PINMUX_GPIO103__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(103) | 6)
+#define PINMUX_GPIO103__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(103) | 7)
+
+#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define PINMUX_GPIO104__FUNC_I2SIN0_BCK (MTK_PIN_NO(104) | 1)
+#define PINMUX_GPIO104__FUNC_SPIM3_B_CLK (MTK_PIN_NO(104) | 2)
+#define PINMUX_GPIO104__FUNC_APU_JTAG_TCK (MTK_PIN_NO(104) | 3)
+#define PINMUX_GPIO104__FUNC_SCP_JTAG0_TCK_VCORE (MTK_PIN_NO(104) | 4)
+#define PINMUX_GPIO104__FUNC_CONN_WF_MCU_TCK (MTK_PIN_NO(104) | 5)
+#define PINMUX_GPIO104__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(104) | 6)
+#define PINMUX_GPIO104__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(104) | 7)
+
+#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define PINMUX_GPIO105__FUNC_I2SIN0_LRCK (MTK_PIN_NO(105) | 1)
+#define PINMUX_GPIO105__FUNC_SPIM3_B_MO (MTK_PIN_NO(105) | 2)
+#define PINMUX_GPIO105__FUNC_APU_JTAG_TDI (MTK_PIN_NO(105) | 3)
+#define PINMUX_GPIO105__FUNC_SCP_JTAG0_TDI_VCORE (MTK_PIN_NO(105) | 4)
+#define PINMUX_GPIO105__FUNC_CONN_WF_MCU_TDI (MTK_PIN_NO(105) | 5)
+#define PINMUX_GPIO105__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(105) | 6)
+#define PINMUX_GPIO105__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(105) | 7)
+
+#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define PINMUX_GPIO106__FUNC_I2SIN0_DI (MTK_PIN_NO(106) | 1)
+#define PINMUX_GPIO106__FUNC_SPIM3_B_MI (MTK_PIN_NO(106) | 2)
+#define PINMUX_GPIO106__FUNC_APU_JTAG_TDO (MTK_PIN_NO(106) | 3)
+#define PINMUX_GPIO106__FUNC_SCP_JTAG0_TDO_VCORE (MTK_PIN_NO(106) | 4)
+#define PINMUX_GPIO106__FUNC_CONN_WF_MCU_TDO (MTK_PIN_NO(106) | 5)
+#define PINMUX_GPIO106__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(106) | 6)
+#define PINMUX_GPIO106__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(106) | 7)
+
+#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define PINMUX_GPIO107__FUNC_I2SOUT0_MCK (MTK_PIN_NO(107) | 1)
+#define PINMUX_GPIO107__FUNC_SPIM4_B_CSB (MTK_PIN_NO(107) | 2)
+#define PINMUX_GPIO107__FUNC_APU_JTAG_TRST (MTK_PIN_NO(107) | 3)
+#define PINMUX_GPIO107__FUNC_SCP_JTAG0_TRSTN_VCORE (MTK_PIN_NO(107) | 4)
+#define PINMUX_GPIO107__FUNC_CONN_WF_MCU_TRST_B (MTK_PIN_NO(107) | 5)
+#define PINMUX_GPIO107__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(107) | 6)
+#define PINMUX_GPIO107__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(107) | 7)
+
+#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define PINMUX_GPIO108__FUNC_I2SOUT0_BCK (MTK_PIN_NO(108) | 1)
+#define PINMUX_GPIO108__FUNC_SPIM4_B_CLK (MTK_PIN_NO(108) | 2)
+#define PINMUX_GPIO108__FUNC_EXTIF0_ACT (MTK_PIN_NO(108) | 3)
+#define PINMUX_GPIO108__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(108) | 4)
+#define PINMUX_GPIO108__FUNC_CLKM2 (MTK_PIN_NO(108) | 6)
+#define PINMUX_GPIO108__FUNC_DBG_MON_A20 (MTK_PIN_NO(108) | 7)
+
+#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define PINMUX_GPIO109__FUNC_I2SOUT0_LRCK (MTK_PIN_NO(109) | 1)
+#define PINMUX_GPIO109__FUNC_SPIM4_B_MO (MTK_PIN_NO(109) | 2)
+#define PINMUX_GPIO109__FUNC_EXTIF0_PRI (MTK_PIN_NO(109) | 3)
+#define PINMUX_GPIO109__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(109) | 4)
+#define PINMUX_GPIO109__FUNC_CLKM3 (MTK_PIN_NO(109) | 6)
+#define PINMUX_GPIO109__FUNC_DBG_MON_A21 (MTK_PIN_NO(109) | 7)
+
+#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define PINMUX_GPIO110__FUNC_I2SOUT0_DO (MTK_PIN_NO(110) | 1)
+#define PINMUX_GPIO110__FUNC_SPIM4_B_MI (MTK_PIN_NO(110) | 2)
+#define PINMUX_GPIO110__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(110) | 3)
+#define PINMUX_GPIO110__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(110) | 4)
+#define PINMUX_GPIO110__FUNC_DBG_MON_A22 (MTK_PIN_NO(110) | 7)
+
+#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define PINMUX_GPIO111__FUNC_DMIC0_CLK (MTK_PIN_NO(111) | 1)
+#define PINMUX_GPIO111__FUNC_I2SIN1_MCK (MTK_PIN_NO(111) | 2)
+#define PINMUX_GPIO111__FUNC_I2SOUT1_MCK (MTK_PIN_NO(111) | 3)
+#define PINMUX_GPIO111__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(111) | 4)
+#define PINMUX_GPIO111__FUNC_CONN_MIPI0_SDATA (MTK_PIN_NO(111) | 6)
+#define PINMUX_GPIO111__FUNC_DBG_MON_A23 (MTK_PIN_NO(111) | 7)
+
+#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define PINMUX_GPIO112__FUNC_DMIC0_DAT0 (MTK_PIN_NO(112) | 1)
+#define PINMUX_GPIO112__FUNC_I2SIN1_BCK (MTK_PIN_NO(112) | 2)
+#define PINMUX_GPIO112__FUNC_I2SOUT1_BCK (MTK_PIN_NO(112) | 3)
+#define PINMUX_GPIO112__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(112) | 4)
+#define PINMUX_GPIO112__FUNC_CONN_MIPI0_SCLK (MTK_PIN_NO(112) | 6)
+#define PINMUX_GPIO112__FUNC_DBG_MON_A24 (MTK_PIN_NO(112) | 7)
+
+#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define PINMUX_GPIO113__FUNC_DMIC1_CLK (MTK_PIN_NO(113) | 1)
+#define PINMUX_GPIO113__FUNC_I2SIN1_LRCK (MTK_PIN_NO(113) | 2)
+#define PINMUX_GPIO113__FUNC_I2SOUT1_LRCK (MTK_PIN_NO(113) | 3)
+#define PINMUX_GPIO113__FUNC_PMSR_SMAP (MTK_PIN_NO(113) | 4)
+#define PINMUX_GPIO113__FUNC_CONN_MIPI1_SDATA (MTK_PIN_NO(113) | 6)
+#define PINMUX_GPIO113__FUNC_DBG_MON_A25 (MTK_PIN_NO(113) | 7)
+
+#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define PINMUX_GPIO114__FUNC_DMIC1_DAT0 (MTK_PIN_NO(114) | 1)
+#define PINMUX_GPIO114__FUNC_I2SIN1_DI (MTK_PIN_NO(114) | 2)
+#define PINMUX_GPIO114__FUNC_I2SOUT1_DO (MTK_PIN_NO(114) | 3)
+#define PINMUX_GPIO114__FUNC_CONN_MIPI1_SCLK (MTK_PIN_NO(114) | 6)
+#define PINMUX_GPIO114__FUNC_DBG_MON_A26 (MTK_PIN_NO(114) | 7)
+
+#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define PINMUX_GPIO115__FUNC_PCM0_CLK (MTK_PIN_NO(115) | 1)
+#define PINMUX_GPIO115__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(115) | 2)
+#define PINMUX_GPIO115__FUNC_PCIE_PHY_I2C_SCL (MTK_PIN_NO(115) | 3)
+#define PINMUX_GPIO115__FUNC_SSUSB_U3PHY_I2C_SCL (MTK_PIN_NO(115) | 4)
+#define PINMUX_GPIO115__FUNC_CMFLASH0 (MTK_PIN_NO(115) | 6)
+#define PINMUX_GPIO115__FUNC_EXTIF0_ACT (MTK_PIN_NO(115) | 7)
+
+#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define PINMUX_GPIO116__FUNC_PCM0_SYNC (MTK_PIN_NO(116) | 1)
+#define PINMUX_GPIO116__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(116) | 2)
+#define PINMUX_GPIO116__FUNC_PCIE_PHY_I2C_SDA (MTK_PIN_NO(116) | 3)
+#define PINMUX_GPIO116__FUNC_SSUSB_U3PHY_I2C_SDA (MTK_PIN_NO(116) | 4)
+#define PINMUX_GPIO116__FUNC_CMFLASH1 (MTK_PIN_NO(116) | 6)
+#define PINMUX_GPIO116__FUNC_EXTIF0_PRI (MTK_PIN_NO(116) | 7)
+
+#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define PINMUX_GPIO117__FUNC_PCM0_DI (MTK_PIN_NO(117) | 1)
+#define PINMUX_GPIO117__FUNC_USB_DRVVBUS_3P (MTK_PIN_NO(117) | 2)
+#define PINMUX_GPIO117__FUNC_DP_TX_HPD (MTK_PIN_NO(117) | 3)
+#define PINMUX_GPIO117__FUNC_SSPXTP_U3PHY_I2C_SCL (MTK_PIN_NO(117) | 4)
+#define PINMUX_GPIO117__FUNC_CMVREF0 (MTK_PIN_NO(117) | 6)
+#define PINMUX_GPIO117__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(117) | 7)
+
+#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define PINMUX_GPIO118__FUNC_PCM0_DO (MTK_PIN_NO(118) | 1)
+#define PINMUX_GPIO118__FUNC_USB_DRVVBUS_4P (MTK_PIN_NO(118) | 2)
+#define PINMUX_GPIO118__FUNC_EDP_TX_HPD (MTK_PIN_NO(118) | 3)
+#define PINMUX_GPIO118__FUNC_SSPXTP_U3PHY_I2C_SDA (MTK_PIN_NO(118) | 4)
+#define PINMUX_GPIO118__FUNC_CMVREF1 (MTK_PIN_NO(118) | 6)
+
+#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define PINMUX_GPIO119__FUNC_GBE_TXD3 (MTK_PIN_NO(119) | 1)
+#define PINMUX_GPIO119__FUNC_DMIC0_CLK (MTK_PIN_NO(119) | 2)
+#define PINMUX_GPIO119__FUNC_LVTS_FOUT (MTK_PIN_NO(119) | 3)
+#define PINMUX_GPIO119__FUNC_CONN_BGF_MCU_TMS (MTK_PIN_NO(119) | 4)
+#define PINMUX_GPIO119__FUNC_UDI_TMS (MTK_PIN_NO(119) | 5)
+#define PINMUX_GPIO119__FUNC_ANT_SEL5 (MTK_PIN_NO(119) | 6)
+#define PINMUX_GPIO119__FUNC_DBG_MON_B0 (MTK_PIN_NO(119) | 7)
+
+#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define PINMUX_GPIO120__FUNC_GBE_TXD2 (MTK_PIN_NO(120) | 1)
+#define PINMUX_GPIO120__FUNC_DMIC0_DAT0 (MTK_PIN_NO(120) | 2)
+#define PINMUX_GPIO120__FUNC_LVTS_SDO (MTK_PIN_NO(120) | 3)
+#define PINMUX_GPIO120__FUNC_CONN_BGF_MCU_TCK (MTK_PIN_NO(120) | 4)
+#define PINMUX_GPIO120__FUNC_UDI_TCK (MTK_PIN_NO(120) | 5)
+#define PINMUX_GPIO120__FUNC_ANT_SEL6 (MTK_PIN_NO(120) | 6)
+#define PINMUX_GPIO120__FUNC_DBG_MON_B1 (MTK_PIN_NO(120) | 7)
+
+#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define PINMUX_GPIO121__FUNC_GBE_TXD1 (MTK_PIN_NO(121) | 1)
+#define PINMUX_GPIO121__FUNC_DMIC0_DAT1 (MTK_PIN_NO(121) | 2)
+#define PINMUX_GPIO121__FUNC_LVTS_26M (MTK_PIN_NO(121) | 3)
+#define PINMUX_GPIO121__FUNC_CONN_BGF_MCU_TDI (MTK_PIN_NO(121) | 4)
+#define PINMUX_GPIO121__FUNC_UDI_TDI (MTK_PIN_NO(121) | 5)
+#define PINMUX_GPIO121__FUNC_ANT_SEL7 (MTK_PIN_NO(121) | 6)
+#define PINMUX_GPIO121__FUNC_DBG_MON_B2 (MTK_PIN_NO(121) | 7)
+
+#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define PINMUX_GPIO122__FUNC_GBE_TXD0 (MTK_PIN_NO(122) | 1)
+#define PINMUX_GPIO122__FUNC_DMIC1_CLK (MTK_PIN_NO(122) | 2)
+#define PINMUX_GPIO122__FUNC_LVTS_SCF (MTK_PIN_NO(122) | 3)
+#define PINMUX_GPIO122__FUNC_CONN_BGF_MCU_TDO (MTK_PIN_NO(122) | 4)
+#define PINMUX_GPIO122__FUNC_UDI_TDO (MTK_PIN_NO(122) | 5)
+#define PINMUX_GPIO122__FUNC_ANT_SEL8 (MTK_PIN_NO(122) | 6)
+#define PINMUX_GPIO122__FUNC_DBG_MON_B3 (MTK_PIN_NO(122) | 7)
+
+#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define PINMUX_GPIO123__FUNC_GBE_RXD3 (MTK_PIN_NO(123) | 1)
+#define PINMUX_GPIO123__FUNC_DMIC1_DAT0 (MTK_PIN_NO(123) | 2)
+#define PINMUX_GPIO123__FUNC_LVTS_SCK (MTK_PIN_NO(123) | 3)
+#define PINMUX_GPIO123__FUNC_CONN_BGF_MCU_TRST_B (MTK_PIN_NO(123) | 4)
+#define PINMUX_GPIO123__FUNC_UDI_NTRST (MTK_PIN_NO(123) | 5)
+#define PINMUX_GPIO123__FUNC_ANT_SEL9 (MTK_PIN_NO(123) | 6)
+#define PINMUX_GPIO123__FUNC_DBG_MON_B4 (MTK_PIN_NO(123) | 7)
+
+#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define PINMUX_GPIO124__FUNC_GBE_RXD2 (MTK_PIN_NO(124) | 1)
+#define PINMUX_GPIO124__FUNC_DMIC1_DAT1 (MTK_PIN_NO(124) | 2)
+#define PINMUX_GPIO124__FUNC_LVTS_SDI (MTK_PIN_NO(124) | 3)
+#define PINMUX_GPIO124__FUNC_CONN_WF_MCU_TMS (MTK_PIN_NO(124) | 4)
+#define PINMUX_GPIO124__FUNC_SCP_JTAG0_TMS_VCORE (MTK_PIN_NO(124) | 5)
+#define PINMUX_GPIO124__FUNC_ANT_SEL10 (MTK_PIN_NO(124) | 6)
+#define PINMUX_GPIO124__FUNC_DBG_MON_B5 (MTK_PIN_NO(124) | 7)
+
+#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define PINMUX_GPIO125__FUNC_GBE_RXD1 (MTK_PIN_NO(125) | 1)
+#define PINMUX_GPIO125__FUNC_CLKM2 (MTK_PIN_NO(125) | 2)
+#define PINMUX_GPIO125__FUNC_CONN_WF_MCU_TCK (MTK_PIN_NO(125) | 4)
+#define PINMUX_GPIO125__FUNC_SCP_JTAG0_TCK_VCORE (MTK_PIN_NO(125) | 5)
+#define PINMUX_GPIO125__FUNC_ANT_SEL11 (MTK_PIN_NO(125) | 6)
+#define PINMUX_GPIO125__FUNC_DBG_MON_B6 (MTK_PIN_NO(125) | 7)
+
+#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define PINMUX_GPIO126__FUNC_GBE_RXD0 (MTK_PIN_NO(126) | 1)
+#define PINMUX_GPIO126__FUNC_CLKM3 (MTK_PIN_NO(126) | 2)
+#define PINMUX_GPIO126__FUNC_CONN_WF_MCU_TDI (MTK_PIN_NO(126) | 4)
+#define PINMUX_GPIO126__FUNC_SCP_JTAG0_TDI_VCORE (MTK_PIN_NO(126) | 5)
+#define PINMUX_GPIO126__FUNC_ANT_SEL12 (MTK_PIN_NO(126) | 6)
+#define PINMUX_GPIO126__FUNC_DBG_MON_B7 (MTK_PIN_NO(126) | 7)
+
+#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
+#define PINMUX_GPIO127__FUNC_GBE_TXC (MTK_PIN_NO(127) | 1)
+#define PINMUX_GPIO127__FUNC_I2SIN1_MCK (MTK_PIN_NO(127) | 2)
+#define PINMUX_GPIO127__FUNC_CONN_WF_MCU_TDO (MTK_PIN_NO(127) | 4)
+#define PINMUX_GPIO127__FUNC_SCP_JTAG0_TDO_VCORE (MTK_PIN_NO(127) | 5)
+#define PINMUX_GPIO127__FUNC_ANT_SEL13 (MTK_PIN_NO(127) | 6)
+#define PINMUX_GPIO127__FUNC_DBG_MON_B8 (MTK_PIN_NO(127) | 7)
+
+#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
+#define PINMUX_GPIO128__FUNC_GBE_RXC (MTK_PIN_NO(128) | 1)
+#define PINMUX_GPIO128__FUNC_I2SIN1_BCK (MTK_PIN_NO(128) | 2)
+#define PINMUX_GPIO128__FUNC_CONN_WF_MCU_TRST_B (MTK_PIN_NO(128) | 4)
+#define PINMUX_GPIO128__FUNC_SCP_JTAG0_TRSTN_VCORE (MTK_PIN_NO(128) | 5)
+#define PINMUX_GPIO128__FUNC_ANT_SEL14 (MTK_PIN_NO(128) | 6)
+#define PINMUX_GPIO128__FUNC_DBG_MON_B9 (MTK_PIN_NO(128) | 7)
+
+#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
+#define PINMUX_GPIO129__FUNC_GBE_RXDV (MTK_PIN_NO(129) | 1)
+#define PINMUX_GPIO129__FUNC_I2SIN1_LRCK (MTK_PIN_NO(129) | 2)
+#define PINMUX_GPIO129__FUNC_CONN_BGF_MCU_AICE_TMSC (MTK_PIN_NO(129) | 4)
+#define PINMUX_GPIO129__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(129) | 5)
+#define PINMUX_GPIO129__FUNC_ANT_SEL15 (MTK_PIN_NO(129) | 6)
+#define PINMUX_GPIO129__FUNC_DBG_MON_B10 (MTK_PIN_NO(129) | 7)
+
+#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
+#define PINMUX_GPIO130__FUNC_GBE_TXEN (MTK_PIN_NO(130) | 1)
+#define PINMUX_GPIO130__FUNC_I2SIN1_DI (MTK_PIN_NO(130) | 2)
+#define PINMUX_GPIO130__FUNC_CONN_BGF_MCU_AICE_TCKC (MTK_PIN_NO(130) | 4)
+#define PINMUX_GPIO130__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(130) | 5)
+#define PINMUX_GPIO130__FUNC_ANT_SEL16 (MTK_PIN_NO(130) | 6)
+#define PINMUX_GPIO130__FUNC_DBG_MON_B11 (MTK_PIN_NO(130) | 7)
+
+#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
+#define PINMUX_GPIO131__FUNC_GBE_MDC (MTK_PIN_NO(131) | 1)
+#define PINMUX_GPIO131__FUNC_CLKM0 (MTK_PIN_NO(131) | 2)
+#define PINMUX_GPIO131__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(131) | 3)
+#define PINMUX_GPIO131__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(131) | 4)
+#define PINMUX_GPIO131__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(131) | 5)
+#define PINMUX_GPIO131__FUNC_ANT_SEL17 (MTK_PIN_NO(131) | 6)
+#define PINMUX_GPIO131__FUNC_DBG_MON_B12 (MTK_PIN_NO(131) | 7)
+
+#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
+#define PINMUX_GPIO132__FUNC_GBE_MDIO (MTK_PIN_NO(132) | 1)
+#define PINMUX_GPIO132__FUNC_CLKM1 (MTK_PIN_NO(132) | 2)
+#define PINMUX_GPIO132__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(132) | 3)
+#define PINMUX_GPIO132__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(132) | 4)
+#define PINMUX_GPIO132__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(132) | 5)
+#define PINMUX_GPIO132__FUNC_ANT_SEL18 (MTK_PIN_NO(132) | 6)
+#define PINMUX_GPIO132__FUNC_DBG_MON_B13 (MTK_PIN_NO(132) | 7)
+
+#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
+#define PINMUX_GPIO133__FUNC_GBE_TXER (MTK_PIN_NO(133) | 1)
+#define PINMUX_GPIO133__FUNC_GBE_AUX_PPS2 (MTK_PIN_NO(133) | 2)
+#define PINMUX_GPIO133__FUNC_CONN_BT_TXD (MTK_PIN_NO(133) | 4)
+#define PINMUX_GPIO133__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(133) | 5)
+#define PINMUX_GPIO133__FUNC_ANT_SEL19 (MTK_PIN_NO(133) | 6)
+#define PINMUX_GPIO133__FUNC_DBG_MON_B14 (MTK_PIN_NO(133) | 7)
+
+#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
+#define PINMUX_GPIO134__FUNC_GBE_RXER (MTK_PIN_NO(134) | 1)
+#define PINMUX_GPIO134__FUNC_GBE_AUX_PPS3 (MTK_PIN_NO(134) | 2)
+#define PINMUX_GPIO134__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(134) | 3)
+#define PINMUX_GPIO134__FUNC_CONN_WF_MCU_AICE_TMSC (MTK_PIN_NO(134) | 4)
+#define PINMUX_GPIO134__FUNC_APU_JTAG_TMS (MTK_PIN_NO(134) | 5)
+#define PINMUX_GPIO134__FUNC_ANT_SEL20 (MTK_PIN_NO(134) | 6)
+#define PINMUX_GPIO134__FUNC_DBG_MON_B15 (MTK_PIN_NO(134) | 7)
+
+#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
+#define PINMUX_GPIO135__FUNC_GBE_COL (MTK_PIN_NO(135) | 1)
+#define PINMUX_GPIO135__FUNC_I2SOUT1_MCK (MTK_PIN_NO(135) | 2)
+#define PINMUX_GPIO135__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(135) | 3)
+#define PINMUX_GPIO135__FUNC_CONN_WF_MCU_AICE_TCKC (MTK_PIN_NO(135) | 4)
+#define PINMUX_GPIO135__FUNC_APU_JTAG_TCK (MTK_PIN_NO(135) | 5)
+#define PINMUX_GPIO135__FUNC_ANT_SEL21 (MTK_PIN_NO(135) | 6)
+#define PINMUX_GPIO135__FUNC_DBG_MON_B16 (MTK_PIN_NO(135) | 7)
+
+#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
+#define PINMUX_GPIO136__FUNC_GBE_INTR (MTK_PIN_NO(136) | 1)
+#define PINMUX_GPIO136__FUNC_I2SOUT1_BCK (MTK_PIN_NO(136) | 2)
+#define PINMUX_GPIO136__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(136) | 3)
+#define PINMUX_GPIO136__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(136) | 4)
+#define PINMUX_GPIO136__FUNC_APU_JTAG_TDI (MTK_PIN_NO(136) | 5)
+#define PINMUX_GPIO136__FUNC_PWM_0 (MTK_PIN_NO(136) | 6)
+#define PINMUX_GPIO136__FUNC_DBG_MON_B17 (MTK_PIN_NO(136) | 7)
+
+#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
+#define PINMUX_GPIO137__FUNC_GBE_AUX_PPS0 (MTK_PIN_NO(137) | 1)
+#define PINMUX_GPIO137__FUNC_I2SOUT1_LRCK (MTK_PIN_NO(137) | 2)
+#define PINMUX_GPIO137__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(137) | 3)
+#define PINMUX_GPIO137__FUNC_DP_TX_HPD (MTK_PIN_NO(137) | 4)
+#define PINMUX_GPIO137__FUNC_APU_JTAG_TDO (MTK_PIN_NO(137) | 5)
+#define PINMUX_GPIO137__FUNC_PWM_1 (MTK_PIN_NO(137) | 6)
+#define PINMUX_GPIO137__FUNC_DBG_MON_B18 (MTK_PIN_NO(137) | 7)
+
+#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
+#define PINMUX_GPIO138__FUNC_GBE_AUX_PPS1 (MTK_PIN_NO(138) | 1)
+#define PINMUX_GPIO138__FUNC_I2SOUT1_DO (MTK_PIN_NO(138) | 2)
+#define PINMUX_GPIO138__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(138) | 3)
+#define PINMUX_GPIO138__FUNC_EDP_TX_HPD (MTK_PIN_NO(138) | 4)
+#define PINMUX_GPIO138__FUNC_APU_JTAG_TRST (MTK_PIN_NO(138) | 5)
+#define PINMUX_GPIO138__FUNC_PWM_2 (MTK_PIN_NO(138) | 6)
+#define PINMUX_GPIO138__FUNC_DBG_MON_B19 (MTK_PIN_NO(138) | 7)
+
+#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
+#define PINMUX_GPIO139__FUNC_CONN_TOP_CLK (MTK_PIN_NO(139) | 1)
+
+#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
+#define PINMUX_GPIO140__FUNC_CONN_TOP_DATA (MTK_PIN_NO(140) | 1)
+
+#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
+#define PINMUX_GPIO141__FUNC_CONN_BT_CLK (MTK_PIN_NO(141) | 1)
+
+#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
+#define PINMUX_GPIO142__FUNC_CONN_BT_DATA (MTK_PIN_NO(142) | 1)
+
+#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
+#define PINMUX_GPIO143__FUNC_CONN_HRST_B (MTK_PIN_NO(143) | 1)
+
+#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
+#define PINMUX_GPIO144__FUNC_CONN_WB_PTA (MTK_PIN_NO(144) | 1)
+
+#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
+#define PINMUX_GPIO145__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(145) | 1)
+
+#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
+#define PINMUX_GPIO146__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(146) | 1)
+
+#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
+#define PINMUX_GPIO147__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(147) | 1)
+
+#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
+#define PINMUX_GPIO148__FUNC_CONN_WF_CTRL3 (MTK_PIN_NO(148) | 1)
+
+#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
+#define PINMUX_GPIO149__FUNC_CONN_WF_CTRL4 (MTK_PIN_NO(149) | 1)
+
+#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
+#define PINMUX_GPIO150__FUNC_SPINOR_CK (MTK_PIN_NO(150) | 1)
+#define PINMUX_GPIO150__FUNC_DMIC0_CLK (MTK_PIN_NO(150) | 2)
+#define PINMUX_GPIO150__FUNC_DP_TX_HPD (MTK_PIN_NO(150) | 3)
+#define PINMUX_GPIO150__FUNC_PWM_0 (MTK_PIN_NO(150) | 4)
+#define PINMUX_GPIO150__FUNC_CONN_BPI_BUS17_ANT0 (MTK_PIN_NO(150) | 5)
+#define PINMUX_GPIO150__FUNC_LVTS_FOUT (MTK_PIN_NO(150) | 6)
+#define PINMUX_GPIO150__FUNC_DBG_MON_B26 (MTK_PIN_NO(150) | 7)
+
+#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
+#define PINMUX_GPIO151__FUNC_SPINOR_CS (MTK_PIN_NO(151) | 1)
+#define PINMUX_GPIO151__FUNC_DMIC0_DAT0 (MTK_PIN_NO(151) | 2)
+#define PINMUX_GPIO151__FUNC_EDP_TX_HPD (MTK_PIN_NO(151) | 3)
+#define PINMUX_GPIO151__FUNC_PWM_1 (MTK_PIN_NO(151) | 4)
+#define PINMUX_GPIO151__FUNC_CONN_BPI_BUS18_ANT1 (MTK_PIN_NO(151) | 5)
+#define PINMUX_GPIO151__FUNC_LVTS_SDO (MTK_PIN_NO(151) | 6)
+#define PINMUX_GPIO151__FUNC_DBG_MON_B27 (MTK_PIN_NO(151) | 7)
+
+#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
+#define PINMUX_GPIO152__FUNC_SPINOR_IO0 (MTK_PIN_NO(152) | 1)
+#define PINMUX_GPIO152__FUNC_DMIC0_DAT1 (MTK_PIN_NO(152) | 2)
+#define PINMUX_GPIO152__FUNC_UTXD2 (MTK_PIN_NO(152) | 3)
+#define PINMUX_GPIO152__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(152) | 4)
+#define PINMUX_GPIO152__FUNC_CONN_BPI_BUS19_ANT2 (MTK_PIN_NO(152) | 5)
+#define PINMUX_GPIO152__FUNC_LVTS_26M (MTK_PIN_NO(152) | 6)
+#define PINMUX_GPIO152__FUNC_DBG_MON_B28 (MTK_PIN_NO(152) | 7)
+
+#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
+#define PINMUX_GPIO153__FUNC_SPINOR_IO1 (MTK_PIN_NO(153) | 1)
+#define PINMUX_GPIO153__FUNC_DMIC1_CLK (MTK_PIN_NO(153) | 2)
+#define PINMUX_GPIO153__FUNC_UCTS2 (MTK_PIN_NO(153) | 3)
+#define PINMUX_GPIO153__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(153) | 4)
+#define PINMUX_GPIO153__FUNC_CONN_BPI_BUS20_ANT3 (MTK_PIN_NO(153) | 5)
+#define PINMUX_GPIO153__FUNC_LVTS_SCF (MTK_PIN_NO(153) | 6)
+#define PINMUX_GPIO153__FUNC_DBG_MON_B29 (MTK_PIN_NO(153) | 7)
+
+#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
+#define PINMUX_GPIO154__FUNC_SPINOR_IO2 (MTK_PIN_NO(154) | 1)
+#define PINMUX_GPIO154__FUNC_DMIC1_DAT0 (MTK_PIN_NO(154) | 2)
+#define PINMUX_GPIO154__FUNC_URTS2 (MTK_PIN_NO(154) | 3)
+#define PINMUX_GPIO154__FUNC_USB_DRVVBUS_3P (MTK_PIN_NO(154) | 4)
+#define PINMUX_GPIO154__FUNC_CONN_BPI_BUS21_ANT4 (MTK_PIN_NO(154) | 5)
+#define PINMUX_GPIO154__FUNC_LVTS_SCK (MTK_PIN_NO(154) | 6)
+#define PINMUX_GPIO154__FUNC_DBG_MON_B30 (MTK_PIN_NO(154) | 7)
+
+#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
+#define PINMUX_GPIO155__FUNC_SPINOR_IO3 (MTK_PIN_NO(155) | 1)
+#define PINMUX_GPIO155__FUNC_DMIC1_DAT1 (MTK_PIN_NO(155) | 2)
+#define PINMUX_GPIO155__FUNC_URXD2 (MTK_PIN_NO(155) | 3)
+#define PINMUX_GPIO155__FUNC_USB_DRVVBUS_4P (MTK_PIN_NO(155) | 4)
+#define PINMUX_GPIO155__FUNC_DISP_PWM1 (MTK_PIN_NO(155) | 5)
+#define PINMUX_GPIO155__FUNC_LVTS_SDI (MTK_PIN_NO(155) | 6)
+#define PINMUX_GPIO155__FUNC_DBG_MON_B31 (MTK_PIN_NO(155) | 7)
+
+#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
+#define PINMUX_GPIO156__FUNC_MSDC0_DAT7 (MTK_PIN_NO(156) | 1)
+
+#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
+#define PINMUX_GPIO157__FUNC_MSDC0_DAT6 (MTK_PIN_NO(157) | 1)
+
+#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
+#define PINMUX_GPIO158__FUNC_MSDC0_DAT5 (MTK_PIN_NO(158) | 1)
+
+#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
+#define PINMUX_GPIO159__FUNC_MSDC0_DAT4 (MTK_PIN_NO(159) | 1)
+
+#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
+#define PINMUX_GPIO160__FUNC_MSDC0_RSTB (MTK_PIN_NO(160) | 1)
+
+#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
+#define PINMUX_GPIO161__FUNC_MSDC0_CMD (MTK_PIN_NO(161) | 1)
+
+#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
+#define PINMUX_GPIO162__FUNC_MSDC0_CLK (MTK_PIN_NO(162) | 1)
+
+#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
+#define PINMUX_GPIO163__FUNC_MSDC0_DAT3 (MTK_PIN_NO(163) | 1)
+
+#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
+#define PINMUX_GPIO164__FUNC_MSDC0_DAT2 (MTK_PIN_NO(164) | 1)
+
+#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
+#define PINMUX_GPIO165__FUNC_MSDC0_DAT1 (MTK_PIN_NO(165) | 1)
+
+#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
+#define PINMUX_GPIO166__FUNC_MSDC0_DAT0 (MTK_PIN_NO(166) | 1)
+
+#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
+#define PINMUX_GPIO167__FUNC_MSDC0_DSL (MTK_PIN_NO(167) | 1)
+
+#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
+#define PINMUX_GPIO168__FUNC_MSDC1_CMD (MTK_PIN_NO(168) | 1)
+#define PINMUX_GPIO168__FUNC_CONN_WF_MCU_AICE_TMSC (MTK_PIN_NO(168) | 2)
+#define PINMUX_GPIO168__FUNC_UCTS1 (MTK_PIN_NO(168) | 3)
+#define PINMUX_GPIO168__FUNC_UDI_TMS (MTK_PIN_NO(168) | 4)
+#define PINMUX_GPIO168__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(168) | 5)
+#define PINMUX_GPIO168__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(168) | 6)
+#define PINMUX_GPIO168__FUNC_CONN_BGF_MCU_TMS (MTK_PIN_NO(168) | 7)
+
+#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
+#define PINMUX_GPIO169__FUNC_MSDC1_CLK (MTK_PIN_NO(169) | 1)
+#define PINMUX_GPIO169__FUNC_CONN_WF_MCU_AICE_TCKC (MTK_PIN_NO(169) | 2)
+#define PINMUX_GPIO169__FUNC_URTS1 (MTK_PIN_NO(169) | 3)
+#define PINMUX_GPIO169__FUNC_UDI_TCK (MTK_PIN_NO(169) | 4)
+#define PINMUX_GPIO169__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(169) | 5)
+#define PINMUX_GPIO169__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(169) | 6)
+#define PINMUX_GPIO169__FUNC_CONN_BGF_MCU_TCK (MTK_PIN_NO(169) | 7)
+
+#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
+#define PINMUX_GPIO170__FUNC_MSDC1_DAT0 (MTK_PIN_NO(170) | 1)
+#define PINMUX_GPIO170__FUNC_SPIM5_B_CSB (MTK_PIN_NO(170) | 2)
+#define PINMUX_GPIO170__FUNC_UCTS2 (MTK_PIN_NO(170) | 3)
+#define PINMUX_GPIO170__FUNC_UDI_TDI (MTK_PIN_NO(170) | 4)
+#define PINMUX_GPIO170__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(170) | 5)
+#define PINMUX_GPIO170__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(170) | 6)
+#define PINMUX_GPIO170__FUNC_CONN_BGF_MCU_TDI (MTK_PIN_NO(170) | 7)
+
+#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
+#define PINMUX_GPIO171__FUNC_MSDC1_DAT1 (MTK_PIN_NO(171) | 1)
+#define PINMUX_GPIO171__FUNC_SPIM5_B_CLK (MTK_PIN_NO(171) | 2)
+#define PINMUX_GPIO171__FUNC_URTS2 (MTK_PIN_NO(171) | 3)
+#define PINMUX_GPIO171__FUNC_UDI_TDO (MTK_PIN_NO(171) | 4)
+#define PINMUX_GPIO171__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(171) | 5)
+#define PINMUX_GPIO171__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(171) | 6)
+#define PINMUX_GPIO171__FUNC_CONN_BGF_MCU_TDO (MTK_PIN_NO(171) | 7)
+
+#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
+#define PINMUX_GPIO172__FUNC_MSDC1_DAT2 (MTK_PIN_NO(172) | 1)
+#define PINMUX_GPIO172__FUNC_SPIM5_B_MO (MTK_PIN_NO(172) | 2)
+#define PINMUX_GPIO172__FUNC_UCTS3 (MTK_PIN_NO(172) | 3)
+#define PINMUX_GPIO172__FUNC_UDI_NTRST (MTK_PIN_NO(172) | 4)
+#define PINMUX_GPIO172__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(172) | 5)
+#define PINMUX_GPIO172__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(172) | 6)
+#define PINMUX_GPIO172__FUNC_CONN_BGF_MCU_TRST_B (MTK_PIN_NO(172) | 7)
+
+#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
+#define PINMUX_GPIO173__FUNC_MSDC1_DAT3 (MTK_PIN_NO(173) | 1)
+#define PINMUX_GPIO173__FUNC_SPIM5_B_MI (MTK_PIN_NO(173) | 2)
+#define PINMUX_GPIO173__FUNC_URTS3 (MTK_PIN_NO(173) | 3)
+#define PINMUX_GPIO173__FUNC_CLKM0 (MTK_PIN_NO(173) | 4)
+#define PINMUX_GPIO173__FUNC_PWM_2 (MTK_PIN_NO(173) | 5)
+
+#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
+#define PINMUX_GPIO174__FUNC_MSDC2_CMD (MTK_PIN_NO(174) | 1)
+#define PINMUX_GPIO174__FUNC_CONN_BGF_MCU_AICE_TMSC (MTK_PIN_NO(174) | 2)
+#define PINMUX_GPIO174__FUNC_UTXD1 (MTK_PIN_NO(174) | 3)
+#define PINMUX_GPIO174__FUNC_VADSP_JTAG0_TMS (MTK_PIN_NO(174) | 4)
+#define PINMUX_GPIO174__FUNC_SSPM_JTAG_TMS_VLP (MTK_PIN_NO(174) | 5)
+#define PINMUX_GPIO174__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(174) | 6)
+#define PINMUX_GPIO174__FUNC_SCP_JTAG0_TMS_VLP (MTK_PIN_NO(174) | 7)
+
+#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
+#define PINMUX_GPIO175__FUNC_MSDC2_CLK (MTK_PIN_NO(175) | 1)
+#define PINMUX_GPIO175__FUNC_CONN_BGF_MCU_AICE_TCKC (MTK_PIN_NO(175) | 2)
+#define PINMUX_GPIO175__FUNC_URXD1 (MTK_PIN_NO(175) | 3)
+#define PINMUX_GPIO175__FUNC_VADSP_JTAG0_TCK (MTK_PIN_NO(175) | 4)
+#define PINMUX_GPIO175__FUNC_SSPM_JTAG_TCK_VLP (MTK_PIN_NO(175) | 5)
+#define PINMUX_GPIO175__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(175) | 6)
+#define PINMUX_GPIO175__FUNC_SCP_JTAG0_TCK_VLP (MTK_PIN_NO(175) | 7)
+
+#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
+#define PINMUX_GPIO176__FUNC_MSDC2_DAT0 (MTK_PIN_NO(176) | 1)
+#define PINMUX_GPIO176__FUNC_SRCLKENAI0 (MTK_PIN_NO(176) | 2)
+#define PINMUX_GPIO176__FUNC_UTXD2 (MTK_PIN_NO(176) | 3)
+#define PINMUX_GPIO176__FUNC_VADSP_JTAG0_TDI (MTK_PIN_NO(176) | 4)
+#define PINMUX_GPIO176__FUNC_SSPM_JTAG_TDI_VLP (MTK_PIN_NO(176) | 5)
+#define PINMUX_GPIO176__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(176) | 6)
+#define PINMUX_GPIO176__FUNC_SCP_JTAG0_TDI_VLP (MTK_PIN_NO(176) | 7)
+
+#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
+#define PINMUX_GPIO177__FUNC_MSDC2_DAT1 (MTK_PIN_NO(177) | 1)
+#define PINMUX_GPIO177__FUNC_SRCLKENAI1 (MTK_PIN_NO(177) | 2)
+#define PINMUX_GPIO177__FUNC_URXD2 (MTK_PIN_NO(177) | 3)
+#define PINMUX_GPIO177__FUNC_VADSP_JTAG0_TDO (MTK_PIN_NO(177) | 4)
+#define PINMUX_GPIO177__FUNC_SSPM_JTAG_TDO_VLP (MTK_PIN_NO(177) | 5)
+#define PINMUX_GPIO177__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(177) | 6)
+#define PINMUX_GPIO177__FUNC_SCP_JTAG0_TDO_VLP (MTK_PIN_NO(177) | 7)
+
+#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
+#define PINMUX_GPIO178__FUNC_MSDC2_DAT2 (MTK_PIN_NO(178) | 1)
+#define PINMUX_GPIO178__FUNC_UTXD3 (MTK_PIN_NO(178) | 3)
+#define PINMUX_GPIO178__FUNC_VADSP_JTAG0_TRSTN (MTK_PIN_NO(178) | 4)
+#define PINMUX_GPIO178__FUNC_SSPM_JTAG_TRSTN_VLP (MTK_PIN_NO(178) | 5)
+#define PINMUX_GPIO178__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(178) | 6)
+#define PINMUX_GPIO178__FUNC_SCP_JTAG0_TRSTN_VLP (MTK_PIN_NO(178) | 7)
+
+#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
+#define PINMUX_GPIO179__FUNC_MSDC2_DAT3 (MTK_PIN_NO(179) | 1)
+#define PINMUX_GPIO179__FUNC_URXD3 (MTK_PIN_NO(179) | 3)
+#define PINMUX_GPIO179__FUNC_CLKM1 (MTK_PIN_NO(179) | 4)
+#define PINMUX_GPIO179__FUNC_PWM_vlp (MTK_PIN_NO(179) | 5)
+#define PINMUX_GPIO179__FUNC_TP_GPIO7_AO (MTK_PIN_NO(179) | 7)
+
+#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0)
+#define PINMUX_GPIO180__FUNC_SPMI_P_SCL (MTK_PIN_NO(180) | 1)
+
+#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0)
+#define PINMUX_GPIO181__FUNC_SPMI_P_SDA (MTK_PIN_NO(181) | 1)
+
+#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0)
+#define PINMUX_GPIO182__FUNC_DDR_PAD_RRESETB (MTK_PIN_NO(182) | 1)
+
+#endif /* __MT8189_PINFUNC_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 4/6] arm: dts: mediatek: Add MediaTek MT8189 dtsi file
2026-03-23 20:16 [PATCH v3 0/6] boards: mediatek: initial support for Genio 720 EVK David Lechner
` (2 preceding siblings ...)
2026-03-23 20:16 ` [PATCH v3 3/6] arm: dts: mediatek: mt8189: Add pinmux macro header file David Lechner
@ 2026-03-23 20:16 ` David Lechner
2026-03-23 20:16 ` [PATCH v3 5/6] arm: dts: mediatek: Add MediaTek Genio 520/720 EVK DTS David Lechner
` (2 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: David Lechner @ 2026-03-23 20:16 UTC (permalink / raw)
To: Tom Rini, Ryder Lee, Weijie Gao, Chunfeng Yun, Igor Belwon,
GSS_MTK_Uboot_upstream, Macpaul Lin, Lukasz Majewski
Cc: Julien Stephan, u-boot, David Lechner, Chris-QJ Chen
From: Chris-QJ Chen <chris-qj.chen@mediatek.com>
Add a basic .dtsi file for MediaTek MT8189. This will suffice until an
upstream devicetree is available from Linux.
Signed-off-by: Chris-QJ Chen <chris-qj.chen@mediatek.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
arch/arm/dts/mt8189.dtsi | 301 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 301 insertions(+)
diff --git a/arch/arm/dts/mt8189.dtsi b/arch/arm/dts/mt8189.dtsi
new file mode 100644
index 00000000000..3aafb9b151f
--- /dev/null
+++ b/arch/arm/dts/mt8189.dtsi
@@ -0,0 +1,301 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2026 MediaTek Inc.
+ * Author: Macpaul Lin <macpaul.lin@mediatek.com>
+ */
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "mediatek,mt8189";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ clk26m: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x000>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <282>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <282>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <282>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <282>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x400>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <282>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x500>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <282>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x600>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x700>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+
+ core4 {
+ cpu = <&cpu4>;
+ };
+
+ core5 {
+ cpu = <&cpu5>;
+ };
+
+ core6 {
+ cpu = <&cpu6>;
+ };
+
+ core7 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+ };
+
+ memory: memory@40000000 {
+ device_type = "memory";
+ /* This memory size is filled in by the bootloader */
+ reg = <0 0x40000000 0 0>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ watchdog: watchdog@1c00a000 {
+ compatible = "mediatek,mt8391-wdt",
+ "mediatek,wdt";
+ reg = <0 0x1c00a000 0 0x100>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ reg = <0 0xc000000 0 0x40000>, /* distributor */
+ <0 0xc040000 0 0x200000>; /* redistributor */
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ #redistributor-regions = <1>;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu6 &cpu7>;
+ };
+ };
+ };
+
+ uart0: serial@11001000 {
+ compatible = "mediatek,mt8189-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11001000 0 0x1000>;
+ interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&pericfg_ao_clk CLK_PERAO_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8189-mmc";
+ reg = <0 0x11230000 0 0x10000>,
+ <0 0x11e70000 0 0x1000>;
+ clocks = <&topckgen_clk CLK_TOP_MSDC50_0_SEL>,
+ <&pericfg_ao_clk CLK_PERAO_MSDC0_H>,
+ <&pericfg_ao_clk CLK_PERAO_MSDC0>;
+ clock-names = "source", "hclk", "source_cg";
+ interrupts = <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
+ clock-controller@1000c000 {
+ compatible = "mediatek,mt8189-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clock-controller@14000000 {
+ compatible = "mediatek,mt8189-dispsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clock-controller@1e980000 {
+ compatible = "mediatek,mt8189-gce-d", "syscon";
+ reg = <0 0x1e980000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clock-controller@1e990000 {
+ compatible = "mediatek,mt8189-gce-m", "syscon";
+ reg = <0 0x1e990000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clock-controller@1e800000 {
+ compatible = "mediatek,mt8189-mm-infra", "syscon";
+ reg = <0 0x1e800000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pericfg_ao_clk: clock-controller@11036000 {
+ compatible = "mediatek,mt8189-peri-ao", "syscon";
+ reg = <0 0x11036000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ topckgen_clk: clock-controller@10000000 {
+ compatible = "mediatek,mt8189-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt8189-pinctrl";
+ reg = <0 0x10005000 0 0x1000>,
+ <0 0x11b50000 0 0x1000>,
+ <0 0x11c50000 0 0x1000>,
+ <0 0x11c60000 0 0x1000>,
+ <0 0x11d20000 0 0x1000>,
+ <0 0x11d30000 0 0x1000>,
+ <0 0x11d40000 0 0x1000>,
+ <0 0x11e20000 0 0x1000>,
+ <0 0x11e30000 0 0x1000>,
+ <0 0x11f20000 0 0x1000>,
+ <0 0x11ce0000 0 0x1000>,
+ <0 0x11de0000 0 0x1000>,
+ <0 0x11e60000 0 0x1000>,
+ <0 0x1c01e000 0 0x1000>,
+ <0 0x11f00000 0 0x1000>;
+ reg-names = "base",
+ "lm",
+ "rb0",
+ "rb1",
+ "bm0",
+ "bm1",
+ "bm2",
+ "lt0",
+ "lt1",
+ "rt",
+ "eint0",
+ "eint1",
+ "eint2",
+ "eint3",
+ "eint4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 182>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
+ #interrupt-cells = <2>;
+ };
+
+ pwrap: pwrap@1cc04000 {
+ compatible = "mediatek,mt8189-pwrap", "mediatek,mt8195-pwrap", "syscon";
+ reg = <0 0x1cc04000 0 0x1000>;
+ reg-names = "pwrap";
+ assigned-clocks = <&vlpckgen_clk CLK_VLP_CK_PWRAP_ULPOSC_SEL>;
+ assigned-clock-parents = <&topckgen_clk CLK_TOP_OSC_D10>;
+ clocks = <&vlpcfg_ao_clk CLK_VLPCFG_REG_PMIF_SPMI_M_SYS>,
+ <&vlpcfg_ao_clk CLK_VLPCFG_REG_PMIF_SPMI_M_TMR>;
+ clock-names = "spi", "wrap";
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ vlpcfg_ao_clk: clock-controller@1c00c000 {
+ compatible = "mediatek,mt8189-vlpcfg-ao", "syscon";
+ reg = <0 0x1c00c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vlpckgen_clk: clock-controller@1c012000 {
+ compatible = "mediatek,mt8189-vlpckgen", "syscon";
+ reg = <0 0x1c012000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 5/6] arm: dts: mediatek: Add MediaTek Genio 520/720 EVK DTS
2026-03-23 20:16 [PATCH v3 0/6] boards: mediatek: initial support for Genio 720 EVK David Lechner
` (3 preceding siblings ...)
2026-03-23 20:16 ` [PATCH v3 4/6] arm: dts: mediatek: Add MediaTek MT8189 dtsi file David Lechner
@ 2026-03-23 20:16 ` David Lechner
2026-03-23 20:16 ` [PATCH v3 6/6] board: mediatek: Add Genio 520/720 EVK defconfigs David Lechner
2026-04-07 16:01 ` [PATCH v3 0/6] boards: mediatek: initial support for Genio 720 EVK David Lechner
6 siblings, 0 replies; 15+ messages in thread
From: David Lechner @ 2026-03-23 20:16 UTC (permalink / raw)
To: Tom Rini, Ryder Lee, Weijie Gao, Chunfeng Yun, Igor Belwon,
GSS_MTK_Uboot_upstream, Macpaul Lin, Lukasz Majewski
Cc: Julien Stephan, u-boot, David Lechner, Chris-QJ Chen
From: Chris-QJ Chen <chris-qj.chen@mediatek.com>
Add a basic .dts file for MediaTek Genio 520/720 EVKs. This will suffice
until an upstream devicetree is available from Linux.
These boards are virtually identical (other than some camera
capabilities) so share mostly the same devicetree.
Signed-off-by: Chris-QJ Chen <chris-qj.chen@mediatek.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/mt8371-genio-520-evk.dts | 11 +++
arch/arm/dts/mt8371-genio-common.dtsi | 176 ++++++++++++++++++++++++++++++++++
arch/arm/dts/mt8391-genio-720-evk.dts | 11 +++
4 files changed, 200 insertions(+)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d90e02ca4e5..4085d4c2de1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1124,6 +1124,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7988-rfb.dtb \
mt7988-sd-rfb.dtb \
mt8183-pumpkin.dtb \
+ mt8371-genio-520-evk.dtb \
+ mt8391-genio-720-evk.dtb \
mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
diff --git a/arch/arm/dts/mt8371-genio-520-evk.dts b/arch/arm/dts/mt8371-genio-520-evk.dts
new file mode 100644
index 00000000000..1ed325eb587
--- /dev/null
+++ b/arch/arm/dts/mt8371-genio-520-evk.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "mt8189.dtsi"
+#include "mt8371-genio-common.dtsi"
+
+/ {
+ model = "MediaTek Genio-520 EVK";
+ compatible = "mediatek,mt8371-evk", "mediatek,mt8371", "mediatek,mt8189";
+};
diff --git a/arch/arm/dts/mt8371-genio-common.dtsi b/arch/arm/dts/mt8371-genio-common.dtsi
new file mode 100644
index 00000000000..c6aa22b7d10
--- /dev/null
+++ b/arch/arm/dts/mt8371-genio-common.dtsi
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2026 MediaTek Inc.
+ * Author: Macpaul Lin <macpaul.lin@mediatek.com>
+ */
+
+#include "mt8189.dtsi"
+#include "mt8189-pinfunc.h"
+#include "mt6359.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+ memory@40000000 {
+ /* 8GB */
+ device_type = "memory";
+ reg = <0 0x40000000 0x2 0x00000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@54600000 {
+ no-map;
+ reg = <0 0x54600000 0x0 0x200000>;
+ };
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee@43200000 {
+ no-map;
+ reg = <0 0x43200000 0 0x00c00000>;
+ };
+
+ dsi_reserved: dsi@60000000 {
+ reg = <0 0x60000000 0 0x02000000>;
+ no-map;
+ };
+ };
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ hs400-ds-delay = <0x1481b>;
+ cap-mmc-hw-reset;
+ vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+ vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+ non-removable;
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_default_pins>;
+ pinctrl-1 = <&mmc0_uhs_pins>;
+ status = "okay";
+};
+
+&mt6359_vufs_ldo_reg {
+ regulator-always-on;
+};
+
+&pio {
+ mmc0_default_pins: mmc0-default-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO162__FUNC_MSDC0_CLK>;
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO166__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO165__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO164__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO163__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO159__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO158__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO157__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO156__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO161__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO160__FUNC_MSDC0_RSTB>;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
+ };
+ };
+
+ mmc0_uhs_pins: mmc0-uhs-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO162__FUNC_MSDC0_CLK>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO166__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO165__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO164__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO163__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO159__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO158__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO157__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO156__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO161__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-ds {
+ pinmux = <PINMUX_GPIO167__FUNC_MSDC0_DSL>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO160__FUNC_MSDC0_RSTB>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO31__FUNC_UTXD0>,
+ <PINMUX_GPIO32__FUNC_URXD0>;
+ bias-pull-up;
+ };
+ };
+};
+
+&pmic {
+ interrupts-extended = <&pio 194 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/arch/arm/dts/mt8391-genio-720-evk.dts b/arch/arm/dts/mt8391-genio-720-evk.dts
new file mode 100644
index 00000000000..c8e57433ce6
--- /dev/null
+++ b/arch/arm/dts/mt8391-genio-720-evk.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "mt8189.dtsi"
+#include "mt8371-genio-common.dtsi"
+
+/ {
+ model = "MediaTek Genio-720 EVK";
+ compatible = "mediatek,mt8391-evk", "mediatek,mt8391", "mediatek,mt8189";
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 6/6] board: mediatek: Add Genio 520/720 EVK defconfigs
2026-03-23 20:16 [PATCH v3 0/6] boards: mediatek: initial support for Genio 720 EVK David Lechner
` (4 preceding siblings ...)
2026-03-23 20:16 ` [PATCH v3 5/6] arm: dts: mediatek: Add MediaTek Genio 520/720 EVK DTS David Lechner
@ 2026-03-23 20:16 ` David Lechner
2026-03-30 15:21 ` Julien Stephan
2026-04-07 16:01 ` [PATCH v3 0/6] boards: mediatek: initial support for Genio 720 EVK David Lechner
6 siblings, 1 reply; 15+ messages in thread
From: David Lechner @ 2026-03-23 20:16 UTC (permalink / raw)
To: Tom Rini, Ryder Lee, Weijie Gao, Chunfeng Yun, Igor Belwon,
GSS_MTK_Uboot_upstream, Macpaul Lin, Lukasz Majewski
Cc: Julien Stephan, u-boot, David Lechner, Chris-QJ Chen
From: Chris-QJ Chen <chris-qj.chen@mediatek.com>
Add basic defconfigs for Genio 520 and 720 EVKs.
Signed-off-by: Chris-QJ Chen <chris-qj.chen@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
board/mediatek/MAINTAINERS | 7 +++++++
configs/mt8189.config | 34 ++++++++++++++++++++++++++++++++++
configs/mt8371_genio_520_evk_defconfig | 4 ++++
configs/mt8391_genio_720_evk_defconfig | 4 ++++
4 files changed, 49 insertions(+)
diff --git a/board/mediatek/MAINTAINERS b/board/mediatek/MAINTAINERS
index 446a9e8e53c..4f371592059 100644
--- a/board/mediatek/MAINTAINERS
+++ b/board/mediatek/MAINTAINERS
@@ -1,3 +1,10 @@
+MT8189/MT8371/MT8391 EVK
+M: Macpaul Lin <macpaul.lin@mediatek.com>
+S: Maintained
+F: configs/mt8189.config
+F: configs/mt8371_genio_520_evk_defconfig
+F: configs/mt8391_genio_720_evk_defconfig
+
MT8365 EVK
M: Julien Masson <jmasson@baylibre.com>
S: Maintained
diff --git a/configs/mt8189.config b/configs/mt8189.config
new file mode 100644
index 00000000000..966d05d1a03
--- /dev/null
+++ b/configs/mt8189.config
@@ -0,0 +1,34 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=13000000
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TEXT_BASE=0x4c000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_TARGET_MT8189=y
+CONFIG_MTK_MEM_MAP_DDR_SIZE=0x200000000
+CONFIG_SYS_LOAD_ADDR=0x4c000000
+CONFIG_FIT=y
+CONFIG_BOOTSTD_FULL=y
+# CONFIG_BOARD_INIT is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CLK=y
+# CONFIG_MMC_QUIRKS is not set
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MTK=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT8189=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_MTK_PWRAP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_MT6359=y
+CONFIG_BAUDRATE=921600
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_WDT=y
+CONFIG_WDT_MTK=y
diff --git a/configs/mt8371_genio_520_evk_defconfig b/configs/mt8371_genio_520_evk_defconfig
new file mode 100644
index 00000000000..9a5e68e48ee
--- /dev/null
+++ b/configs/mt8371_genio_520_evk_defconfig
@@ -0,0 +1,4 @@
+#include <configs/mt8189.config>
+
+CONFIG_DEFAULT_DEVICE_TREE="mt8371-genio-520-evk"
+CONFIG_DEFAULT_FDT_FILE="mt8371-genio-520-evk"
diff --git a/configs/mt8391_genio_720_evk_defconfig b/configs/mt8391_genio_720_evk_defconfig
new file mode 100644
index 00000000000..3fcd08be50a
--- /dev/null
+++ b/configs/mt8391_genio_720_evk_defconfig
@@ -0,0 +1,4 @@
+#include <configs/mt8189.config>
+
+CONFIG_DEFAULT_DEVICE_TREE="mt8391-genio-720-evk"
+CONFIG_DEFAULT_FDT_FILE="mt8391-genio-720-evk"
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/6] clk: mediatek: mt8189: add some VLP clocks
2026-03-23 20:16 ` [PATCH v3 1/6] clk: mediatek: mt8189: add some VLP clocks David Lechner
@ 2026-03-23 20:23 ` Tom Rini
2026-03-23 20:33 ` Tom Rini
0 siblings, 1 reply; 15+ messages in thread
From: Tom Rini @ 2026-03-23 20:23 UTC (permalink / raw)
To: David Lechner
Cc: Ryder Lee, Weijie Gao, Chunfeng Yun, Igor Belwon,
GSS_MTK_Uboot_upstream, Macpaul Lin, Lukasz Majewski,
Julien Stephan, u-boot
[-- Attachment #1: Type: text/plain, Size: 952 bytes --]
On Mon, Mar 23, 2026 at 03:16:52PM -0500, David Lechner wrote:
> Add some VLP clocks needed by the PMIC on MT8189 and similar SoCs.
>
> Signed-off-by: David Lechner <dlechner@baylibre.com>
> ---
> drivers/clk/mediatek/clk-mt8189.c | 289 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 289 insertions(+)
I'm working on a series now to fix this globally, and it's not a
MediaTek only problem, but:
> @@ -1733,6 +2012,16 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = {
> .flags = DM_FLAG_PRE_RELOC,
> };
>
> +U_BOOT_DRIVER(mtk_clk_vlpckgen) = {
This is a bad name to use. I bet in other parts of the series you re-use
it. These names need to be unique within a binary, and while today they
will be I bet (since all the other examples are fine), someday we'd like
to be able to compile test (and so static analyize) more code, and it
will clash and fail to link. A better one would be
"mt8189_clk_vlpckgen".
--
Tom
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/6] clk: mediatek: mt8189: add some VLP clocks
2026-03-23 20:23 ` Tom Rini
@ 2026-03-23 20:33 ` Tom Rini
2026-03-23 20:59 ` David Lechner
0 siblings, 1 reply; 15+ messages in thread
From: Tom Rini @ 2026-03-23 20:33 UTC (permalink / raw)
To: David Lechner
Cc: Ryder Lee, Weijie Gao, Chunfeng Yun, Igor Belwon,
GSS_MTK_Uboot_upstream, Macpaul Lin, Lukasz Majewski,
Julien Stephan, u-boot
[-- Attachment #1: Type: text/plain, Size: 1186 bytes --]
On Mon, Mar 23, 2026 at 02:23:58PM -0600, Tom Rini wrote:
> On Mon, Mar 23, 2026 at 03:16:52PM -0500, David Lechner wrote:
>
> > Add some VLP clocks needed by the PMIC on MT8189 and similar SoCs.
> >
> > Signed-off-by: David Lechner <dlechner@baylibre.com>
> > ---
> > drivers/clk/mediatek/clk-mt8189.c | 289 ++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 289 insertions(+)
>
> I'm working on a series now to fix this globally, and it's not a
> MediaTek only problem, but:
>
> > @@ -1733,6 +2012,16 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = {
> > .flags = DM_FLAG_PRE_RELOC,
> > };
> >
> > +U_BOOT_DRIVER(mtk_clk_vlpckgen) = {
>
> This is a bad name to use. I bet in other parts of the series you re-use
> it. These names need to be unique within a binary, and while today they
> will be I bet (since all the other examples are fine), someday we'd like
> to be able to compile test (and so static analyize) more code, and it
> will clash and fail to link. A better one would be
> "mt8189_clk_vlpckgen".
Ugh, and I just hit the build problem where I see these re-used names
are important. So, thinking about things harder now.
--
Tom
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/6] clk: mediatek: mt8189: add some VLP clocks
2026-03-23 20:33 ` Tom Rini
@ 2026-03-23 20:59 ` David Lechner
2026-03-23 21:13 ` Tom Rini
0 siblings, 1 reply; 15+ messages in thread
From: David Lechner @ 2026-03-23 20:59 UTC (permalink / raw)
To: Tom Rini
Cc: Ryder Lee, Weijie Gao, Chunfeng Yun, Igor Belwon,
GSS_MTK_Uboot_upstream, Macpaul Lin, Lukasz Majewski,
Julien Stephan, u-boot
On 3/23/26 3:33 PM, Tom Rini wrote:
> On Mon, Mar 23, 2026 at 02:23:58PM -0600, Tom Rini wrote:
>> On Mon, Mar 23, 2026 at 03:16:52PM -0500, David Lechner wrote:
>>
>>> Add some VLP clocks needed by the PMIC on MT8189 and similar SoCs.
>>>
>>> Signed-off-by: David Lechner <dlechner@baylibre.com>
>>> ---
>>> drivers/clk/mediatek/clk-mt8189.c | 289 ++++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 289 insertions(+)
>>
>> I'm working on a series now to fix this globally, and it's not a
>> MediaTek only problem, but:
>>
>>> @@ -1733,6 +2012,16 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = {
>>> .flags = DM_FLAG_PRE_RELOC,
>>> };
>>>
>>> +U_BOOT_DRIVER(mtk_clk_vlpckgen) = {
>>
>> This is a bad name to use. I bet in other parts of the series you re-use
>> it. These names need to be unique within a binary, and while today they
>> will be I bet (since all the other examples are fine), someday we'd like
>> to be able to compile test (and so static analyize) more code, and it
>> will clash and fail to link. A better one would be
>> "mt8189_clk_vlpckgen".
>
> Ugh, and I just hit the build problem where I see these re-used names
> are important. So, thinking about things harder now.
>
I assume you are referring to the use in mtk_find_parent_rate() and
a few of the mtk_common_clk_*_init() functions.
FYI, I would like to get away from that usage eventually. It seems
pretty fragile. And now you've give another reason to motivate that
change as well. I have so many other MediaTek clock refactor patches
that I'm juggling right now, it will take a while to get around to it
though.
As it happens, mtk_clk_vlpckgen is actually globally unique, so I will
just keep it to be consistent for now and work towards unique naming
for all of the MediaTek clocks later.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/6] clk: mediatek: mt8189: add some VLP clocks
2026-03-23 20:59 ` David Lechner
@ 2026-03-23 21:13 ` Tom Rini
0 siblings, 0 replies; 15+ messages in thread
From: Tom Rini @ 2026-03-23 21:13 UTC (permalink / raw)
To: David Lechner
Cc: Ryder Lee, Weijie Gao, Chunfeng Yun, Igor Belwon,
GSS_MTK_Uboot_upstream, Macpaul Lin, Lukasz Majewski,
Julien Stephan, u-boot
[-- Attachment #1: Type: text/plain, Size: 2251 bytes --]
On Mon, Mar 23, 2026 at 03:59:09PM -0500, David Lechner wrote:
> On 3/23/26 3:33 PM, Tom Rini wrote:
> > On Mon, Mar 23, 2026 at 02:23:58PM -0600, Tom Rini wrote:
> >> On Mon, Mar 23, 2026 at 03:16:52PM -0500, David Lechner wrote:
> >>
> >>> Add some VLP clocks needed by the PMIC on MT8189 and similar SoCs.
> >>>
> >>> Signed-off-by: David Lechner <dlechner@baylibre.com>
> >>> ---
> >>> drivers/clk/mediatek/clk-mt8189.c | 289 ++++++++++++++++++++++++++++++++++++++
> >>> 1 file changed, 289 insertions(+)
> >>
> >> I'm working on a series now to fix this globally, and it's not a
> >> MediaTek only problem, but:
> >>
> >>> @@ -1733,6 +2012,16 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = {
> >>> .flags = DM_FLAG_PRE_RELOC,
> >>> };
> >>>
> >>> +U_BOOT_DRIVER(mtk_clk_vlpckgen) = {
> >>
> >> This is a bad name to use. I bet in other parts of the series you re-use
> >> it. These names need to be unique within a binary, and while today they
> >> will be I bet (since all the other examples are fine), someday we'd like
> >> to be able to compile test (and so static analyize) more code, and it
> >> will clash and fail to link. A better one would be
> >> "mt8189_clk_vlpckgen".
> >
> > Ugh, and I just hit the build problem where I see these re-used names
> > are important. So, thinking about things harder now.
> >
>
> I assume you are referring to the use in mtk_find_parent_rate() and
> a few of the mtk_common_clk_*_init() functions.
Yes, exactly.
> FYI, I would like to get away from that usage eventually. It seems
> pretty fragile. And now you've give another reason to motivate that
> change as well. I have so many other MediaTek clock refactor patches
> that I'm juggling right now, it will take a while to get around to it
> though.
>
> As it happens, mtk_clk_vlpckgen is actually globally unique, so I will
> just keep it to be consistent for now and work towards unique naming
> for all of the MediaTek clocks later.
Sounds good. I do feel like given a lot of the feedback over the last
6-9 months around clock stuff means we need to take a harder look at how
we're doing things today and there's some foundational / structural
issues that need to be addressed.
--
Tom
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 6/6] board: mediatek: Add Genio 520/720 EVK defconfigs
2026-03-23 20:16 ` [PATCH v3 6/6] board: mediatek: Add Genio 520/720 EVK defconfigs David Lechner
@ 2026-03-30 15:21 ` Julien Stephan
2026-03-30 15:56 ` David Lechner
2026-04-07 13:32 ` Macpaul Lin (林智斌)
0 siblings, 2 replies; 15+ messages in thread
From: Julien Stephan @ 2026-03-30 15:21 UTC (permalink / raw)
To: David Lechner
Cc: Tom Rini, Ryder Lee, Weijie Gao, Chunfeng Yun, Igor Belwon,
GSS_MTK_Uboot_upstream, Macpaul Lin, Lukasz Majewski, u-boot,
Chris-QJ Chen
Le lun. 23 mars 2026 à 21:18, David Lechner <dlechner@baylibre.com> a écrit :
>
> From: Chris-QJ Chen <chris-qj.chen@mediatek.com>
>
> Add basic defconfigs for Genio 520 and 720 EVKs.
>
> Signed-off-by: Chris-QJ Chen <chris-qj.chen@mediatek.com>
> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> Signed-off-by: David Lechner <dlechner@baylibre.com>
> ---
> board/mediatek/MAINTAINERS | 7 +++++++
> configs/mt8189.config | 34 ++++++++++++++++++++++++++++++++++
> configs/mt8371_genio_520_evk_defconfig | 4 ++++
> configs/mt8391_genio_720_evk_defconfig | 4 ++++
> 4 files changed, 49 insertions(+)
>
> diff --git a/board/mediatek/MAINTAINERS b/board/mediatek/MAINTAINERS
> index 446a9e8e53c..4f371592059 100644
> --- a/board/mediatek/MAINTAINERS
> +++ b/board/mediatek/MAINTAINERS
> @@ -1,3 +1,10 @@
> +MT8189/MT8371/MT8391 EVK
> +M: Macpaul Lin <macpaul.lin@mediatek.com>
Don't you want to add yourself here? Since you have all the boards to test..
Other than that, for the whole series:
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Thanks
Julien
> +S: Maintained
> +F: configs/mt8189.config
> +F: configs/mt8371_genio_520_evk_defconfig
> +F: configs/mt8391_genio_720_evk_defconfig
> +
> MT8365 EVK
> M: Julien Masson <jmasson@baylibre.com>
> S: Maintained
> diff --git a/configs/mt8189.config b/configs/mt8189.config
> new file mode 100644
> index 00000000000..966d05d1a03
> --- /dev/null
> +++ b/configs/mt8189.config
> @@ -0,0 +1,34 @@
> +CONFIG_ARM=y
> +CONFIG_COUNTER_FREQUENCY=13000000
> +CONFIG_POSITION_INDEPENDENT=y
> +CONFIG_ARCH_MEDIATEK=y
> +CONFIG_TEXT_BASE=0x4c000000
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_OF_LIBFDT_OVERLAY=y
> +CONFIG_TARGET_MT8189=y
> +CONFIG_MTK_MEM_MAP_DDR_SIZE=0x200000000
> +CONFIG_SYS_LOAD_ADDR=0x4c000000
> +CONFIG_FIT=y
> +CONFIG_BOOTSTD_FULL=y
> +# CONFIG_BOARD_INIT is not set
> +CONFIG_CMD_CLK=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_PMIC=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_CLK=y
> +# CONFIG_MMC_QUIRKS is not set
> +CONFIG_MMC_HS200_SUPPORT=y
> +CONFIG_MMC_MTK=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCONF=y
> +CONFIG_PINCTRL_MT8189=y
> +CONFIG_DM_PMIC=y
> +CONFIG_DM_PMIC_MTK_PWRAP=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_MT6359=y
> +CONFIG_BAUDRATE=921600
> +CONFIG_DM_SERIAL=y
> +CONFIG_MTK_SERIAL=y
> +CONFIG_WDT=y
> +CONFIG_WDT_MTK=y
> diff --git a/configs/mt8371_genio_520_evk_defconfig b/configs/mt8371_genio_520_evk_defconfig
> new file mode 100644
> index 00000000000..9a5e68e48ee
> --- /dev/null
> +++ b/configs/mt8371_genio_520_evk_defconfig
> @@ -0,0 +1,4 @@
> +#include <configs/mt8189.config>
> +
> +CONFIG_DEFAULT_DEVICE_TREE="mt8371-genio-520-evk"
> +CONFIG_DEFAULT_FDT_FILE="mt8371-genio-520-evk"
> diff --git a/configs/mt8391_genio_720_evk_defconfig b/configs/mt8391_genio_720_evk_defconfig
> new file mode 100644
> index 00000000000..3fcd08be50a
> --- /dev/null
> +++ b/configs/mt8391_genio_720_evk_defconfig
> @@ -0,0 +1,4 @@
> +#include <configs/mt8189.config>
> +
> +CONFIG_DEFAULT_DEVICE_TREE="mt8391-genio-720-evk"
> +CONFIG_DEFAULT_FDT_FILE="mt8391-genio-720-evk"
>
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 6/6] board: mediatek: Add Genio 520/720 EVK defconfigs
2026-03-30 15:21 ` Julien Stephan
@ 2026-03-30 15:56 ` David Lechner
2026-04-07 13:32 ` Macpaul Lin (林智斌)
1 sibling, 0 replies; 15+ messages in thread
From: David Lechner @ 2026-03-30 15:56 UTC (permalink / raw)
To: Julien Stephan
Cc: Tom Rini, Ryder Lee, Weijie Gao, Chunfeng Yun, Igor Belwon,
GSS_MTK_Uboot_upstream, Macpaul Lin, Lukasz Majewski, u-boot,
Chris-QJ Chen
On 3/30/26 10:21 AM, Julien Stephan wrote:
> Le lun. 23 mars 2026 à 21:18, David Lechner <dlechner@baylibre.com> a écrit :
>>
>> From: Chris-QJ Chen <chris-qj.chen@mediatek.com>
>>
>> Add basic defconfigs for Genio 520 and 720 EVKs.
>>
>> Signed-off-by: Chris-QJ Chen <chris-qj.chen@mediatek.com>
>> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
>> Signed-off-by: David Lechner <dlechner@baylibre.com>
>> ---
>> board/mediatek/MAINTAINERS | 7 +++++++
>> configs/mt8189.config | 34 ++++++++++++++++++++++++++++++++++
>> configs/mt8371_genio_520_evk_defconfig | 4 ++++
>> configs/mt8391_genio_720_evk_defconfig | 4 ++++
>> 4 files changed, 49 insertions(+)
>>
>> diff --git a/board/mediatek/MAINTAINERS b/board/mediatek/MAINTAINERS
>> index 446a9e8e53c..4f371592059 100644
>> --- a/board/mediatek/MAINTAINERS
>> +++ b/board/mediatek/MAINTAINERS
>> @@ -1,3 +1,10 @@
>> +MT8189/MT8371/MT8391 EVK
>> +M: Macpaul Lin <macpaul.lin@mediatek.com>
>
> Don't you want to add yourself here? Since you have all the boards to test..
I don't know how long I will have them. :-)
And now that we are custodians, we should be getting cc'ed on all
patches anyway.
>
> Other than that, for the whole series:
>
> Reviewed-by: Julien Stephan <jstephan@baylibre.com>
>
> Thanks
> Julien
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 6/6] board: mediatek: Add Genio 520/720 EVK defconfigs
2026-03-30 15:21 ` Julien Stephan
2026-03-30 15:56 ` David Lechner
@ 2026-04-07 13:32 ` Macpaul Lin (林智斌)
1 sibling, 0 replies; 15+ messages in thread
From: Macpaul Lin (林智斌) @ 2026-04-07 13:32 UTC (permalink / raw)
To: Julien Stephan, Pablo Sun (孫毓翔),
David Lechner, Bear Wang (萩原惟德),
Ramax Lo (羅明遠)
Cc: Chunfeng Yun (云春峰), trini@konsulko.com,
Ryder Lee, igor.belwon@mentallysanemainliners.org, lukma@denx.de,
Weijie Gao (高惟杰), GSS_MTK_Uboot_upstream,
u-boot@lists.denx.de, Chris-qj Chen (陳奇進)
On Mon, 2026-03-30 at 17:21 +0200, Julien Stephan wrote:
> Le lun. 23 mars 2026 à 21:18, David Lechner <dlechner@baylibre.com> a
> écrit :
> >
> > From: Chris-QJ Chen <chris-qj.chen@mediatek.com>
> >
> > Add basic defconfigs for Genio 520 and 720 EVKs.
> >
> > Signed-off-by: Chris-QJ Chen <chris-qj.chen@mediatek.com>
> > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> > Signed-off-by: David Lechner <dlechner@baylibre.com>
> > ---
> > board/mediatek/MAINTAINERS | 7 +++++++
> > configs/mt8189.config | 34
> > ++++++++++++++++++++++++++++++++++
> > configs/mt8371_genio_520_evk_defconfig | 4 ++++
> > configs/mt8391_genio_720_evk_defconfig | 4 ++++
> > 4 files changed, 49 insertions(+)
> >
> > diff --git a/board/mediatek/MAINTAINERS
> > b/board/mediatek/MAINTAINERS
> > index 446a9e8e53c..4f371592059 100644
> > --- a/board/mediatek/MAINTAINERS
> > +++ b/board/mediatek/MAINTAINERS
> > @@ -1,3 +1,10 @@
> > +MT8189/MT8371/MT8391 EVK
> > +M: Macpaul Lin <macpaul.lin@mediatek.com>
>
> Don't you want to add yourself here? Since you have all the boards to
> test..
>
> Other than that, for the whole series:
>
> Reviewed-by: Julien Stephan <jstephan@baylibre.com>
> Thanks
> Julien
>
Sure! I just not sure I should add a tag for a patch I've participated
before. And, I've just came back for 2 weeks vacations. Thanks for
remind me that.
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
Thanks!
Macpaul Lin
[snip...]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 0/6] boards: mediatek: initial support for Genio 720 EVK
2026-03-23 20:16 [PATCH v3 0/6] boards: mediatek: initial support for Genio 720 EVK David Lechner
` (5 preceding siblings ...)
2026-03-23 20:16 ` [PATCH v3 6/6] board: mediatek: Add Genio 520/720 EVK defconfigs David Lechner
@ 2026-04-07 16:01 ` David Lechner
6 siblings, 0 replies; 15+ messages in thread
From: David Lechner @ 2026-04-07 16:01 UTC (permalink / raw)
To: Tom Rini, Ryder Lee, Weijie Gao, Chunfeng Yun, Igor Belwon,
GSS_MTK_Uboot_upstream, Macpaul Lin, Lukasz Majewski,
David Lechner
Cc: Julien Stephan, u-boot, Chris-QJ Chen, Cathy Xu
On Mon, 23 Mar 2026 15:16:51 -0500, David Lechner wrote:
> boards: mediatek: initial support for Genio 720 EVK
>
> These patches along with the listed prerequisites are enough to get the
> MediaTek Genio 720 EVK board to boot into Linux from the eMMC (with a
> bit of extra config that isn't included here because it isn't generic.)
>
> This is currently being upstreamed in Linux as well, so we just have
> some minimal devicetree files here to hold us over for a while until we
> can switch to the upstream ones.
>
> [...]
Applied to mediatek-for-master, thanks!
[1/6] clk: mediatek: mt8189: add some VLP clocks
commit: c594a2a7ee9aa644999953fd64792ca3d1f98827
[2/6] arm: mediatek: add support of MT8189 SoC family
commit: 437090305f9d1cbc7b8a7fff5d78ef31454ca283
[3/6] arm: dts: mediatek: mt8189: Add pinmux macro header file
commit: 91a41a2084c9534f7c2201fe6767b4ad77356811
[4/6] arm: dts: mediatek: Add MediaTek MT8189 dtsi file
commit: 2eb1c269b0a551f500e2e61c2ab5d8c69eb378b3
[5/6] arm: dts: mediatek: Add MediaTek Genio 520/720 EVK DTS
commit: 06a4a171fba4cf7d7956e28d0a778deba092f8f8
[6/6] board: mediatek: Add Genio 520/720 EVK defconfigs
commit: 75902cc1f407b7380b5659667f37b0ee6d3ef3ef
Best regards,
--
David Lechner <dlechner@baylibre.com>
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2026-04-07 16:01 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-03-23 20:16 [PATCH v3 0/6] boards: mediatek: initial support for Genio 720 EVK David Lechner
2026-03-23 20:16 ` [PATCH v3 1/6] clk: mediatek: mt8189: add some VLP clocks David Lechner
2026-03-23 20:23 ` Tom Rini
2026-03-23 20:33 ` Tom Rini
2026-03-23 20:59 ` David Lechner
2026-03-23 21:13 ` Tom Rini
2026-03-23 20:16 ` [PATCH v3 2/6] arm: mediatek: add support of MT8189 SoC family David Lechner
2026-03-23 20:16 ` [PATCH v3 3/6] arm: dts: mediatek: mt8189: Add pinmux macro header file David Lechner
2026-03-23 20:16 ` [PATCH v3 4/6] arm: dts: mediatek: Add MediaTek MT8189 dtsi file David Lechner
2026-03-23 20:16 ` [PATCH v3 5/6] arm: dts: mediatek: Add MediaTek Genio 520/720 EVK DTS David Lechner
2026-03-23 20:16 ` [PATCH v3 6/6] board: mediatek: Add Genio 520/720 EVK defconfigs David Lechner
2026-03-30 15:21 ` Julien Stephan
2026-03-30 15:56 ` David Lechner
2026-04-07 13:32 ` Macpaul Lin (林智斌)
2026-04-07 16:01 ` [PATCH v3 0/6] boards: mediatek: initial support for Genio 720 EVK David Lechner
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