[PATCH 0/3] Enable ENETC on i.MX952 EVK

[PATCH 0/3] Enable ENETC on i.MX952 EVK

[alice.guo]

Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
Alice Guo (1):
      imx952_evk: Enable ENETC0

Clark Wang (1):
      net: fsl_enetc: fix the duplex setting on the iMX platform

Ye Li (1):
      net: fsl_enetc: Add support for i.MX952

 arch/arm/dts/imx952-evk-u-boot.dtsi   |  94 ++++++++++++++++++++++++++++++++
 arch/arm/dts/imx952-u-boot.dtsi       | 100 ++++++++++++++++++++++++++++++++++
 configs/imx952_evk_defconfig          |   3 +
 drivers/net/Kconfig                   |   4 +-
 drivers/net/fsl_enetc.c               |  46 ++++++++++++----
 drivers/net/fsl_enetc_netc_blk_ctrl.c |  72 ++++++++++++++++++++++++
 6 files changed, 307 insertions(+), 12 deletions(-)
---
base-commit: f7e7c55e53e80100c327b9cb0512c069acf80ab5
change-id: 20260403-enetc-b2d80f42ba23

Best regards,
-- 
Alice Guo <alice.guo@nxp.com>

[PATCH v1 1/3] net: fsl_enetc: fix the duplex setting on the iMX platform

[alice.guo]

From: Clark Wang <xiaoning.wang@nxp.com>

The iMX and LS platforms use different bits in the same register to
set duplex, but their logics are opposite.
The current settings will result in unexpected configurations in
RGMII mode.

Fixes: e6df2f5e22c6 ("net: fsl_enetc: Update enetc driver to support i.MX95")
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
 drivers/net/fsl_enetc.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
index a4ba27904bc..766aea035d3 100644
--- a/drivers/net/fsl_enetc.c
+++ b/drivers/net/fsl_enetc.c
@@ -17,6 +17,7 @@
 #include <asm/io.h>
 #include <pci.h>
 #include <miiphy.h>
+#include <linux/bitfield.h>
 #include <linux/bug.h>
 #include <linux/delay.h>
 #include <linux/build_bug.h>
@@ -388,7 +389,7 @@ static int enetc_init_sgmii(struct udevice *dev)
 /* set up MAC for RGMII */
 static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev)
 {
-	u32 old_val, val, dpx = 0;
+	u32 old_val, val = 0;
 
 	old_val = val = enetc_read_mac_port(dev, ENETC_PM_IF_MODE);
 
@@ -408,15 +409,14 @@ static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev)
 		val |= ENETC_PM_IFM_SSP_10;
 	}
 
-	if (enetc_is_imx95(dev))
-		dpx = ENETC_PM_IFM_FULL_DPX_IMX;
+	if  (enetc_is_imx95(dev))
+		val = u32_replace_bits(val,
+				       phydev->duplex == DUPLEX_FULL ? 0 : 1,
+				       ENETC_PM_IFM_FULL_DPX_IMX);
 	else if (enetc_is_ls1028a(dev))
-		dpx = ENETC_PM_IFM_FULL_DPX_LS;
-
-	if (phydev->duplex == DUPLEX_FULL)
-		val |= dpx;
-	else
-		val &= ~dpx;
+		val = u32_replace_bits(val,
+				       phydev->duplex == DUPLEX_FULL ? 1 : 0,
+				       ENETC_PM_IFM_FULL_DPX_LS);
 
 	if (val == old_val)
 		return;

-- 
2.43.0

[PATCH v1 2/3] net: fsl_enetc: Add support for i.MX952

[alice.guo]

From: Ye Li <ye.li@nxp.com>

Extend ENETC driver to support i.MX952 platform where 2 ENETC
controllers are located on different PCIe buses.

Key changes:
- Add enetc_dev_id_imx() to derive device ID from device tree "reg"
  property for i.MX952, mapping bus_devfn values 0x0 and 0x100 to device
  IDs 0 and 1 respectively
- Implement imx952_netcmix_init() to configure MII protocol and PCS
  settings based on PHY mode parsed from device tree
- Add i.MX952 to FSL_ENETC_NETC_BLK_CTRL Kconfig dependencies

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
 drivers/net/Kconfig                   |  4 +-
 drivers/net/fsl_enetc.c               | 28 +++++++++++++-
 drivers/net/fsl_enetc_netc_blk_ctrl.c | 72 +++++++++++++++++++++++++++++++++++
 3 files changed, 101 insertions(+), 3 deletions(-)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index ed07e286676..4da10ed1289 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1018,8 +1018,8 @@ config FSL_ENETC
 config FSL_ENETC_NETC_BLK_CTRL
 	bool "NXP ENETC NETC blocks control driver"
 	depends on FSL_ENETC
-	depends on IMX95 || IMX94
-	default y if IMX95 || IMX94
+	depends on IMX95 || IMX94 || IMX952
+	default y if IMX95 || IMX94 || IMX952
 	help
 	  This driver configures Integrated Endpoint Register Block (IERB) and
 	  Privileged Register Block (PRB) of NETC. For i.MX platforms, it also
diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
index 766aea035d3..a1569b9d989 100644
--- a/drivers/net/fsl_enetc.c
+++ b/drivers/net/fsl_enetc.c
@@ -67,10 +67,36 @@ static int enetc_is_ls1028a(struct udevice *dev)
 	       pplat->vendor == PCI_VENDOR_ID_FREESCALE;
 }
 
+static int enetc_dev_id_imx(struct udevice *dev)
+{
+	if (IS_ENABLED(CONFIG_IMX952)) {
+		int bus_devfn;
+		u32 reg[5];
+		int error;
+
+		error = ofnode_read_u32_array(dev_ofnode(dev), "reg", reg, ARRAY_SIZE(reg));
+		if (error)
+			return error;
+
+		bus_devfn = (reg[0] >> 8) & 0xffff;
+
+		switch (bus_devfn) {
+		case 0:
+			return 0;
+		case 0x100:
+			return 1;
+		default:
+			return -EINVAL;
+		}
+	}
+
+	return PCI_DEV(pci_get_devfn(dev)) >> 3;
+}
+
 static int enetc_dev_id(struct udevice *dev)
 {
 	if (enetc_is_imx95(dev))
-		return PCI_DEV(pci_get_devfn(dev)) >> 3;
+		return enetc_dev_id_imx(dev);
 	if (enetc_is_ls1028a(dev))
 		return PCI_FUNC(pci_get_devfn(dev));
 
diff --git a/drivers/net/fsl_enetc_netc_blk_ctrl.c b/drivers/net/fsl_enetc_netc_blk_ctrl.c
index 8577bb75632..0c87d80ea5c 100644
--- a/drivers/net/fsl_enetc_netc_blk_ctrl.c
+++ b/drivers/net/fsl_enetc_netc_blk_ctrl.c
@@ -35,6 +35,7 @@
 #define  MII_PROT_RGMII			0x2
 #define  MII_PROT_SERIAL		0x3
 #define  MII_PROT(port, prot)		(((prot) & 0xf) << ((port) << 2))
+#define  MII_PROT_GET(reg, port)	(((reg) >> ((port) << 2)) & 0xf)
 
 #define IMX95_CFG_LINK_PCS_PROT(a)	(0x8 + (a) * 4)
 #define PCS_PROT_1G_SGMII		BIT(0)
@@ -97,6 +98,9 @@
 #define IMX94_TIMER1_ID			1
 #define IMX94_TIMER2_ID			2
 
+#define IMX952_ENETC0_BUS_DEVFN		0x0
+#define IMX952_ENETC1_BUS_DEVFN		0x100
+
 /* Flags for different platforms */
 #define NETC_HAS_NETCMIX		BIT(0)
 
@@ -567,6 +571,69 @@ static int netc_prb_check_error(struct netc_blk_ctrl *priv)
 	return 0;
 }
 
+static int imx952_netcmix_init(struct udevice *dev)
+{
+	struct netc_blk_ctrl *priv = dev_get_priv(dev);
+	ofnode child, gchild;
+	phy_interface_t interface;
+	int bus_devfn, mii_proto;
+	u32 val;
+
+	/* Default setting */
+	val = MII_PROT(0, MII_PROT_RGMII) | MII_PROT(1, MII_PROT_RGMII);
+
+	/* Update the link MII protocol through parsing phy-mode */
+	dev_for_each_subnode(child, dev) {
+		if (!ofnode_is_enabled(child))
+			continue;
+
+		ofnode_for_each_subnode(gchild, child) {
+			if (!ofnode_is_enabled(gchild))
+				continue;
+
+			if (!ofnode_device_is_compatible(gchild, "pci1131,e101"))
+				continue;
+
+			bus_devfn = netc_of_pci_get_bus_devfn(gchild);
+			if (bus_devfn < 0)
+				return -EINVAL;
+
+			interface = ofnode_read_phy_mode(gchild);
+			if (interface == -1)
+				continue;
+
+			mii_proto = netc_get_link_mii_protocol(interface);
+			if (mii_proto < 0)
+				return -EINVAL;
+
+			switch (bus_devfn) {
+			case IMX952_ENETC0_BUS_DEVFN:
+				val &= ~CFG_LINK_MII_PORT_0;
+				val |= FIELD_PREP(CFG_LINK_MII_PORT_0, mii_proto);
+				break;
+			case IMX952_ENETC1_BUS_DEVFN:
+				val &= ~CFG_LINK_MII_PORT_1;
+				val |= FIELD_PREP(CFG_LINK_MII_PORT_1, mii_proto);
+				break;
+			default:
+				return -EINVAL;
+			}
+		}
+	}
+
+	if (MII_PROT_GET(val, 1) == MII_PROT_SERIAL) {
+		/* Configure Link I/O variant */
+		netc_reg_write(priv->netcmix, IMX95_CFG_LINK_IO_VAR,
+			       IO_VAR(1, IO_VAR_16FF_16G_SERDES));
+		/* Configure Link 2 PCS protocol */
+		netc_reg_write(priv->netcmix, IMX95_CFG_LINK_PCS_PROT(1),
+			       PCS_PROT_2500M_SGMII);
+	}
+	netc_reg_write(priv->netcmix, IMX95_CFG_LINK_MII_PROT, val);
+
+	return 0;
+}
+
 static const struct netc_devinfo imx95_devinfo = {
 	.netcmix_init = imx95_netcmix_init,
 	.ierb_init = imx95_ierb_init,
@@ -578,9 +645,14 @@ static const struct netc_devinfo imx94_devinfo = {
 	.xpcs_port_init = imx94_netc_xpcs_port_init,
 };
 
+static const struct netc_devinfo imx952_devinfo = {
+	.netcmix_init = imx952_netcmix_init,
+};
+
 static const struct udevice_id netc_blk_ctrl_match[] = {
 	{ .compatible = "nxp,imx95-netc-blk-ctrl", .data = (ulong)&imx95_devinfo },
 	{ .compatible = "nxp,imx94-netc-blk-ctrl", .data = (ulong)&imx94_devinfo },
+	{ .compatible = "nxp,imx952-netc-blk-ctrl", .data = (ulong)&imx952_devinfo },
 	{},
 };
 

-- 
2.43.0

[PATCH v1 3/3] imx952_evk: Enable ENETC0

[alice.guo]

From: Alice Guo <alice.guo@nxp.com>

Enable ENETC0 functionality on the i.MX952 EVK board.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
 arch/arm/dts/imx952-evk-u-boot.dtsi |  94 +++++++++++++++++++++++++++++++++
 arch/arm/dts/imx952-u-boot.dtsi     | 100 ++++++++++++++++++++++++++++++++++++
 configs/imx952_evk_defconfig        |   3 ++
 3 files changed, 197 insertions(+)

diff --git a/arch/arm/dts/imx952-evk-u-boot.dtsi b/arch/arm/dts/imx952-evk-u-boot.dtsi
index b872c3a7273..2a1770e694a 100644
--- a/arch/arm/dts/imx952-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx952-evk-u-boot.dtsi
@@ -5,6 +5,100 @@
 
 #include "imx952-u-boot.dtsi"
 
+&enetc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enetc0>;
+	phy-handle = <&ethphy0>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+};
+
+&lpi2c6 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c6>;
+	status = "okay";
+
+	pcal6416: gpio@21 {
+		compatible = "nxp,pcal6416";
+		#gpio-cells = <2>;
+		gpio-controller;
+		reg = <0x21>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pcal6416>;
+		vcc-supply = <&reg_3p3v>;
+	};
+};
+
+&netc_blk_ctrl {
+	status = "okay";
+};
+
+&netc_bus0 {
+	status = "okay";
+};
+
+&netc_emdio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_emdio>;
+	status = "okay";
+
+	ethphy0: ethernet-phy@1 {
+		reg = <1>;
+		reset-gpios = <&pcal6416 13 GPIO_ACTIVE_LOW>;
+		reset-assert-us = <10000>;
+		reset-deassert-us = <80000>;
+		realtek,clkout-disable;
+	};
+};
+
+&netc_timer {
+	status = "okay";
+};
+
 &wdog3 {
 	status = "disabled";
 };
+
+&scmi_iomuxc {
+	pinctrl_lpi2c6: lpi2c6grp {
+		fsl,pins = <
+			IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C6_SDA		0x40000b9e
+			IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C6_SCL		0x40000b9e
+		>;
+	};
+
+	pinctrl_pcal6416: pcal6416grp {
+		fsl,pins = <
+			IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10		0x31e
+		>;
+	};
+
+	pinctrl_emdio: emdiogrp{
+		fsl,pins = <
+			IMX952_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC		0x50e
+			IMX952_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO		0x90e
+		>;
+	};
+
+	pinctrl_enetc0: enetc0grp {
+		fsl,pins = <
+			IMX952_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3	0x50e
+			IMX952_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2	0x50e
+			IMX952_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1	0x50e
+			IMX952_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0	0x50e
+			IMX952_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL	0x50e
+			IMX952_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK	0x58e
+			IMX952_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL	0x50e
+			IMX952_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK	0x58e
+			IMX952_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0	0x50e
+			IMX952_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1	0x50e
+			IMX952_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2	0x50e
+			IMX952_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3	0x50e
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx952-u-boot.dtsi b/arch/arm/dts/imx952-u-boot.dtsi
index e977014992e..179e287dbf2 100644
--- a/arch/arm/dts/imx952-u-boot.dtsi
+++ b/arch/arm/dts/imx952-u-boot.dtsi
@@ -223,6 +223,106 @@
 
 &{/soc} {
 	bootph-all;
+
+	netc_blk_ctrl: netc-blk-ctrl@4cd20000 {
+		compatible = "nxp,imx952-netc-blk-ctrl";
+		reg = <0x0 0x4cd20000 0x0 0x10000>,
+		      <0x0 0x4cd30000 0x0 0x10000>,
+		      <0x0 0x4c81000c 0x0 0x1c>;
+		reg-names = "ierb", "prb", "netcmix";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		power-domains = <&scmi_devpd IMX952_PD_NETC>;
+		assigned-clocks = <&scmi_clk IMX952_CLK_ENET>,
+				  <&scmi_clk IMX952_CLK_ENETREF>;
+		assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD2>,
+					 <&scmi_clk IMX952_CLK_SYSPLL1_PFD0>;
+		assigned-clock-rates = <666666666>, <250000000>;
+		clocks = <&scmi_clk IMX952_CLK_CGC_NETC>;
+		clock-names = "ipg";
+
+		netc_bus0: pcie@4ca00000 {
+			compatible = "pci-host-ecam-generic";
+			reg = <0x0 0x4ca00000 0x0 0x100000>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			linux,pci-domain = <0>;
+			bus-range = <0x0 0x0>;
+			msi-map = <0x000 &its 0x60 0x1>, //ENETC0 PF
+				  <0x001 &its 0x62 0x1>, //NETC Timer
+				  <0x002 &its 0x63 0x1>, //EMDIO
+				  <0x040 &its 0x64 0x1>; //ENETC0 VF
+				  /* ENETC0 BAR0 - non-prefetchable memory */
+			ranges = <0x82000000 0x0 0x4cc00000  0x0 0x4cc00000  0x0 0x40000
+				  /* Timer and EMDIO BAR0/2 and ENETC0 VF BAR0 - non-prefetchable memory */
+				  0x82000000 0x0 0x4cc80000  0x0 0x4cc80000  0x0 0x70000
+				  /* ENETC0 VF BAR2 - non-prefetchable memory */
+				  0x82000000 0x0 0x4cd00000  0x0 0x4cd00000  0x0 0x10000>;
+
+			enetc0: ethernet@0,0 {
+				compatible = "pci1131,e101";
+				reg = <0x00000 0 0 0 0>;
+				clocks = <&scmi_clk IMX952_CLK_ENETREF>;
+				clock-names = "ref";
+				status = "disabled";
+			};
+
+			netc_timer: ethernet@0,1 {
+				compatible = "pci1131,ee02";
+				reg = <0x00100 0 0 0 0>;
+				status = "disabled";
+			};
+
+			netc_emdio: mdio@0,2 {
+				compatible = "pci1131,ee00";
+				reg = <0x00200 0 0 0 0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			rcec@1,0 {
+				compatible = "pci1131,e001";
+				reg = <0x00800 0 0 0 0>;
+				interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		netc_bus1: pcie@4cb00000 {
+			compatible = "pci-host-ecam-generic";
+			reg = <0x0 0x4cb00000 0x0 0x100000>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			linux,pci-domain = <1>;
+			bus-range = <0x1 0x1>;
+			msi-map = <0x100 &its 0x61 0x1>, //ENETC1 PF
+				  <0x140 &its 0x65 0x1>; //ENETC1 VF
+				  /* ENETC1 BAR0 - non-prefetchable memory */
+			ranges = <0x82000000 0x0 0x4cc40000  0x0 0x4cc40000  0x0 0x40000
+				  /* ENETC1: VF BAR0 - non-prefetchable memory */
+				  0x82000000 0x0 0x4ccf0000  0x0 0x4ccf0000  0x0 0x10000
+				  /* ENETC1: VF BAR2 - non-prefetchable memory */
+				  0x82000000 0x0 0x4cd10000  0x0 0x4cd10000  0x0 0x10000>;
+			power-domains = <&scmi_devpd IMX952_PD_NETC>;
+
+			enetc1: ethernet@0,0 {
+				compatible = "pci1131,e101";
+				reg = <0x10000 0 0 0 0>;
+				clocks = <&scmi_clk IMX952_CLK_ENETREF>;
+				clock-names = "ref";
+				status = "disabled";
+			};
+
+			rcec@1,0 {
+				compatible = "pci1131,e001";
+				reg = <0x10800 0 0 0 0>;
+				interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+	};
 };
 
 &sram0 {
diff --git a/configs/imx952_evk_defconfig b/configs/imx952_evk_defconfig
index a700aea67a1..c03f3dec89d 100644
--- a/configs/imx952_evk_defconfig
+++ b/configs/imx952_evk_defconfig
@@ -40,6 +40,7 @@ CONFIG_DEFAULT_FDT_FILE="freescale/imx952-evk.dtb"
 CONFIG_SYS_CBSIZE=2048
 CONFIG_SYS_PBSIZE=2074
 CONFIG_BOARD_LATE_INIT=y
+CONFIG_PCI_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x30000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_LOAD_IMX_CONTAINER=y
@@ -111,6 +112,8 @@ CONFIG_DM_PCA953X=y
 CONFIG_ADP5585_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
 CONFIG_IMX_MU_MBOX=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_SUPPORT_EMMC_BOOT=y

-- 
2.43.0

Re: [PATCH v1 3/3] imx952_evk: Enable ENETC0

[Fabio Estevam]

On Fri, Apr 3, 2026 at 8:02 AM <alice.guo@oss.nxp.com> wrote:
>
> From: Alice Guo <alice.guo@nxp.com>
>
> Enable ENETC0 functionality on the i.MX952 EVK board.
>
> Signed-off-by: Alice Guo <alice.guo@nxp.com>
> ---
>  arch/arm/dts/imx952-evk-u-boot.dtsi |  94 +++++++++++++++++++++++++++++++++
>  arch/arm/dts/imx952-u-boot.dtsi     | 100 ++++++++++++++++++++++++++++++++++++

Please explain in the commit log why you are adding these nodes to the
u-boot.dtsi files.

Have they already been submitted to Linux? Have they landed in linux-next?

Please show the full picture here.

回复: [EXT] Re: [PATCH v1 3/3] imx952_evk: Enable ENETC0

[Alice Guo]

> -----邮件原件-----
> 发件人: Fabio Estevam <festevam@gmail.com>
> 发送时间: 2026年4月4日 19:39
> 收件人: Alice Guo (OSS) <alice.guo@oss.nxp.com>
> 抄送: Marek Vasut <marex@nabladev.com>; tharvey@gateworks.com; Ye Li
> <ye.li@nxp.com>; u-boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>;
> Jerome Forissier <jerome.forissier@arm.com>; Tom Rini <trini@konsulko.com>;
> Thomas Schäfer <thomas.schaefer@kontron.com>; Michael Walle
> <mwalle@kernel.org>; Clark Wang <xiaoning.wang@nxp.com>; Christian
> Marangi <ansuelsmth@gmail.com>; Simon Glass <sjg@chromium.org>;
> Quentin Schulz <quentin.schulz@cherry.de>; Mikhail Kshevetskiy
> <mikhail.kshevetskiy@iopsys.eu>; Robert Marko <robert.marko@sartura.hr>;
> Yao Zi <me@ziyao.cc>; Heiko Thiery <heiko.thiery@gmail.com>; Marek Vasut
> <marek.vasut+renesas@mailbox.org>; Peng Fan <peng.fan@nxp.com>; Jacky
> Bai <ping.bai@nxp.com>; Andrew Goodbody <andrew.goodbody@linaro.org>;
> Stefano Babic <sbabic@nabladev.com>; Alice Guo <alice.guo@nxp.com>
> 主题: [EXT] Re: [PATCH v1 3/3] imx952_evk: Enable ENETC0
> 
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report this
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> 
> 
> On Fri, Apr 3, 2026 at 8:02 AM <alice.guo@oss.nxp.com> wrote:
> >
> > From: Alice Guo <alice.guo@nxp.com>
> >
> > Enable ENETC0 functionality on the i.MX952 EVK board.
> >
> > Signed-off-by: Alice Guo <alice.guo@nxp.com>
> > ---
> >  arch/arm/dts/imx952-evk-u-boot.dtsi |  94
> +++++++++++++++++++++++++++++++++
> >  arch/arm/dts/imx952-u-boot.dtsi     | 100
> ++++++++++++++++++++++++++++++++++++
> 
> Please explain in the commit log why you are adding these nodes to the
> u-boot.dtsi files.
> 
> Have they already been submitted to Linux? Have they landed in linux-next?
> 
> Please show the full picture here.

Hi Fabio,

ENETC device tree nodes have not yet been submitted to the Linux. They are not present in linux-next or devicetree-rebasing. Do I need to resubmit the patch to U-Boot after these nodes are included in linux-next?

Best regards,
Alice Guo

Re: [EXT] Re: [PATCH v1 3/3] imx952_evk: Enable ENETC0

[Fabio Estevam]

Hi Alice,

On Tue, Apr 7, 2026 at 4:16 AM Alice Guo <alice.guo@nxp.com> wrote:

> ENETC device tree nodes have not yet been submitted to the Linux. They are not present in linux-next or devicetree-rebasing. Do I need to resubmit the patch to U-Boot after these nodes are included in linux-next?

Yes, please.