[PATCH 1/2] sunxi: H616: dram: fix LPDDR3 TPR6 parsing

[Philippe Simons <simons.philippe@gmail.com>]

From: Jernej Skrabec <jernej.skrabec@gmail.com>

When a user copies the vendor value of tpr6 into the mainline U-Boot,
the code parses the tpr6 parameter incorrectly and writes the wrong value.
Fixes Vref parsing from TPR6. Proper order from LSB to MSB is DDR3, DDR4,
LPDDR3 and LPDDR4

Fix that.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
[adjusted commit message]
Signed-off-by: Philippe Simons <simons.philippe@gmail.com>
---
 arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 3345c9b8e82..42a0550e015 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -975,7 +975,7 @@ static bool mctl_phy_init(const struct dram_para *para,
 		val = para->tpr6 & 0xff;
 		break;
 	case SUNXI_DRAM_TYPE_LPDDR3:
-		val = para->tpr6 >> 8 & 0xff;
+		val = para->tpr6 >> 16 & 0xff;
 		break;
 	case SUNXI_DRAM_TYPE_LPDDR4:
 		val = para->tpr6 >> 24 & 0xff;
-- 
2.53.0