Re: [PATCH 1/2] sunxi: H616: dram: fix LPDDR3 TPR6 parsing

[Andre Przywara <andre.przywara@arm.com>]

On Sun,  5 Apr 2026 21:59:26 +0200
Philippe Simons <simons.philippe@gmail.com> wrote:

Hi Philippe,

thanks for taking care of sending this patch!

> From: Jernej Skrabec <jernej.skrabec@gmail.com>
> 
> When a user copies the vendor value of tpr6 into the mainline U-Boot,
> the code parses the tpr6 parameter incorrectly and writes the wrong value.

That sentence is hard to understand unless you know what this value is
about already. What about:

===============
Allwinner's BSP DRAM code uses parameter TPR6, presumably containing
some "Vref" parameter, to encode the values for *all* four supported DRAM
types. The code selects one byte based on the DRAM type used at runtime.
To allow copying DRAM parameters from vendor firmware, we used this value
and its encoding, but wrongly: the proper order of bytes is DDR3, DDR4,
LPDDR3, LPDDR4, from LSB to MSB, cf. the A523 and A133 DRAM code.

Correct the masking for LPDDR3 to fix DRAM operation on some boards
using this DRAM type.
==============

Plus we need the second patch merged into this one, otherwise this
would introduce (an admittedly theoretical) regression.

But the actual changes in both patches looks good to me.

Cheers,
Andre


> Fixes Vref parsing from TPR6. Proper order from LSB to MSB is DDR3, DDR4,
> LPDDR3 and LPDDR4
> 
> Fix that.
> 
> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
> [adjusted commit message]
> Signed-off-by: Philippe Simons <simons.philippe@gmail.com>
> ---
>  arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
> index 3345c9b8e82..42a0550e015 100644
> --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
> +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
> @@ -975,7 +975,7 @@ static bool mctl_phy_init(const struct dram_para *para,
>  		val = para->tpr6 & 0xff;
>  		break;
>  	case SUNXI_DRAM_TYPE_LPDDR3:
> -		val = para->tpr6 >> 8 & 0xff;
> +		val = para->tpr6 >> 16 & 0xff;
>  		break;
>  	case SUNXI_DRAM_TYPE_LPDDR4:
>  		val = para->tpr6 >> 24 & 0xff;