* [PATCH 0/2] Fix LPDDR3 H616 TPR6 parsing @ 2026-04-05 19:59 Philippe Simons 2026-04-05 19:59 ` [PATCH 1/2] sunxi: H616: dram: fix LPDDR3 " Philippe Simons 2026-04-05 19:59 ` [PATCH 2/2] sunxi: fix DRAM_SUNXI_TPR6 default value Philippe Simons 0 siblings, 2 replies; 4+ messages in thread From: Philippe Simons @ 2026-04-05 19:59 UTC (permalink / raw) To: Jagan Teki, Andre Przywara, Tom Rini Cc: Jernej Skrabec, Kory Maincent (TI.com), Paul Kocialkowski, Cody Eksal, Philippe Simons, Samuel Holland, Mikhail Kalashnikov, u-boot Vendor TPR6 parameter is currently incorrectly parsed in H616 dram code. Fix that and adjust Kconfig default value accordingly. Philippe Simons (2): sunxi: H616: dram: fix LPDDR3 TPR6 parsing sunxi: fix DRAM_SUNXI_TPR6 default value arch/arm/mach-sunxi/Kconfig | 2 +- arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 2.53.0 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] sunxi: H616: dram: fix LPDDR3 TPR6 parsing 2026-04-05 19:59 [PATCH 0/2] Fix LPDDR3 H616 TPR6 parsing Philippe Simons @ 2026-04-05 19:59 ` Philippe Simons 2026-04-06 21:35 ` Andre Przywara 2026-04-05 19:59 ` [PATCH 2/2] sunxi: fix DRAM_SUNXI_TPR6 default value Philippe Simons 1 sibling, 1 reply; 4+ messages in thread From: Philippe Simons @ 2026-04-05 19:59 UTC (permalink / raw) To: Jagan Teki, Andre Przywara, Tom Rini Cc: Jernej Skrabec, Kory Maincent (TI.com), Paul Kocialkowski, Cody Eksal, Philippe Simons, Samuel Holland, Mikhail Kalashnikov, u-boot From: Jernej Skrabec <jernej.skrabec@gmail.com> When a user copies the vendor value of tpr6 into the mainline U-Boot, the code parses the tpr6 parameter incorrectly and writes the wrong value. Fixes Vref parsing from TPR6. Proper order from LSB to MSB is DDR3, DDR4, LPDDR3 and LPDDR4 Fix that. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> [adjusted commit message] Signed-off-by: Philippe Simons <simons.philippe@gmail.com> --- arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 3345c9b8e82..42a0550e015 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -975,7 +975,7 @@ static bool mctl_phy_init(const struct dram_para *para, val = para->tpr6 & 0xff; break; case SUNXI_DRAM_TYPE_LPDDR3: - val = para->tpr6 >> 8 & 0xff; + val = para->tpr6 >> 16 & 0xff; break; case SUNXI_DRAM_TYPE_LPDDR4: val = para->tpr6 >> 24 & 0xff; -- 2.53.0 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] sunxi: H616: dram: fix LPDDR3 TPR6 parsing 2026-04-05 19:59 ` [PATCH 1/2] sunxi: H616: dram: fix LPDDR3 " Philippe Simons @ 2026-04-06 21:35 ` Andre Przywara 0 siblings, 0 replies; 4+ messages in thread From: Andre Przywara @ 2026-04-06 21:35 UTC (permalink / raw) To: Philippe Simons Cc: Jagan Teki, Tom Rini, Jernej Skrabec, Kory Maincent (TI.com), Paul Kocialkowski, Cody Eksal, Samuel Holland, Mikhail Kalashnikov, u-boot, linux-sunxi On Sun, 5 Apr 2026 21:59:26 +0200 Philippe Simons <simons.philippe@gmail.com> wrote: Hi Philippe, thanks for taking care of sending this patch! > From: Jernej Skrabec <jernej.skrabec@gmail.com> > > When a user copies the vendor value of tpr6 into the mainline U-Boot, > the code parses the tpr6 parameter incorrectly and writes the wrong value. That sentence is hard to understand unless you know what this value is about already. What about: =============== Allwinner's BSP DRAM code uses parameter TPR6, presumably containing some "Vref" parameter, to encode the values for *all* four supported DRAM types. The code selects one byte based on the DRAM type used at runtime. To allow copying DRAM parameters from vendor firmware, we used this value and its encoding, but wrongly: the proper order of bytes is DDR3, DDR4, LPDDR3, LPDDR4, from LSB to MSB, cf. the A523 and A133 DRAM code. Correct the masking for LPDDR3 to fix DRAM operation on some boards using this DRAM type. ============== Plus we need the second patch merged into this one, otherwise this would introduce (an admittedly theoretical) regression. But the actual changes in both patches looks good to me. Cheers, Andre > Fixes Vref parsing from TPR6. Proper order from LSB to MSB is DDR3, DDR4, > LPDDR3 and LPDDR4 > > Fix that. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> > [adjusted commit message] > Signed-off-by: Philippe Simons <simons.philippe@gmail.com> > --- > arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c > index 3345c9b8e82..42a0550e015 100644 > --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c > +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c > @@ -975,7 +975,7 @@ static bool mctl_phy_init(const struct dram_para *para, > val = para->tpr6 & 0xff; > break; > case SUNXI_DRAM_TYPE_LPDDR3: > - val = para->tpr6 >> 8 & 0xff; > + val = para->tpr6 >> 16 & 0xff; > break; > case SUNXI_DRAM_TYPE_LPDDR4: > val = para->tpr6 >> 24 & 0xff; ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/2] sunxi: fix DRAM_SUNXI_TPR6 default value 2026-04-05 19:59 [PATCH 0/2] Fix LPDDR3 H616 TPR6 parsing Philippe Simons 2026-04-05 19:59 ` [PATCH 1/2] sunxi: H616: dram: fix LPDDR3 " Philippe Simons @ 2026-04-05 19:59 ` Philippe Simons 1 sibling, 0 replies; 4+ messages in thread From: Philippe Simons @ 2026-04-05 19:59 UTC (permalink / raw) To: Jagan Teki, Andre Przywara, Tom Rini Cc: Jernej Skrabec, Kory Maincent (TI.com), Paul Kocialkowski, Cody Eksal, Philippe Simons, Samuel Holland, Mikhail Kalashnikov, u-boot With LPDDR3 TPR6 parsing fix, adapt default DRAM_SUNXI_TPR6 value. Also change LPDDR4 default value to 0x38 used by A523 boards. Signed-off-by: Philippe Simons <simons.philippe@gmail.com> --- arch/arm/mach-sunxi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index e979ee4a2cc..a1ddc6a1fc8 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -144,7 +144,7 @@ config DRAM_SUNXI_TPR3 config DRAM_SUNXI_TPR6 hex "DRAM TPR6 parameter" - default 0x3300c080 + default 0x38c00080 help TPR6 value from vendor DRAM settings. -- 2.53.0 ^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2026-04-06 21:36 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-04-05 19:59 [PATCH 0/2] Fix LPDDR3 H616 TPR6 parsing Philippe Simons 2026-04-05 19:59 ` [PATCH 1/2] sunxi: H616: dram: fix LPDDR3 " Philippe Simons 2026-04-06 21:35 ` Andre Przywara 2026-04-05 19:59 ` [PATCH 2/2] sunxi: fix DRAM_SUNXI_TPR6 default value Philippe Simons
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