[PATCH 0/9] arm: hpe: Add HPE GSC (Gen12) BMC SoC support

[PATCH 0/9] arm: hpe: Add HPE GSC (Gen12) BMC SoC support

[Jorge Cisneros]

This series adds support for the HPE GSC (Gen Server Controller), an
ARM64-based BMC SoC used in HPE ProLiant and Synergy Gen12 servers.

The GSC is the successor to the GXP SoC (already upstream) used in
Gen11 servers. It features dual Cortex-A35 cores with GICv3, a Denali
DDR memory controller, Cadence GEM Ethernet (SGMII), and reuses several
GXP IP blocks (timer, SPI, I2C).

The existing ARCH_GXP Kconfig symbol is renamed to ARCH_HPE to serve as
an umbrella for both the GXP (ARMv7) and GSC (ARMv8) SoC variants,
selected via a choice menu under mach-hpe.

New drivers:
- Watchdog (drivers/watchdog/gsc_wdt.c)
- Memory-mapped virtual EEPROM for VPD (drivers/misc/gsc_mem_eeprom.c)
- Cadence GEM support added to the existing MACB driver

Board support includes DRAM sizing from the Denali memory controller,
MAC address provisioning from VPD EEPROM, FDT fixups for network
configuration, shared Ethernet/DisplayPort PHY initialization, and a
server_id command for reading server identification from the CPLD.

Notes:
- The server_id command (patch 7) is hardware-specific and reads from
  GSC CPLD registers, so no sandbox test is included.
- MAINTAINERS warnings in patches 1-8 are resolved by patch 9.

Based on v2026.04-rc4 (ba7bf918dafcd093ad733b07ba490baeb20cf5da).
Tested: both gxp_defconfig and gsc_defconfig build cleanly.

Signed-off-by: Jorge Cisneros <jorge.cisneros@hpe.com>
---
Jorge Cisneros (9):
      arm: hpe: Rename ARCH_GXP to ARCH_HPE and add GSC SoC choice
      arm: hpe: Add GSC SoC support
      arm: dts: Add HPE GSC device tree
      watchdog: Add HPE GSC watchdog driver
      misc: Add HPE GSC memory-mapped EEPROM driver
      net: macb: Add HPE GSC GEM Ethernet support
      board: hpe: Add GSC board support
      configs: Add gsc_defconfig for HPE GSC SoC
      MAINTAINERS: Add HPE GSC files and maintainer

 MAINTAINERS                                  |   8 +-
 arch/arm/Kconfig                             |   9 +-
 arch/arm/Makefile                            |   2 +-
 arch/arm/dts/hpe-gsc.dts                     | 146 ++++++++
 arch/arm/include/asm/arch-gsc/clk.h          |  14 +
 arch/arm/mach-hpe/Kconfig                    |  33 ++
 arch/arm/mach-hpe/Makefile                   |   1 +
 arch/arm/mach-hpe/gsc/Kconfig                |  27 ++
 arch/arm/mach-hpe/gsc/Makefile               |   1 +
 arch/arm/mach-hpe/gsc/reset.c                |  19 +
 arch/arm/mach-hpe/gxp/Kconfig                |   2 +-
 board/hpe/gsc/Kconfig                        |  18 +
 board/hpe/gsc/Makefile                       |   3 +
 board/hpe/gsc/common-phy-wrapper-addresses.h |  86 +++++
 board/hpe/gsc/common-phy.c                   | 296 +++++++++++++++
 board/hpe/gsc/common-phy.h                   |   8 +
 board/hpe/gsc/gsc.env                        |   9 +
 board/hpe/gsc/gsc_board.c                    | 538 +++++++++++++++++++++++++++
 board/hpe/gsc/server_id.c                    |  51 +++
 configs/gsc_defconfig                        |  88 +++++
 configs/gxp_defconfig                        |   2 +-
 drivers/misc/Kconfig                         |   7 +
 drivers/misc/Makefile                        |   1 +
 drivers/misc/gsc_mem_eeprom.c                | 118 ++++++
 drivers/net/macb.c                           |  17 +
 drivers/watchdog/Kconfig                     |   7 +
 drivers/watchdog/Makefile                    |   1 +
 drivers/watchdog/gsc_wdt.c                   | 110 ++++++
 include/configs/gsc.h                        |  25 ++
 29 files changed, 1640 insertions(+), 7 deletions(-)
---
base-commit: ba7bf918dafcd093ad733b07ba490baeb20cf5da
change-id: 20260408-hpe-gsc-upstream-369c5ee59c0a

Best regards,
--  
Jorge Cisneros <jorge.cisneros@hpe.com>

[PATCH 1/9] arm: hpe: Rename ARCH_GXP to ARCH_HPE and add GSC SoC choice

[Jorge Cisneros]

Rename ARCH_GXP to ARCH_HPE to serve as an umbrella config for all HPE
BMC SoCs. Add a choice menu under mach-hpe to select between:
- HPE_GXP: Gen11 (GXP) BMC SoC (ARMv7)
- HPE_GSC: Gen12 (GSC) BMC SoC (ARMv8)

Update arch/arm/Makefile to use the new CONFIG_ARCH_HPE symbol and
migrate the existing gxp_defconfig. Add stub Kconfig files for the GSC
SoC and board to maintain a valid Kconfig tree.

Signed-off-by: Jorge Cisneros <jorge.cisneros@hpe.com>
---
 arch/arm/Kconfig               |  9 ++++++---
 arch/arm/Makefile              |  2 +-
 arch/arm/mach-hpe/Kconfig      | 33 +++++++++++++++++++++++++++++++++
 arch/arm/mach-hpe/Makefile     |  1 +
 arch/arm/mach-hpe/gsc/Kconfig  | 27 +++++++++++++++++++++++++++
 arch/arm/mach-hpe/gsc/Makefile |  1 +
 arch/arm/mach-hpe/gxp/Kconfig  |  2 +-
 board/hpe/gsc/Kconfig          | 18 ++++++++++++++++++
 configs/gxp_defconfig          |  2 +-
 9 files changed, 89 insertions(+), 6 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cd6a454fd60..509a593eb77 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2182,11 +2182,14 @@ config TARGET_XENGUEST_ARM64
 	select XEN_SERIAL
 	imply OF_HAS_PRIOR_STAGE
 
-config ARCH_GXP
-	bool "Support HPE GXP SoCs"
+config ARCH_HPE
+	bool "Support HPE SoCs"
 	select DM
 	select OF_CONTROL
 	imply CMD_DM
+	help
+	  Support for HPE BMC SoCs including the GXP (Gen11)
+	  and GSC (Gen12) server management controllers.
 
 endchoice
 
@@ -2290,7 +2293,7 @@ source "arch/arm/mach-davinci/Kconfig"
 
 source "arch/arm/mach-exynos/Kconfig"
 
-source "arch/arm/mach-hpe/gxp/Kconfig"
+source "arch/arm/mach-hpe/Kconfig"
 
 source "arch/arm/mach-highbank/Kconfig"
 
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index b36b0742580..4a60cd94a66 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -60,7 +60,7 @@ machine-$(CONFIG_ARCH_BCMBCA)		+= bcmbca
 machine-$(CONFIG_ARCH_BCMSTB)		+= bcmstb
 machine-$(CONFIG_ARCH_DAVINCI)		+= davinci
 machine-$(CONFIG_ARCH_EXYNOS)		+= exynos
-machine-$(CONFIG_ARCH_GXP)		+= hpe
+machine-$(CONFIG_ARCH_HPE)		+= hpe
 machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
 machine-$(CONFIG_ARCH_HISTB)		+= histb
 machine-$(CONFIG_ARCH_IPQ40XX)		+= ipq40xx
diff --git a/arch/arm/mach-hpe/Kconfig b/arch/arm/mach-hpe/Kconfig
new file mode 100644
index 00000000000..23840721435
--- /dev/null
+++ b/arch/arm/mach-hpe/Kconfig
@@ -0,0 +1,33 @@
+if ARCH_HPE
+
+choice
+	prompt "HPE SoC select"
+	depends on ARCH_HPE
+	default HPE_GXP
+	help
+	  Select the HPE SoC variant. GXP is used in Gen11
+	  servers and GSC is used in Gen12 servers.
+
+config HPE_GXP
+	bool "Support HPE GXP SoC"
+	help
+	  Support for the HPE GXP SoC, an ARM-based BMC
+	  used in HPE ProLiant Gen11 servers.
+
+config HPE_GSC
+	bool "Support HPE GSC SoC"
+	select DM
+	select SOC_GSC
+	select OF_CONTROL
+	select ARCH_EARLY_INIT_R
+	imply CMD_DM
+	help
+	  Support for the HPE GSC SoC, an ARM64-based BMC
+	  used in HPE ProLiant Gen12 servers.
+
+endchoice
+
+source "arch/arm/mach-hpe/gxp/Kconfig"
+source "arch/arm/mach-hpe/gsc/Kconfig"
+
+endif
diff --git a/arch/arm/mach-hpe/Makefile b/arch/arm/mach-hpe/Makefile
index afe5f7a29ee..ff566a3a047 100644
--- a/arch/arm/mach-hpe/Makefile
+++ b/arch/arm/mach-hpe/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_SOC_GXP) += gxp/
+obj-$(CONFIG_SOC_GSC) += gsc/
diff --git a/arch/arm/mach-hpe/gsc/Kconfig b/arch/arm/mach-hpe/gsc/Kconfig
new file mode 100644
index 00000000000..9821bf6149f
--- /dev/null
+++ b/arch/arm/mach-hpe/gsc/Kconfig
@@ -0,0 +1,27 @@
+if HPE_GSC
+
+config SOC_GSC
+	bool
+	select ARM64
+
+config SYS_SOC
+	default "gsc"
+
+config GSC_I3C_HUB_DT
+	bool "Fix up the I3C Hub Node in Kernel DTS"
+	default n
+	help
+	  Enable this if I3C Hub is supported otherwise noise will show
+	  up on I3C Bus for unused populated ports.
+
+config GSC_PATCH_KERNEL_DTS_VPD
+	bool "Patch kernel DTS to add system VPD from virtual EEPROM"
+	default n
+	help
+	  Enable to patch kernel DTS to add system VPD from virtual
+	  EEPROM. This will add Vital Product Data such as serial
+	  number and model name to the kernel DTS at /.
+
+source "board/hpe/gsc/Kconfig"
+
+endif
diff --git a/arch/arm/mach-hpe/gsc/Makefile b/arch/arm/mach-hpe/gsc/Makefile
new file mode 100644
index 00000000000..f3cc6684b89
--- /dev/null
+++ b/arch/arm/mach-hpe/gsc/Makefile
@@ -0,0 +1 @@
+obj-y += reset.o
diff --git a/arch/arm/mach-hpe/gxp/Kconfig b/arch/arm/mach-hpe/gxp/Kconfig
index 2d43133ab06..42e65714ef6 100644
--- a/arch/arm/mach-hpe/gxp/Kconfig
+++ b/arch/arm/mach-hpe/gxp/Kconfig
@@ -1,4 +1,4 @@
-if ARCH_GXP
+if HPE_GXP
 
 config SOC_GXP
 	bool
diff --git a/board/hpe/gsc/Kconfig b/board/hpe/gsc/Kconfig
new file mode 100644
index 00000000000..66346e2df27
--- /dev/null
+++ b/board/hpe/gsc/Kconfig
@@ -0,0 +1,18 @@
+if SOC_GSC
+
+config SYS_BOARD
+default "gsc"
+
+config SYS_VENDOR
+default "hpe"
+
+config SYS_CONFIG_NAME
+default "gsc"
+
+config GICV3
+def_bool y
+
+config TEXT_BASE
+default 0x10000000
+
+endif
diff --git a/configs/gxp_defconfig b/configs/gxp_defconfig
index 7821759f83d..31e4d9b8ac8 100644
--- a/configs/gxp_defconfig
+++ b/configs/gxp_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_GXP=y
+CONFIG_ARCH_HPE=y
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_GXP_VROM_64MB=y
 CONFIG_NR_DRAM_BANKS=1

-- 
2.43.0

[PATCH 2/9] arm: hpe: Add GSC SoC support

[Jorge Cisneros]

Add core SoC support for the HPE GSC (Gen Server Controller), an ARM64
BMC SoC used in HPE Gen12 ProLiant and Synergy servers.

This includes:
- Kconfig entries for SOC_GSC with ARM64, I3C hub DT fixup, and VPD
  patching options (SYS_SOC set to "gsc")
- SoC reset implementation via writel to GSC system control register
- Architecture-level clock header for MACB Ethernet driver compatibility

The GSC reuses several GXP IP blocks (timer, SPI, I2C) while adding
new peripherals including a GICv3 interrupt controller, Cadence MACB
GEM Ethernet, and a Denali DDR memory controller.

Signed-off-by: Jorge Cisneros <jorge.cisneros@hpe.com>
---
 arch/arm/include/asm/arch-gsc/clk.h | 14 ++++++++++++++
 arch/arm/mach-hpe/gsc/reset.c       | 19 +++++++++++++++++++
 2 files changed, 33 insertions(+)

diff --git a/arch/arm/include/asm/arch-gsc/clk.h b/arch/arm/include/asm/arch-gsc/clk.h
new file mode 100644
index 00000000000..19922c433d4
--- /dev/null
+++ b/arch/arm/include/asm/arch-gsc/clk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * HPE GSC SoC clock interface
+ */
+
+#ifndef _ASM_ARCH_CLK_H_
+#define _ASM_ARCH_CLK_H_
+
+static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
+{
+	return 50000000; /* 50 MHz */
+}
+
+#endif /* _ASM_ARCH_CLK_H_ */
diff --git a/arch/arm/mach-hpe/gsc/reset.c b/arch/arm/mach-hpe/gsc/reset.c
new file mode 100644
index 00000000000..67fc83b2deb
--- /dev/null
+++ b/arch/arm/mach-hpe/gsc/reset.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * GSC SoC reset
+ *
+ * (C) Copyright 2019-2025 Hewlett Packard Enterprise Development LP.
+ * Author: Gilbert Chen <gilbert.chen@hpe.com>
+ */
+
+#include <asm/io.h>
+
+#define GSC_CCR	0xC0000000
+
+void reset_cpu(void)
+{
+	writel(1, GSC_CCR);
+
+	while (1)
+		;	/* loop forever till reset */
+}

-- 
2.43.0

[PATCH 3/9] arm: dts: Add HPE GSC device tree

[Jorge Cisneros]

Add device tree for the HPE GSC SoC including:
- Dual Cortex-A35 cores with spin-table enable method
- GICv3 interrupt controller
- NS16550A compatible UART
- GXP timer and SPI/I2C controllers (shared IP blocks)
- Two Cadence GEM Ethernet MACs with SGMII PHYs
- Synopsys DWC MSHC eMMC controller
- GSC watchdog timer
- Memory-mapped virtual EEPROM for VPD storage
- Fixed clock definitions for peripheral buses

Signed-off-by: Jorge Cisneros <jorge.cisneros@hpe.com>
---
 arch/arm/dts/hpe-gsc.dts | 146 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 146 insertions(+)

diff --git a/arch/arm/dts/hpe-gsc.dts b/arch/arm/dts/hpe-gsc.dts
new file mode 100644
index 00000000000..162099c2b60
--- /dev/null
+++ b/arch/arm/dts/hpe-gsc.dts
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * GSC Device Tree
+ *
+ * (C) Copyright 2019-2025 Hewlett Packard Enterprise Development LP.
+ * Author: Gilbert Chen <gilbert.chen@hpe.com>
+ */
+
+/dts-v1/;
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "hpe,gsc";
+	model = "HPE GSC";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = &uartc;
+	};
+
+	aliases {
+		serial0 = &uartc;
+		spi0 = &spi0;
+	};
+
+	ahb@80000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x80000000 0x52000000>;
+		ranges;
+
+		gic: gic@ce000000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			ranges;
+			interrupt-controller;
+			redistributor-stride = <0x0 0x20000>;
+			#redistributor-regions = <1>;
+			reg = <0xce000000 0x10000>,
+			      <0xce060000 0x40000>,
+			      <0xce200000 0x40000>;
+		};
+
+		timer: timer@c0000098 {
+			compatible = "hpe,gxp-timer";
+			reg = <0xc0000098 0x08>;
+			clock-frequency = <1000000>;
+		};
+
+		uartc: serial@c00000f0 {
+			compatible = "ns16550a";
+			reg = <0xc00000f0 0x8>;
+			clock-frequency = <1843212>;
+			reg-shift = <0>;
+			no-loopback-test;
+			status = "okay";
+		};
+
+		watchdog: watchdog@c0000090 {
+			compatible = "hpe,gsc-wdt";
+			reg = <0xc0000090 0x02>, <0xc0000096 0x01>;
+		};
+
+		spi0: spi@cef00000 {
+			reg = <0xcef00000 0x80>, <0xcef08000 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "hpe,gxp-spi";
+			status = "okay";
+
+			flash@0 {
+				reg = <0>;
+				compatible = "jedec,spi-nor";
+				spi-max-frequency = <50000000>;
+			};
+
+			flash@1 {
+				reg = <1>;
+				compatible = "jedec,spi-nor";
+				spi-max-frequency = <50000000>;
+			};
+		};
+
+		i2c2: i2c@c0002200 {
+			compatible = "hpe,gxp-i2c";
+			reg = <0xc0002200 0x70>;
+			clock-frequency = <100000>;
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			eeprom: eeprom@a0017f00 {
+				compatible = "i2c_gsc_mem_eeprom";
+				reg = <0xa0017f00 0x100>;
+			};
+		};
+
+		sdhci0: sdhci@cefe1000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xcefe1000 0x400>;
+			interrupts = <0 23 4>;
+			interrupt-parent = <&gic>;
+			clocks = <&emmcclk>;
+			clock-names = "core";
+			bus-width = <8>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			non-removable;
+			max-frequency = <200000000>;
+			mmc-hs200-1_8v;
+		};
+
+		macb0: ethernet@c0004000 {
+			compatible = "hpe,gsc-gem";
+			reg = <0xc0004000 0x1000>;
+			interrupts = <0 74 4>, <0 75 4>, <0 76 4>;
+			interrupt-parent = <&gic>;
+			phy-handle = <&ethernet_phy>;
+			clock-names = "pclk", "hclk", "tx_clk";
+			clocks = <&clk125>, <&clk125>, <&clk125>;
+			phy-mode = "sgmii";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			ethernet_phy: ethernet-phy@0 {
+				reg = <0x0>;
+			};
+		};
+	};
+
+	clocks {
+		clk125: clk125 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <125000000>;
+		};
+
+		emmcclk: emmcclk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+			clock-output-names = "emmcclk";
+		};
+	};
+};

-- 
2.43.0

[PATCH 4/9] watchdog: Add HPE GSC watchdog driver

[Jorge Cisneros]

Add watchdog driver for the HPE GSC SoC. The GSC watchdog uses two
separate register regions: a counter register and a control register.
Writing the counter value resets the watchdog timer, while writing to
the control register enables or disables the watchdog.

Supported operations: start, stop, reset, and expire_now.

Signed-off-by: Jorge Cisneros <jorge.cisneros@hpe.com>
---
 drivers/watchdog/Kconfig   |   7 +++
 drivers/watchdog/Makefile  |   1 +
 drivers/watchdog/gsc_wdt.c | 110 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 118 insertions(+)

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 35ae7d106b1..692a7eb4304 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -195,6 +195,13 @@ config WDT_DAVINCI
 	  Select this to enable the watchdog timer for DaVinci SoCs such as the
 	  OMAP-L138.
 
+config WDT_GSC
+	bool "HPE GSC watchdog support"
+	depends on WDT
+	help
+	  Enable support for the watchdog timer in HPE GSC BMC SoC
+	  used in HPE Gen12 servers.
+
 config WDT_GPIO
 	bool "External gpio watchdog support"
 	depends on WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 02e2674f8af..f7397e03527 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
 obj-$(CONFIG_WDT_DA9063) += da9063-wdt.o
 obj-$(CONFIG_WDT_DAVINCI) += davinci_wdt.o
 obj-$(CONFIG_WDT_FTWDT010) += ftwdt010_wdt.o
+obj-$(CONFIG_WDT_GSC) += gsc_wdt.o
 obj-$(CONFIG_$(SPL_TPL_)WDT_GPIO) += gpio_wdt.o
 obj-$(CONFIG_WDT_MAX6370) += max6370_wdt.o
 obj-$(CONFIG_WDT_MCF) += mcf_wdt.o
diff --git a/drivers/watchdog/gsc_wdt.c b/drivers/watchdog/gsc_wdt.c
new file mode 100644
index 00000000000..b535f47e052
--- /dev/null
+++ b/drivers/watchdog/gsc_wdt.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (C) 2022-2025 Hewlett Packard Enterprise Development LP */
+
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <wdt.h>
+#include <asm/io.h>
+#include <linux/err.h>
+
+#define MASK_WDGCS_ENABLE	BIT(0)
+#define MASK_WDGCS_RELOAD	BIT(2)
+#define MASK_WDGCS_NMIEN	BIT(3)
+#define MASK_WDGCS_WARN		BIT(7)
+
+#define WDT_MAX_TIMEOUT_MS	655350
+#define SECS_TO_WDOG_TICKS(x)	((x) * 100)
+
+struct gsc_wdt_priv {
+	void __iomem *counter;
+	void __iomem *control;
+};
+
+static int gsc_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+	struct gsc_wdt_priv *priv = dev_get_priv(dev);
+	u8 val;
+	u16 timeout_secs;
+
+	if (timeout_ms > WDT_MAX_TIMEOUT_MS)
+		timeout_ms = WDT_MAX_TIMEOUT_MS;
+	else if (timeout_ms == 0)
+		timeout_ms = CONFIG_WATCHDOG_TIMEOUT_MSECS;
+
+	timeout_secs = timeout_ms / 1000;
+	writew(SECS_TO_WDOG_TICKS(timeout_secs), priv->counter);
+
+	val = readb(priv->control);
+	val |= MASK_WDGCS_ENABLE;
+	writeb(val, priv->control);
+
+	return 0;
+}
+
+static int gsc_wdt_stop(struct udevice *dev)
+{
+	struct gsc_wdt_priv *priv = dev_get_priv(dev);
+	u8 val;
+
+	val = readb(priv->control);
+	val &= ~MASK_WDGCS_ENABLE;
+	writeb(val, priv->control);
+
+	return 0;
+}
+
+static int gsc_wdt_reset(struct udevice *dev)
+{
+	struct gsc_wdt_priv *priv = dev_get_priv(dev);
+	u8 val;
+
+	val = readb(priv->control);
+	val |= MASK_WDGCS_RELOAD;
+	writeb(val, priv->control);
+
+	return 0;
+}
+
+static int gsc_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+	return gsc_wdt_start(dev, 1, flags);
+}
+
+static const struct wdt_ops gsc_wdt_ops = {
+	.start = gsc_wdt_start,
+	.reset = gsc_wdt_reset,
+	.stop = gsc_wdt_stop,
+	.expire_now = gsc_wdt_expire_now,
+};
+
+static const struct udevice_id gsc_wdt_ids[] = {
+	{ .compatible = "hpe,gsc-wdt" },
+	{ }
+};
+
+static int gsc_wdt_probe(struct udevice *dev)
+{
+	struct gsc_wdt_priv *priv = dev_get_priv(dev);
+
+	priv->counter = dev_remap_addr_index(dev, 0);
+	if (!priv->counter)
+		return -EINVAL;
+
+	priv->control = dev_remap_addr_index(dev, 1);
+	if (!priv->control)
+		return -EINVAL;
+
+	gsc_wdt_stop(dev);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(gsc_wdt) = {
+	.name = "gsc_wdt",
+	.id = UCLASS_WDT,
+	.of_match = gsc_wdt_ids,
+	.probe = gsc_wdt_probe,
+	.priv_auto = sizeof(struct gsc_wdt_priv),
+	.ops = &gsc_wdt_ops,
+};

-- 
2.43.0

[PATCH 5/9] misc: Add HPE GSC memory-mapped EEPROM driver

[Jorge Cisneros]

Add a driver for the HPE GSC memory-mapped virtual EEPROM. This
device provides access to system VPD (Vital Product Data) including
MAC addresses, serial numbers, and part numbers through a simple
memory-mapped interface.

The driver registers as UCLASS_I2C_EEPROM for compatibility with
the standard EEPROM read/write API and includes checksum validation
to detect data corruption.

Signed-off-by: Jorge Cisneros <jorge.cisneros@hpe.com>
---
 drivers/misc/Kconfig          |   7 +++
 drivers/misc/Makefile         |   1 +
 drivers/misc/gsc_mem_eeprom.c | 118 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 126 insertions(+)

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index a0aa290480e..5d316b03ec7 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -573,6 +573,13 @@ config SPL_I2C_EEPROM
 	  This option is an SPL-variant of the I2C_EEPROM option.
 	  See the help of I2C_EEPROM for details.
 
+config GSC_MEMEEPROM
+	bool "HPE GSC memory-mapped EEPROM driver"
+	depends on MISC
+	help
+	  Support for HPE GSC memory-mapped EEPROM used for storing
+	  VPD (Vital Product Data) in HPE Gen12 server BMCs.
+
 config SYS_I2C_EEPROM_ADDR
 	hex "Chip address of the EEPROM device"
 	depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 1d950f7a0ab..e616b9f67d2 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o
 obj-$(CONFIG_IRQ) += irq-uclass.o
 obj-$(CONFIG_SANDBOX) += irq_sandbox.o irq_sandbox_test.o
 obj-$(CONFIG_$(PHASE_)I2C_EEPROM) += i2c_eeprom.o
+obj-$(CONFIG_GSC_MEMEEPROM) += gsc_mem_eeprom.o
 obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
 obj-$(CONFIG_IMX8) += imx8/
 obj-$(CONFIG_IMX_ELE) += imx_ele/
diff --git a/drivers/misc/gsc_mem_eeprom.c b/drivers/misc/gsc_mem_eeprom.c
new file mode 100644
index 00000000000..f67662fe40b
--- /dev/null
+++ b/drivers/misc/gsc_mem_eeprom.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * HPE GSC memory-mapped EEPROM driver
+ *
+ * (C) Copyright 2025 Hewlett Packard Enterprise Development LP.
+ */
+
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <i2c_eeprom.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+struct memory_eeprom_priv {
+	u64 mem_offset;
+	int size;
+};
+
+static int validate_checksum(u8 *data)
+{
+	u16 sum = 0;
+	u16 word;
+	u8 rev;
+	int i;
+
+	rev = readb(data);
+	switch (rev) {
+	case 2:
+	case 3:
+		for (i = 0; i < 64; i++) {
+			memcpy(&word, data, sizeof(word));
+			data += sizeof(word);
+			sum += word;
+		}
+		if (sum == 0)
+			return 1;
+		debug("%s - Computed checksum fails 0x%04x\n", __func__, sum);
+		break;
+	default:
+		debug("%s - Version byte 0x%02x unsupported.\n", __func__, rev);
+	}
+	return 0;
+}
+
+static int mem_eeprom_read(struct udevice *dev, int offset, u8 *buf,
+			   int size)
+{
+	struct memory_eeprom_priv *priv = dev_get_priv(dev);
+	u8 *ptr;
+
+	ptr = map_physmem(priv->mem_offset, priv->size, MAP_NOCACHE);
+	if (!ptr) {
+		printf("%s - failed to map physical memory.\n", __func__);
+		return -ENODEV;
+	}
+
+	if (size + offset > priv->size) {
+		unmap_physmem(ptr, MAP_NOCACHE);
+		return -ENOSYS;
+	}
+
+	memcpy(buf, &ptr[offset], size);
+	unmap_physmem(ptr, MAP_NOCACHE);
+
+	return 0;
+}
+
+static const struct i2c_eeprom_ops i2c_mem_eeprom_ops = {
+	.read = mem_eeprom_read,
+};
+
+static const struct udevice_id i2c_mem_eeprom_ids[] = {
+	{ .compatible = "i2c_gsc_mem_eeprom" },
+	{ }
+};
+
+static int i2c_mem_eeprom_probe(struct udevice *dev)
+{
+	struct memory_eeprom_priv *priv = dev_get_priv(dev);
+	u8 *ptr;
+	u8 crc1, crc2;
+	u32 reg[2];
+	int ret;
+
+	ret = dev_read_u32_array(dev, "reg", reg, 2);
+	if (ret) {
+		printf("Error reading reg from DT: %d\n", ret);
+		return ret;
+	}
+	priv->mem_offset = reg[0];
+	priv->size = reg[1];
+
+	ptr = map_physmem(priv->mem_offset, priv->size, MAP_NOCACHE);
+	if (!ptr) {
+		printf("%s failed to map physical memory.\n", __func__);
+		return -ENODEV;
+	}
+
+	crc1 = validate_checksum(ptr);
+	crc2 = validate_checksum(ptr + 128);
+	unmap_physmem(ptr, MAP_NOCACHE);
+
+	if (crc1 != 1 || crc2 != 1) {
+		printf("%s - Warning: Invalid checksum\n", __func__);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+U_BOOT_DRIVER(i2c_gsc_memeeprom) = {
+	.name = "gsc_mem_eeprom",
+	.id = UCLASS_I2C_EEPROM,
+	.of_match = i2c_mem_eeprom_ids,
+	.probe = i2c_mem_eeprom_probe,
+	.ops = &i2c_mem_eeprom_ops,
+	.priv_auto = sizeof(struct memory_eeprom_priv),
+};

-- 
2.43.0

[PATCH 6/9] net: macb: Add HPE GSC GEM Ethernet support

[Jorge Cisneros]

Add support for the HPE GSC SoC's Cadence GEM Ethernet MAC. The GSC
integrates a GEM controller with SGMII interface, gigabit capability,
jumbo frames, and PTP timestamping support.

The GSC GEM instance does not require software clock initialization
as clocking is handled by the SoC integration layer, so the clock
init callback is a no-op.

Signed-off-by: Jorge Cisneros <jorge.cisneros@hpe.com>
---
 drivers/net/macb.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index cbf5f605518..c1e7044e7bb 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -619,6 +619,12 @@ static int macb_sama7g5_clk_init(struct udevice *dev, ulong rate)
 	return clk_enable(&clk);
 }
 
+static int macb_gsc_clk_init(struct udevice *dev, ulong rate)
+{
+	/* Clock is handled by the GSC IP block, no programming needed */
+	return 0;
+}
+
 int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
 {
 #ifdef CONFIG_CLK
@@ -1360,6 +1366,15 @@ static const struct macb_config sama7g5_emac_config = {
 	.usrio = &sama7g5_usrio,
 };
 
+static const struct macb_config gsc_config = {
+	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
+		MACB_CAPS_JUMBO | MACB_CAPS_GEM_HAS_PTP,
+	.dma_burst_length = 8,
+	.hw_dma_cap = HW_DMA_CAP_32B,
+	.clk_init = macb_gsc_clk_init,
+	.usrio = &macb_default_usrio,
+};
+
 static const struct udevice_id macb_eth_ids[] = {
 	{ .compatible = "cdns,macb" },
 	{ .compatible = "cdns,at91sam9260-macb" },
@@ -1374,6 +1389,8 @@ static const struct udevice_id macb_eth_ids[] = {
 	{ .compatible = "cdns,zynq-gem" },
 	{ .compatible = "sifive,fu540-c000-gem",
 	  .data = (ulong)&sifive_config },
+	{ .compatible = "hpe,gsc-gem",
+	  .data = (ulong)&gsc_config },
 	{ }
 };
 

-- 
2.43.0

[PATCH 7/9] board: hpe: Add GSC board support

[Jorge Cisneros]

Add board support for the HPE GSC (Gen Server Controller), the BMC
SoC used in HPE Gen12 ProLiant and Synergy servers.

Board files include:
- gsc_board.c: Board init, DRAM sizing from Denali memory controller,
  MAC address provisioning from memory-mapped EEPROM, and FDT fixups
  for network configuration based on CPLD xregisters
- common-phy.c: Shared Ethernet/DisplayPort PHY initialization with
  configurable transmitter amplitude and de-emphasis
- server_id.c: Custom command to read server identification from CPLD
- gsc.env: Default SPI flash boot environment
- gsc.h: Board configuration header with GICv3 and spin-table addresses

Signed-off-by: Jorge Cisneros <jorge.cisneros@hpe.com>
---
 board/hpe/gsc/Makefile                       |   3 +
 board/hpe/gsc/common-phy-wrapper-addresses.h |  86 +++++
 board/hpe/gsc/common-phy.c                   | 296 +++++++++++++++
 board/hpe/gsc/common-phy.h                   |   8 +
 board/hpe/gsc/gsc.env                        |   9 +
 board/hpe/gsc/gsc_board.c                    | 538 +++++++++++++++++++++++++++
 board/hpe/gsc/server_id.c                    |  51 +++
 include/configs/gsc.h                        |  25 ++
 8 files changed, 1016 insertions(+)

diff --git a/board/hpe/gsc/Makefile b/board/hpe/gsc/Makefile
new file mode 100644
index 00000000000..bc14c9d3bbf
--- /dev/null
+++ b/board/hpe/gsc/Makefile
@@ -0,0 +1,3 @@
+obj-y += gsc_board.o
+obj-y += common-phy.o
+obj-y += server_id.o
diff --git a/board/hpe/gsc/common-phy-wrapper-addresses.h b/board/hpe/gsc/common-phy-wrapper-addresses.h
new file mode 100644
index 00000000000..50bacd756f2
--- /dev/null
+++ b/board/hpe/gsc/common-phy-wrapper-addresses.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Copyright (C) 2022-2025 Hewlett-Packard Enterprise Development Company, L.P. */
+
+#ifndef _COMMON_PHY_WRAPPER_ADDRESSES_H
+#define _COMMON_PHY_WRAPPER_ADDRESSES_H
+
+#define kWRAP_CDB_ENABLE		0x8018
+#define kWRAP_CDB_BUSSEL		0x801c
+#define kWRAP_CDB_ACC_OK		0x8020
+#define kWRAP_CDB_REG_INIT_END		0x8024
+
+#define kWRAP_PHY_REFCLK_ACTIVE		0x803c
+#define kWRAP_PHY_CONFIG_RSTN		0x8040
+#define kWRAP_PHY_CMN_READY		0x8044
+#define kWRAP_PHY_LANE_EN_BITS		0x8048
+#define kWRAP_PHY_LANE_RSTN_BITS	0x804c
+
+#define kWRAP_PHY_PLL0_ENABLE		0x8050
+#define kWRAP_PHY_PLL0_STATUS		0x8054
+
+#define kWRAP_PHY_PLL1_ENABLE		0x8058
+#define kWRAP_PHY_PLL1_STATUS		0x805c
+
+#define kWRAP_PHY_DP_LANE_MODE		0x8060
+#define kWRAP_PHY_DP_LANESET_READY	0x8064
+#define kWRAP_LANE_ELEC_IDLE_BITS	0x8070
+#define kWRAP_DP_DUAL_MODE_ENABLE	0x8074
+#define kWRAP_PHY_DP_LINK_RATE		0x8078
+#define kWRAP_DISABLE_AUTO_RXLINK	0x807c
+
+#define kWRAP_TX_DEEMPH_LANE0		0x8080
+#define kWRAP_TX_DEEMPH_LANE1		0x8084
+#define kWRAP_TX_DEEMPH_LANE2		0x8088
+#define kWRAP_TX_DEEMPH_LANE3		0x808c
+
+#define kWRAP_TX_VMARGIN_LANE0		0x8090
+#define kWRAP_TX_VMARGIN_LANE1		0x8094
+#define kWRAP_TX_VMARGIN_LANE2		0x8098
+#define kWRAP_TX_VMARGIN_LANE3		0x809c
+
+#define kWRAP_XCVR_PLLCLK0_ENABLE	0x80a0
+#define kWRAP_XCVR_PLLCLK1_ENABLE	0x80a4
+#define kWRAP_XCVR_PLLCLK2_ENABLE	0x80a8
+#define kWRAP_XCVR_PLLCLK3_ENABLE	0x80ac
+
+#define kWRAP_XCVR_PLLCLK0_EN_ACK	0x80b0
+#define kWRAP_XCVR_PLLCLK1_EN_ACK	0x80b4
+#define kWRAP_XCVR_PLLCLK2_EN_ACK	0x80b8
+#define kWRAP_XCVR_PLLCLK3_EN_ACK	0x80bc
+
+#define kWRAP_XCVR_RATE_CHNG0_REQ	0x80c0
+#define kWRAP_XCVR_RATE_CHNG1_REQ	0x80c4
+#define kWRAP_XCVR_RATE_CHNG2_REQ	0x80c8
+#define kWRAP_XCVR_RATE_CHNG3_REQ	0x80cc
+
+#define kWRAP_XCVR_RATE_CHNG0_ACK	0x80d0
+#define kWRAP_XCVR_RATE_CHNG1_ACK	0x80d4
+#define kWRAP_XCVR_RATE_CHNG2_ACK	0x80d8
+#define kWRAP_XCVR_RATE_CHNG3_ACK	0x80dc
+
+#define kWRAP_XCVR_MODE_LANE0		0x80e0
+#define kWRAP_XCVR_MODE_LANE1		0x80e4
+#define kWRAP_XCVR_MODE_LANE2		0x80e8
+#define kWRAP_XCVR_MODE_LANE3		0x80ec
+
+#define kWRAP_PHY_RX_DATA_ENABLE	0x80f0
+#define kWRAP_PHY_TX_DATA_ENABLE	0x80f4
+
+#define kWRAP_PHY_XCVR0_SCANIN0	0x8100
+#define kWRAP_PHY_XCVR0_SCANIN1	0x8104
+#define kWRAP_PHY_XCVR1_SCANIN0	0x8108
+#define kWRAP_PHY_XCVR1_SCANIN1	0x810c
+#define kWRAP_PHY_XCVR2_SCANIN0	0x8110
+#define kWRAP_PHY_XCVR2_SCANIN1	0x8114
+#define kWRAP_PHY_XCVR3_SCANIN0	0x8118
+#define kWRAP_PHY_XCVR3_SCANIN1	0x811c
+#define kWRAP_PHY_XCVR0_SCANOUT0	0x8120
+#define kWRAP_PHY_XCVR0_SCANOUT1	0x8124
+#define kWRAP_PHY_XCVR1_SCANOUT0	0x8128
+#define kWRAP_PHY_XCVR1_SCANOUT1	0x812c
+#define kWRAP_PHY_XCVR2_SCANOUT0	0x8130
+#define kWRAP_PHY_XCVR2_SCANOUT1	0x8134
+#define kWRAP_PHY_XCVR3_SCANOUT0	0x8138
+#define kWRAP_PHY_XCVR3_SCANOUT1	0x813c
+
+#endif /* _COMMON_PHY_WRAPPER_ADDRESSES_H */
diff --git a/board/hpe/gsc/common-phy.c b/board/hpe/gsc/common-phy.c
new file mode 100644
index 00000000000..c39653727e9
--- /dev/null
+++ b/board/hpe/gsc/common-phy.c
@@ -0,0 +1,296 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (C) 2022-2025 Hewlett-Packard Enterprise Development Company, L.P. */
+
+#include <dm.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+#include "common-phy-wrapper-addresses.h"
+
+#define DP_TX_BASE			0xc0020000
+#define PHY_PIP_CONFIG_REG_INDEX_ADDR	0x0FC0
+#define PHY_PIP_CONFIG_REG_DATA_ADDR	0x0FC4
+
+/*
+ * Xreg 0x39 Layout - Transmitter Amplitude
+ *
+ * Bits | Desc
+ *  7   | Secondary Transmitter Disable
+ * 6:4  | Secondary Transmitter Amplitude
+ *  3   | Primary Transmitter Disable
+ * 2:0  | Primary Transmitter Amplitude
+ */
+#define V_AMPLT_400		0x4
+#define V_AMPLT_600		0x5
+#define V_AMPLT_800		0x6
+#define V_AMPLT_945		0x7
+
+/* Xreg 0x38 De-emphasis Levels */
+#define DE_EMPH_0		0x0
+#define DE_EMPH_1		0x1
+#define DE_EMPH_2		0x2
+#define DE_EMPH_3		0x3
+
+/* Xreg Mask and Shift */
+#define V_AMPLT_MASK			0x7
+#define DE_EMPH_MASK			0x3
+#define DISABLE_MASK			0x8
+#define SECONDARY_SHIFT_V_AMPLT		0x4
+#define SECONDARY_SHIFT_DE_EMPH		0x2
+
+static void common_phy_register_write(unsigned int reg, unsigned int data)
+{
+	writel(reg, DP_TX_BASE + PHY_PIP_CONFIG_REG_INDEX_ADDR);
+	writel(data, DP_TX_BASE + PHY_PIP_CONFIG_REG_DATA_ADDR);
+}
+
+static void common_phy_register_read(unsigned int reg, unsigned int *data)
+{
+	writel(reg, DP_TX_BASE + PHY_PIP_CONFIG_REG_INDEX_ADDR);
+	*data = readl(DP_TX_BASE + PHY_PIP_CONFIG_REG_DATA_ADDR);
+}
+
+static int poll_register(unsigned int reg, int value)
+{
+	unsigned int data = 0;
+	int retry_cnt = 20;
+
+	while (retry_cnt > 0) {
+		common_phy_register_read(reg, &data);
+		if (data == value)
+			return 0;
+		mdelay(1);
+		retry_cnt--;
+	}
+
+	pr_err("CommonPhy: polling failed: reg=0x%x expected=0x%x got=0x%x\n",
+	       reg, value, data);
+	return -1;
+}
+
+static void common_phy_get_deemph_and_vamplitude(unsigned int amplt,
+						  unsigned int emph,
+						  unsigned int *reg_amplt,
+						  unsigned int *reg_emph)
+{
+	/* Default: 400 mV, de-emphasis level 0 */
+	*reg_amplt = 0x00040404;
+	*reg_emph = 0x00000000;
+
+	if (emph > DE_EMPH_3) {
+		pr_err("CommonPhy: invalid config: amplitude 0x%x, de-emph 0x%x\n",
+		       amplt, emph);
+		return;
+	}
+
+	if (amplt == V_AMPLT_400) {
+		if (emph == DE_EMPH_0) {
+			*reg_amplt = 0x00040404;
+			*reg_emph = 0x00000000;
+		} else if (emph == DE_EMPH_1) {
+			*reg_amplt = 0x00030303;
+			*reg_emph = 0x00030404;
+		} else if (emph == DE_EMPH_2) {
+			*reg_amplt = 0x00010101;
+			*reg_emph = 0x00050606;
+		} else if (emph == DE_EMPH_3) {
+			*reg_amplt = 0x00000000;
+			*reg_emph = 0x00060606;
+		}
+	} else if (amplt == V_AMPLT_600) {
+		if (emph == DE_EMPH_0) {
+			*reg_amplt = 0x00030303;
+			*reg_emph = 0x00000000;
+		} else if (emph == DE_EMPH_1) {
+			*reg_amplt = 0x00000000;
+			*reg_emph = 0x00030404;
+		} else if (emph == DE_EMPH_2) {
+			*reg_amplt = 0x00000000;
+			*reg_emph = 0x00050606;
+		} else if (emph == DE_EMPH_3) {
+			*reg_amplt = 0x00000000;
+			*reg_emph = 0x00060606;
+		}
+	} else if (amplt == V_AMPLT_800) {
+		if (emph == DE_EMPH_0) {
+			*reg_amplt = 0x00040404;
+			*reg_emph = 0x00010101;
+		} else if (emph == DE_EMPH_1) {
+			*reg_amplt = 0x00000000;
+			*reg_emph = 0x00030404;
+		} else if (emph == DE_EMPH_2) {
+			*reg_amplt = 0x00000000;
+			*reg_emph = 0x00050606;
+		} else if (emph == DE_EMPH_3) {
+			*reg_amplt = 0x00000000;
+			*reg_emph = 0x00060606;
+		}
+	} else if (amplt == V_AMPLT_945) {
+		if (emph == DE_EMPH_0) {
+			*reg_amplt = 0x00000000;
+			*reg_emph = 0x00000000;
+		} else if (emph == DE_EMPH_1) {
+			*reg_amplt = 0x00000000;
+			*reg_emph = 0x00030404;
+		} else if (emph == DE_EMPH_2) {
+			*reg_amplt = 0x00000000;
+			*reg_emph = 0x00050606;
+		} else if (emph == DE_EMPH_3) {
+			*reg_amplt = 0x00000000;
+			*reg_emph = 0x00060606;
+		}
+	} else {
+		pr_err("CommonPhy: invalid config: amplitude 0x%x, de-emph 0x%x\n",
+		       amplt, emph);
+	}
+}
+
+/*
+ * Power On Initialization of Common PHY.
+ * Configures the shared PHY for Ethernet and Display Port operation.
+ */
+int common_phy_poweron_init(void)
+{
+	unsigned int xreg_amplt, xreg_emph, emph, amplt;
+	unsigned int rstn_bits = 0x0F;
+
+	/* 1. Clear registers to default un-initialized state */
+	common_phy_register_write(kWRAP_PHY_RX_DATA_ENABLE, 0x00);
+	common_phy_register_write(kWRAP_PHY_TX_DATA_ENABLE, 0x00);
+	common_phy_register_write(kWRAP_PHY_LANE_RSTN_BITS, 0x00);
+	common_phy_register_write(kWRAP_PHY_LANE_EN_BITS, 0x00);
+	common_phy_register_write(kWRAP_PHY_CONFIG_RSTN, 0x00);
+	common_phy_register_write(kWRAP_LANE_ELEC_IDLE_BITS, 0x0F);
+	common_phy_register_write(kWRAP_PHY_PLL0_ENABLE, 0x00);
+	common_phy_register_write(kWRAP_PHY_PLL1_ENABLE, 0x00);
+	common_phy_register_write(kWRAP_CDB_BUSSEL, 0x00);
+	common_phy_register_write(kWRAP_CDB_REG_INIT_END, 0x00);
+	common_phy_register_write(kWRAP_PHY_DP_LANE_MODE, 0x00);
+	common_phy_register_write(kWRAP_DISABLE_AUTO_RXLINK, 0x01);
+	common_phy_register_write(kWRAP_XCVR_MODE_LANE0, 0x00);
+	common_phy_register_write(kWRAP_XCVR_MODE_LANE1, 0x00);
+	common_phy_register_write(kWRAP_XCVR_MODE_LANE2, 0x00);
+	common_phy_register_write(kWRAP_XCVR_MODE_LANE3, 0x00);
+
+	/* 2. Release PHY lanes out of reset */
+	common_phy_register_write(kWRAP_PHY_CONFIG_RSTN, 0x01);
+
+	/* 3. Poll for internal initialization completion */
+	if (poll_register(kWRAP_CDB_ACC_OK, 0x01) != 0) {
+		pr_err("CommonPhy: kWRAP_CDB_ACC_OK polling failed\n");
+		return -1;
+	}
+
+	/* 4. Additional PHY register modifications */
+	common_phy_register_write(kWRAP_CDB_BUSSEL, 0x01);
+	common_phy_register_write(kWRAP_CDB_ENABLE, 0x01);
+
+	/* Set DP lanes for Dual Mode */
+	common_phy_register_write(0x4021, 0x00);
+	common_phy_register_write(0x4221, 0x00);
+
+	/* RX Lane Fixes B0 */
+	common_phy_register_write(0x4026, 0x124A);
+	common_phy_register_write(0x4226, 0x124A);
+	common_phy_register_write(0x4226, 0x124A);
+	common_phy_register_write(0x4626, 0x124A);
+
+	common_phy_register_write(kWRAP_CDB_BUSSEL, 0x00);
+	common_phy_register_write(kWRAP_CDB_ENABLE, 0x00);
+
+	/* 5. Set PHY initialization complete */
+	common_phy_register_write(kWRAP_CDB_REG_INIT_END, 0x01);
+
+	/* 6. Enable PLL 0 and PLL 1 */
+	common_phy_register_write(kWRAP_PHY_PLL0_ENABLE, 0x01);
+	common_phy_register_write(kWRAP_PHY_PLL1_ENABLE, 0x01);
+
+	/* 7. Program vswing/pre-emphasis for DP lanes 0 and 1 */
+	common_phy_register_write(kWRAP_TX_VMARGIN_LANE0, 0x00040404);
+	common_phy_register_write(kWRAP_TX_VMARGIN_LANE1, 0x00040404);
+	common_phy_register_write(kWRAP_TX_DEEMPH_LANE0, 0x00000000);
+	common_phy_register_write(kWRAP_TX_DEEMPH_LANE1, 0x00000000);
+
+	/* 8. Program vswing/pre-emphasis for Ethernet lanes 2 and 3 */
+	xreg_amplt = readb(0xd1000039);
+	xreg_emph = readb(0xd1000038);
+
+	debug("CommonPhy: amplitude=0x%x de-emph=0x%x\n",
+	      xreg_amplt, xreg_emph);
+
+	/* Primary transmitter */
+	if ((xreg_amplt & DISABLE_MASK) == 0) {
+		debug("CommonPhy: configuring primary transmitter\n");
+		common_phy_get_deemph_and_vamplitude(
+			xreg_amplt & V_AMPLT_MASK,
+			xreg_emph & DE_EMPH_MASK,
+			&amplt, &emph);
+		common_phy_register_write(kWRAP_TX_VMARGIN_LANE2, amplt);
+		common_phy_register_write(kWRAP_TX_DEEMPH_LANE2, emph);
+	} else {
+		debug("CommonPhy: primary transmitter disabled\n");
+		rstn_bits &= 0x0B;
+	}
+
+	/* Secondary transmitter */
+	if (((xreg_amplt >> SECONDARY_SHIFT_V_AMPLT) & DISABLE_MASK) == 0) {
+		debug("CommonPhy: configuring secondary transmitter\n");
+		common_phy_get_deemph_and_vamplitude(
+			(xreg_amplt >> SECONDARY_SHIFT_V_AMPLT) & V_AMPLT_MASK,
+			(xreg_emph >> SECONDARY_SHIFT_DE_EMPH) & DE_EMPH_MASK,
+			&amplt, &emph);
+		common_phy_register_write(kWRAP_TX_VMARGIN_LANE3, amplt);
+		common_phy_register_write(kWRAP_TX_DEEMPH_LANE3, emph);
+	} else {
+		debug("CommonPhy: secondary transmitter disabled\n");
+		rstn_bits &= 0x07;
+	}
+
+	/* 9. Take lanes out of Electrical Idle */
+	common_phy_register_write(kWRAP_LANE_ELEC_IDLE_BITS, 0x0);
+
+	/* 10. Enable PLL Clocks */
+	common_phy_register_write(kWRAP_XCVR_PLLCLK0_ENABLE, 0x01);
+	common_phy_register_write(kWRAP_XCVR_PLLCLK2_ENABLE, 0x01);
+	common_phy_register_write(kWRAP_XCVR_PLLCLK3_ENABLE, 0x01);
+
+	/* 11. Release lane resets */
+	common_phy_register_write(kWRAP_PHY_LANE_RSTN_BITS, rstn_bits);
+
+	/* 12. Enable Lanes (DisplayPort only) */
+	common_phy_register_write(kWRAP_PHY_LANE_EN_BITS, 0x0F);
+
+	/* 13. Poll for Common Ready */
+	if (poll_register(kWRAP_PHY_CMN_READY, 0x01) != 0) {
+		pr_err("CommonPhy: kWRAP_PHY_CMN_READY polling failed\n");
+		return -1;
+	}
+
+	/* 14. Poll for PLL status */
+	if (poll_register(kWRAP_XCVR_PLLCLK0_EN_ACK, 0x01) != 0) {
+		pr_err("CommonPhy: PLLCLK0_EN_ACK polling failed\n");
+		return -1;
+	}
+	if (poll_register(kWRAP_XCVR_PLLCLK1_EN_ACK, 0x01) != 0) {
+		pr_err("CommonPhy: PLLCLK1_EN_ACK polling failed\n");
+		return -1;
+	}
+	if (poll_register(kWRAP_XCVR_PLLCLK2_EN_ACK, 0x01) != 0) {
+		pr_err("CommonPhy: PLLCLK2_EN_ACK polling failed\n");
+		return -1;
+	}
+
+	/* 15. Poll for Lanes ready */
+	if (poll_register(kWRAP_PHY_DP_LANESET_READY, 0x0F) != 0) {
+		pr_err("CommonPhy: DP_LANESET_READY polling failed\n");
+		return -1;
+	}
+
+	/* 16. Enable TX data flow */
+	common_phy_register_write(kWRAP_PHY_TX_DATA_ENABLE, 0x01);
+
+	/* 17. Set DP Link Rate to 1.62 Gbps */
+	common_phy_register_write(kWRAP_PHY_DP_LINK_RATE, 0x6);
+
+	return 0;
+}
diff --git a/board/hpe/gsc/common-phy.h b/board/hpe/gsc/common-phy.h
new file mode 100644
index 00000000000..bb41ea21ffa
--- /dev/null
+++ b/board/hpe/gsc/common-phy.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _COMMON_PHY_H
+#define _COMMON_PHY_H
+
+int common_phy_poweron_init(void);
+
+#endif /* _COMMON_PHY_H */
diff --git a/board/hpe/gsc/gsc.env b/board/hpe/gsc/gsc.env
new file mode 100644
index 00000000000..9723c30ba40
--- /dev/null
+++ b/board/hpe/gsc/gsc.env
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+loadfit=sf probe;sf read 0x2000000 0x1a0000 0xa00000;
+recover_cmd=bootm 0xfc1a0000;
+spiboot=run loadfit; saveenv; bootm 0x2000000;
+run recover_cmd;
+while itest 0 < 1; do
+	echo KERNEL BOOT FAILURE!;
+done;
diff --git a/board/hpe/gsc/gsc_board.c b/board/hpe/gsc/gsc_board.c
new file mode 100644
index 00000000000..bc86fd07485
--- /dev/null
+++ b/board/hpe/gsc/gsc_board.c
@@ -0,0 +1,538 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (C) 2019-2025 Hewlett-Packard Enterprise Development Company, L.P.
+
+#include <dm.h>
+#include <env.h>
+#include <ram.h>
+#include <timer.h>
+#include <asm/io.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <dm/uclass.h>
+#include <console.h>
+#include <asm/armv8/mmu.h>
+#include <fdt_support.h>
+#include <phy.h>
+#include <net.h>
+#include <i2c_eeprom.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ARCH_TIMER_CNTCR_REG	0xc0034000
+#define ARCH_TIMER_CNTFID0	0xc0034020
+#define ARCH_TIMER_FREQUENCY	50000000
+#define ARCH_TIMER_CNTCR_ENABLE	BIT(0)
+#define ARCH_TIMER_CNTCR_HDBG	BIT(1)
+
+#define DEFAULT_RESERVED_MEMORY_SIZE	(0x300000u)
+#define DEFAULT_VIDEO_RAM_SIZE		(0x1000000u)
+#define DENALI_ROW_DIFF			(0xCEFE219C)
+#define DENALI_ECC_ENABLE_DISABLE	(0xCEFE2134)
+#define DENALI_NON_ECC_REGION_ENABLED	(0xCEFE2170)
+#define DENALI_REG_NONECC_REGION_ONE	(0xCEFE2168)
+#define DENALI_REG_NONECC_REGION_TWO	(0xCEFE216C)
+#define VMEMOFF_ADDRESS			(0xc000001c)
+#define VIDEOMEM_ARRAY_SIZE		(7u)
+#define V_EEPROM_RO_START		(128)
+#define V_EEPROM_RO_MAC0		(V_EEPROM_RO_START + 4)
+#define V_EEPROM_RO_MAC1		(V_EEPROM_RO_START + 10)
+#define V_EEPROM_RO_SN			(1)
+#define V_EEPROM_RO_PN			(109)
+#define V_EEPROM_RO_PCA_SN		(144)
+#define V_EEPROM_RO_PCA_PN		(160)
+#define SSTRAP				0xc0000af0
+#define MEMID_BYTE_4			0xd1e10004
+#define MEMCGF_ADDRESS			0xc0000024
+
+#define GSC_MACB0		"/ahb/ethernet@c0004000/"
+#define GSC_MACB2		"/ahb/ethernet@c0006000/"
+#define GSC_MACB0_ETHERNET_PHY	"/ahb/ethernet@c0004000/ethernet-phy@0/"
+#define GSC_MACB2_ETHERNET_PHY	"/ahb/ethernet@c0006000/ethernet-phy@0/"
+#define GSC_I3C_HUB_PORT_0	"/ahb/i3c@c0003300/hub@0,0/target-port@0/"
+#define GSC_I3C_HUB_PORT_1	"/ahb/i3c@c0003300/hub@0,0/target-port@1/"
+#define GSC_I3C_HUB_PORT_2	"/ahb/i3c@c0003300/hub@0,0/target-port@2/"
+#define GSC_I3C_HUB_PORT_3	"/ahb/i3c@c0003300/hub@0,0/target-port@3/"
+
+/* Xregister Network Configuration Definitions v0x25 */
+#define GSC_PRIMARY_SECONDARY_CFG	0xd1000038
+#define GSC_SECONDARY_MAC_SHIFT		4
+#define GSC_SECONDARY_MAC_MASK		0x30
+#define GSC_PRIMARY_MAC_SHIFT		6
+#define GSC_PRIMARY_MAC_MASK		0xc0
+#define FAILOVER_SOFTSTRAP_MASK		0x6000
+#define GSC_PRIMARY_SECONDARY_PHY_TYPE	0xd100003b
+#define GSC_SECONDARY_TYPE_SHIFT	1
+#define GSC_SECONDARY_TYPE_MASK		0x0E
+#define GSC_PRIMARY_TYPE_SHIFT		4
+#define GSC_PRIMARY_TYPE_MASK		0x30
+#define GSC_PRIMARY_SPEED_DUPLEX	0xd100003c
+#define GSC_SECONDARY_SPEED_DUPLEX	0xd100003d
+#define GSC_DUPLEX_AUTO_MASK		0x08
+#define GSC_DUPLEX_FULL_MASK		0x04
+#define GSC_SPEED_AUTO_MASK		0x80
+#define GSC_SPEED_1000_MASK		0x40
+
+#include "common-phy.h"
+
+static int get_eeprom_val(uint offset, u8 *v_ptr, size_t len)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_first_device_err(UCLASS_I2C_EEPROM, &dev);
+	if (ret) {
+		debug("%s Uclass_first_device_err %d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = i2c_eeprom_read(dev, offset, v_ptr, len);
+	if (ret) {
+		debug("%s Read eeprom failure %d\n", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __ft_add_fixed_link(void *blob, int nodeoff)
+{
+	int rc;
+
+	nodeoff = fdt_add_subnode(blob, nodeoff, "fixed-link");
+	if (nodeoff < 0) {
+		pr_err("Failed to add fixed-link subnode %d\n", nodeoff);
+		return nodeoff;
+	}
+
+	rc = fdt_setprop_u32(blob, nodeoff, "speed", 1000);
+	if (rc < 0) {
+		pr_err("Failed to set speed property: %d\n", rc);
+		return rc;
+	}
+
+	rc = fdt_setprop(blob, nodeoff, "full-duplex", NULL, 0);
+	if (rc < 0) {
+		pr_err("Failed to set full-duplex property: %d\n", rc);
+		return rc;
+	}
+
+	return 0;
+}
+
+static int set_vpd_val(void *blob, uint offset, u8 *val, size_t len,
+		       char *name)
+{
+	int ret, i;
+	size_t str_len;
+	int actual_len = 0;
+
+	ret = get_eeprom_val(offset, val, len);
+	if (ret) {
+		pr_err("Failed to read %s from veeprom: %d\n", name, ret);
+		return ret;
+	}
+
+	for (i = 0; i < len - 1; i++) {
+		if (val[i] == '\0' || val[i] < 0x20 || val[i] > 0x7E) {
+			actual_len = i;
+			break;
+		}
+	}
+
+	if (actual_len == 0 && i == len - 1)
+		actual_len = len - 1;
+
+	val[actual_len] = '\0';
+	str_len = actual_len + 1;
+
+	ret = fdt_setprop(blob, fdt_path_offset(blob, "/"), name, val, str_len);
+	if (ret < 0) {
+		pr_err("Failed to set %s in DTB: %s\n", name,
+		       fdt_strerror(ret));
+		return ret;
+	}
+
+	return 0;
+}
+
+static int ft_board_setup_vpd(void *blob, struct bd_info *bd)
+{
+	if (IS_ENABLED(CONFIG_GSC_PATCH_KERNEL_DTS_VPD)) {
+		u8 val[16];
+
+		set_vpd_val(blob, V_EEPROM_RO_SN, val, 16, "sn");
+		set_vpd_val(blob, V_EEPROM_RO_PN, val, 16, "pn");
+		set_vpd_val(blob, V_EEPROM_RO_PCA_SN, val, 16, "serial-number");
+		set_vpd_val(blob, V_EEPROM_RO_PCA_PN, val, 16, "model");
+	}
+
+	return 0;
+}
+
+static int ft_board_config_i3c_hub(void *blob, struct bd_info *bd)
+{
+	static const char * const port_paths[] = {
+		GSC_I3C_HUB_PORT_0,
+		GSC_I3C_HUB_PORT_1,
+		GSC_I3C_HUB_PORT_2,
+		GSC_I3C_HUB_PORT_3,
+	};
+	u8 cpu;
+	int nodeoff, rc, i;
+
+	if (!IS_ENABLED(CONFIG_GSC_I3C_HUB_DT))
+		return 0;
+
+	cpu = readb(MEMID_BYTE_4);
+	if (cpu == 0) {
+		pr_err("Error: CPU Presence = 0\n");
+		return 0;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(port_paths); i++) {
+		if (cpu & BIT(i))
+			continue;
+
+		nodeoff = fdt_path_offset(blob, port_paths[i]);
+		if (nodeoff < 0) {
+			pr_err("Failed to find I3C hub port %d\n", i);
+			continue;
+		}
+
+		rc = fdt_del_node(blob, nodeoff);
+		if (rc < 0)
+			pr_err("Failed to delete I3C hub port %d: %d\n", i, rc);
+	}
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int rc, nodeoff;
+	unsigned int tmp;
+	u8 val;
+	u8 mac2_is_primary = 0;
+
+	rc = ft_board_config_i3c_hub(blob, bd);
+	if (rc)
+		pr_err("I3C Hub DT Adjustment failed: %d\n", rc);
+
+	tmp = readl(SSTRAP);
+
+	if (tmp & FAILOVER_SOFTSTRAP_MASK) {
+		val = (readb(GSC_PRIMARY_SECONDARY_CFG) & GSC_PRIMARY_MAC_MASK)
+				>> GSC_PRIMARY_MAC_SHIFT;
+		if (val == 0x00) {
+			val = (readb(GSC_PRIMARY_SECONDARY_PHY_TYPE) &
+					GSC_PRIMARY_TYPE_MASK)
+					>> GSC_PRIMARY_TYPE_SHIFT;
+			if (val == 0x01) {
+				nodeoff = fdt_path_offset(blob, GSC_MACB0);
+				if (nodeoff < 0) {
+					pr_err("Failed to find macb0 node\n");
+					return 0;
+				}
+
+				rc = fdt_delprop(blob, nodeoff, "phy-handle");
+				if (rc < 0) {
+					pr_err("Failed to delete phy-handle\n");
+					return 0;
+				}
+
+				nodeoff = fdt_path_offset(blob, GSC_MACB0_ETHERNET_PHY);
+				if (nodeoff < 0) {
+					pr_err("Failed to find macb0 phy node\n");
+					return 0;
+				}
+
+				rc = fdt_del_node(blob, nodeoff);
+				if (rc < 0) {
+					pr_err("Failed to delete phy node\n");
+					return 0;
+				}
+			}
+
+			val = readb(GSC_PRIMARY_SPEED_DUPLEX);
+			if (val == (GSC_DUPLEX_FULL_MASK | GSC_SPEED_1000_MASK)) {
+				nodeoff = fdt_path_offset(blob, GSC_MACB0);
+				if (nodeoff < 0) {
+					pr_err("Failed to find macb0 node\n");
+					return 0;
+				}
+
+				rc = __ft_add_fixed_link(blob, nodeoff);
+				if (rc < 0) {
+					pr_err("Failed to add macb0 fixed-link\n");
+					return 0;
+				}
+			}
+
+			rc = fdt_find_and_setprop(blob, GSC_MACB0, "status",
+						  "okay", 6, 1);
+			if (rc < 0)
+				pr_err("Failed to set okay (%s)\n", GSC_MACB0);
+
+		} else if (val == 0x02) {
+			mac2_is_primary = 1;
+			rc = fdt_find_and_setprop(blob, GSC_MACB2, "status",
+						  "okay", 6, 1);
+			if (rc < 0)
+				pr_err("Failed to set okay (%s)\n", GSC_MACB2);
+		}
+
+		val = (readb(GSC_PRIMARY_SECONDARY_CFG) & GSC_SECONDARY_MAC_MASK)
+				>> GSC_SECONDARY_MAC_SHIFT;
+		if (val == 0x00) {
+			if (mac2_is_primary) {
+				rc = fdt_find_and_setprop(blob, GSC_MACB0,
+							  "status",
+							  "disabled", 10, 1);
+				if (rc < 0)
+					pr_err("Failed to disable (%s)\n",
+					       GSC_MACB0);
+			} else {
+				val = (readb(GSC_PRIMARY_SECONDARY_PHY_TYPE) &
+					GSC_SECONDARY_TYPE_MASK)
+					>> GSC_SECONDARY_TYPE_SHIFT;
+				if (val == 0x00) {
+					rc = fdt_find_and_setprop(blob,
+								  GSC_MACB2,
+								  "status",
+								  "disabled",
+								  10, 1);
+					if (rc < 0)
+						pr_err("Failed to disable (%s)\n",
+						       GSC_MACB2);
+				}
+			}
+		}
+	} else {
+		/* Failover mode: configure 1000base-x */
+		nodeoff = fdt_path_offset(blob, GSC_MACB0);
+		if (nodeoff < 0) {
+			pr_err("Failed to find macb0 node\n");
+			return 0;
+		}
+
+		rc = fdt_delprop(blob, nodeoff, "phy-handle");
+		if (rc < 0) {
+			pr_err("Failed to delete phy-handle\n");
+			return 0;
+		}
+
+		nodeoff = fdt_path_offset(blob, GSC_MACB0_ETHERNET_PHY);
+		if (nodeoff < 0) {
+			pr_err("Failed to find macb0 phy node\n");
+			return 0;
+		}
+
+		rc = fdt_del_node(blob, nodeoff);
+		if (rc < 0) {
+			pr_err("Failed to delete phy node\n");
+			return 0;
+		}
+
+		rc = fdt_find_and_setprop(blob, GSC_MACB0, "phy-mode",
+					  "1000base-x", 12, 0);
+		if (rc < 0) {
+			pr_err("Failed to set phy-mode\n");
+			return 0;
+		}
+
+		nodeoff = fdt_path_offset(blob, GSC_MACB0);
+		if (nodeoff < 0) {
+			pr_err("Failed to find macb0 node\n");
+			return 0;
+		}
+
+		rc = __ft_add_fixed_link(blob, nodeoff);
+		if (rc < 0) {
+			pr_err("Failed to add macb0 fixed-link\n");
+			return 0;
+		}
+
+		rc = fdt_find_and_setprop(blob, GSC_MACB0, "status",
+					  "okay", 6, 1);
+		if (rc < 0)
+			pr_err("Failed to set okay (%s)\n", GSC_MACB0);
+
+		rc = fdt_find_and_setprop(blob, GSC_MACB2, "status",
+					  "disabled", 10, 1);
+		if (rc < 0)
+			pr_err("Failed to disable (%s)\n", GSC_MACB2);
+	}
+
+	ft_board_setup_vpd(blob, bd);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	/* Apply runtime FDT changes to U-Boot's own device tree */
+	ft_board_setup((void *)gd->fdt_blob, gd->bd);
+
+	return 0;
+}
+
+static struct mm_region gsc_mem_map[] = {
+	{
+		.virt = 0x00000000,
+		.phys = 0x00000000,
+		.size = 0x00000000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		.virt = 0x40000000,
+		.phys = 0x40000000,
+		.size = 0x00000000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		.virt = 0xa0008000,
+		.phys = 0xa0008000,
+		.size = 0x10000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		.virt = 0xc0000000,
+		.phys = 0xc0000000,
+		.size = 0x1f000000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN |
+			 PTE_BLOCK_UXN
+	}, {
+		.virt = 0xfc000000,
+		.phys = 0xfc000000,
+		.size = 0x04000000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = gsc_mem_map;
+
+static void calculate_available_dram_size(void)
+{
+	phys_size_t total_ddr_size = 0x40000000u;
+	phys_size_t non_ecc_region_1_size = 0u;
+	phys_size_t non_ecc_region_2_size = 0u;
+	u8 index = 0u;
+	phys_size_t video_mem_size_a[VIDEOMEM_ARRAY_SIZE] = {
+		0x0, 0x400000, 0x800000, 0x1000000,
+		0x2000000, 0x4000000, 0x8000000
+	};
+
+	total_ddr_size = 1u << (17u - ((readl(DENALI_ROW_DIFF) >> 24u) & 0x7));
+	total_ddr_size = (total_ddr_size / 8u) * (128u * 1024u);
+
+	if (((readl(DENALI_ECC_ENABLE_DISABLE) >> 16u) & 0x3) > 0u) {
+		total_ddr_size = (total_ddr_size / 8u) * 7u;
+
+		if ((readl(DENALI_NON_ECC_REGION_ENABLED) & 0x1) > 0u) {
+			non_ecc_region_1_size =
+				((readl(DENALI_REG_NONECC_REGION_ONE) >> 16u) & 0xfff) -
+				(readl(DENALI_REG_NONECC_REGION_ONE) & 0xfff);
+			non_ecc_region_1_size <<= 20u;
+			total_ddr_size -= non_ecc_region_1_size;
+		}
+
+		if ((readl(DENALI_NON_ECC_REGION_ENABLED) & 0x2) > 0u) {
+			non_ecc_region_2_size =
+				((readl(DENALI_REG_NONECC_REGION_TWO) >> 16u) & 0xfff) -
+				(readl(DENALI_REG_NONECC_REGION_TWO) & 0xfff);
+			non_ecc_region_2_size <<= 20u;
+			total_ddr_size -= non_ecc_region_2_size;
+		}
+	} else {
+		index = readl(VMEMOFF_ADDRESS) & 0x7;
+		if (index < VIDEOMEM_ARRAY_SIZE)
+			total_ddr_size -= video_mem_size_a[index];
+		else
+			total_ddr_size -= DEFAULT_VIDEO_RAM_SIZE;
+		total_ddr_size -= DEFAULT_RESERVED_MEMORY_SIZE;
+	}
+
+	gd->ram_size = total_ddr_size;
+	gsc_mem_map[0].size = total_ddr_size;
+	if ((17u - ((readl(DENALI_ROW_DIFF) >> 24u) & 0x7)) == 16u)
+		gsc_mem_map[1].size = total_ddr_size;
+}
+
+int dram_init(void)
+{
+	calculate_available_dram_size();
+	return 0;
+}
+
+static int get_eeprom_mac(uint offset, u8 *v_mac)
+{
+	return get_eeprom_val(offset, v_mac, 6);
+}
+
+static int set_mac_addr(const char *name, uint offset)
+{
+	int ret;
+	u8 v_mac[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+
+	ret = get_eeprom_mac(offset, v_mac);
+	if (ret || !is_valid_ethaddr(v_mac)) {
+		pr_err("Warning: MAC %s - %pM ", name, v_mac);
+		if (IS_ENABLED(CONFIG_NET_RANDOM_ETHADDR)) {
+			net_random_ethaddr(v_mac);
+			pr_err("invalid, using random MAC - %pM\n", v_mac);
+		} else {
+			pr_err("is not valid\n");
+			return -1;
+		}
+	}
+
+	env_set(".flags", name);
+	env_set(name, NULL);
+	eth_env_set_enetaddr(name, v_mac);
+	debug("%s MAC Address %pM\n", name, v_mac);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	set_mac_addr("ethaddr", V_EEPROM_RO_MAC0);
+	set_mac_addr("eth1addr", V_EEPROM_RO_MAC1);
+	return 0;
+}
+
+static void arch_timer_start_reg_set(void)
+{
+	writel(ARCH_TIMER_FREQUENCY, ARCH_TIMER_CNTFID0);
+	writel(ARCH_TIMER_CNTCR_ENABLE | ARCH_TIMER_CNTCR_HDBG,
+	       ARCH_TIMER_CNTCR_REG);
+}
+
+int arch_early_init_r(void)
+{
+	if (IS_ENABLED(CONFIG_ARMV8_SPIN_TABLE)) {
+		writel(gd->relocaddr, SECONDARY_RELEASE_ADDR);
+		dsb();
+		asm volatile("sev");
+	}
+
+	arch_timer_start_reg_set();
+
+	if (common_phy_poweron_init() == 0)
+		debug("CommonPhy poweron init succeeded\n");
+	else
+		pr_err("CommonPhy poweron init failed\n");
+
+	return 0;
+}
diff --git a/board/hpe/gsc/server_id.c b/board/hpe/gsc/server_id.c
new file mode 100644
index 00000000000..acfcc889f87
--- /dev/null
+++ b/board/hpe/gsc/server_id.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * GSC server_id command
+ *
+ * (C) Copyright 2019-2025 Hewlett Packard Enterprise Development LP.
+ * Author: Jorge Cisneros <jorge.cisneros@hpe.com>
+ */
+
+#include <env.h>
+#include <asm/io.h>
+#include <command.h>
+
+#define REGISTER_BASE_ADDRESS	0xD1000000
+#define SERVER_ID_OFFSET	0x0
+#define SERVER_ID_MASK		0xFFFF00
+
+static unsigned int get_server_id(void)
+{
+	unsigned int server_id;
+
+	server_id = readl(REGISTER_BASE_ADDRESS + SERVER_ID_OFFSET);
+	server_id &= SERVER_ID_MASK;
+	server_id >>= 8;
+	return server_id;
+}
+
+static int do_server_id(struct cmd_tbl *cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	unsigned int server_id = get_server_id();
+	char env_value[16];
+
+	if (argc == 2) {
+		if (strcmp(argv[1], "show") == 0)
+			printf("Server ID: 0x%04X\n", server_id);
+		else
+			printf("Usage: %s <show>\n", cmdtp->name);
+	} else {
+		snprintf(env_value, sizeof(env_value), "0x%04x", server_id);
+		env_set("server_id", env_value);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	server_id, 2, 0, do_server_id,
+	"Get the server ID from the GSC registers",
+	"<show> - Show the server id instead of setting the environment variable\n"
+	"         otherwise set an environment variable \"server_id\" with the value\n"
+);
diff --git a/include/configs/gsc.h b/include/configs/gsc.h
new file mode 100644
index 00000000000..6a199f52674
--- /dev/null
+++ b/include/configs/gsc.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * GSC board configuration
+ *
+ * (C) Copyright 2019-2025 Hewlett Packard Enterprise Development LP.
+ */
+
+#ifndef _GSC_H_
+#define _GSC_H_
+
+#include <linux/sizes.h>
+
+#define CFG_SYS_SDRAM_BASE		0x0
+#define CFG_SYS_INIT_RAM_ADDR		0x0
+#define CFG_SYS_INIT_RAM_SIZE		0x100000
+#define CFG_SYS_INIT_SP_OFFSET \
+	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_ADDR \
+	(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET)
+
+#define GICD_BASE			0xce000000
+#define GICR_BASE			0xce060000
+#define SECONDARY_RELEASE_ADDR		0xa0008048
+
+#endif

-- 
2.43.0

[PATCH 8/9] configs: Add gsc_defconfig for HPE GSC SoC

[Jorge Cisneros]

Add default configuration for the HPE GSC (Gen Server Controller)
board. This is an ARM64 BMC SoC used in HPE Gen12 ProLiant and
Synergy servers.

Key features enabled:
- ARMv8 spin-table multicore with GICv3
- FIT image boot from SPI flash
- GXP timer, I2C, and SPI drivers (shared IP blocks)
- Cadence MACB GEM Ethernet with Marvell PHY
- GSC watchdog and memory-mapped EEPROM
- FDT fixups for I3C hub and VPD provisioning

Signed-off-by: Jorge Cisneros <jorge.cisneros@hpe.com>
---
 configs/gsc_defconfig | 88 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/configs/gsc_defconfig b/configs/gsc_defconfig
new file mode 100644
index 00000000000..7bfa40221bf
--- /dev/null
+++ b/configs/gsc_defconfig
@@ -0,0 +1,88 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_HPE=y
+CONFIG_HPE_GSC=y
+CONFIG_TEXT_BASE=0x10000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_GSC_I3C_HUB_DT=y
+CONFIG_GSC_PATCH_KERNEL_DTS_VPD=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="hpe-gsc"
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SYS_LOAD_ADDR=0x200000
+CONFIG_WATCHDOG_TIMEOUT_MSECS=30000
+CONFIG_ARMV8_MULTIENTRY=y
+CONFIG_ARMV8_SET_SMPEN=y
+CONFIG_ARMV8_SPIN_TABLE=y
+CONFIG_ARMV8_CRYPTO=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=5
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run spiboot"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_MISC_INIT_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="HPE_BMC# "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNLZ4 is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_OF_TAG_MIGRATE is not set
+CONFIG_CLK=y
+CONFIG_DM_I2C=y
+CONFIG_GXP_I2C=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_GSC_MEMEEPROM=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MARVELL=y
+CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
+CONFIG_MACB=y
+CONFIG_MII=y
+# CONFIG_POWER is not set
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_GXP_SPI=y
+CONFIG_TIMER=y
+CONFIG_GXP_TIMER=y
+CONFIG_WDT=y
+CONFIG_WDT_GSC=y
+CONFIG_SHA512=y
+CONFIG_LZ4=y
+CONFIG_LZMA=y

-- 
2.43.0

[PATCH 9/9] MAINTAINERS: Add HPE GSC files and maintainer

[Jorge Cisneros]

Add Jorge Cisneros as maintainer for the HPE GSC SoC support. Rename
the section to 'ARM HPE GXP/GSC ARCHITECTURE' to reflect both the
Gen11 (GXP) and Gen12 (GSC) BMC SoCs. Add file patterns for all new
GSC-specific files.

Signed-off-by: Jorge Cisneros <jorge.cisneros@hpe.com>
---
 MAINTAINERS | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index d2040fee252..70e98732c16 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -334,18 +334,24 @@ F:	arch/arm/include/asm/arch-hi6220/
 F:	arch/arm/include/asm/arch-hi3660/
 F:	arch/arm/mach-histb
 
-ARM HPE GXP ARCHITECTURE
+ARM HPE GXP/GSC ARCHITECTURE
 M:	Jean-Marie Verdun <verdun@hpe.com>
 M:	Nick Hawkins <nick.hawkins@hpe.com>
+M:	Jorge Cisneros <jorge.cisneros@hpe.com>
 S:	Maintained
 F:	arch/arm/dts/hpe-bmc*
+F:	arch/arm/dts/hpe-gsc*
 F:	arch/arm/dts/hpe-gxp*
 F:	arch/arm/mach-hpe/
 F:	board/hpe/
+F:	configs/gsc_defconfig
 F:	configs/gxp_defconfig
 F:	doc/device-tree-bindings/spi/hpe,gxp-spi.yaml
+F:	drivers/misc/gsc_mem_eeprom.c
 F:	drivers/timer/gxp-timer.c
 F:	drivers/spi/gxp_spi.c
+F:	drivers/watchdog/gsc_wdt.c
+F:	include/configs/gsc.h
 
 ARM IPQ40XX
 M:	Robert Marko <robert.marko@sartura.hr>

-- 
2.43.0

Re: [PATCH 0/9] arm: hpe: Add HPE GSC (Gen12) BMC SoC support

[Tom Rini]

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On Wed, Apr 08, 2026 at 07:24:12PM +0000, Jorge Cisneros wrote:

> This series adds support for the HPE GSC (Gen Server Controller), an
> ARM64-based BMC SoC used in HPE ProLiant and Synergy Gen12 servers.
> 
> The GSC is the successor to the GXP SoC (already upstream) used in
> Gen11 servers. It features dual Cortex-A35 cores with GICv3, a Denali
> DDR memory controller, Cadence GEM Ethernet (SGMII), and reuses several
> GXP IP blocks (timer, SPI, I2C).
> 
> The existing ARCH_GXP Kconfig symbol is renamed to ARCH_HPE to serve as
> an umbrella for both the GXP (ARMv7) and GSC (ARMv8) SoC variants,
> selected via a choice menu under mach-hpe.
> 
> New drivers:
> - Watchdog (drivers/watchdog/gsc_wdt.c)
> - Memory-mapped virtual EEPROM for VPD (drivers/misc/gsc_mem_eeprom.c)
> - Cadence GEM support added to the existing MACB driver
> 
> Board support includes DRAM sizing from the Denali memory controller,
> MAC address provisioning from VPD EEPROM, FDT fixups for network
> configuration, shared Ethernet/DisplayPort PHY initialization, and a
> server_id command for reading server identification from the CPLD.
> 
> Notes:
> - The server_id command (patch 7) is hardware-specific and reads from
>   GSC CPLD registers, so no sandbox test is included.
> - MAINTAINERS warnings in patches 1-8 are resolved by patch 9.
> 
> Based on v2026.04-rc4 (ba7bf918dafcd093ad733b07ba490baeb20cf5da).
> Tested: both gxp_defconfig and gsc_defconfig build cleanly.

Thanks for posting this. I have just a few comments to follow.

-- 
Tom

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Re: [PATCH 1/9] arm: hpe: Rename ARCH_GXP to ARCH_HPE and add GSC SoC choice

[Tom Rini]

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On Wed, Apr 08, 2026 at 07:24:13PM +0000, Jorge Cisneros wrote:

> Rename ARCH_GXP to ARCH_HPE to serve as an umbrella config for all HPE
> BMC SoCs. Add a choice menu under mach-hpe to select between:
> - HPE_GXP: Gen11 (GXP) BMC SoC (ARMv7)
> - HPE_GSC: Gen12 (GSC) BMC SoC (ARMv8)
> 
> Update arch/arm/Makefile to use the new CONFIG_ARCH_HPE symbol and
> migrate the existing gxp_defconfig. Add stub Kconfig files for the GSC
> SoC and board to maintain a valid Kconfig tree.
> 
> Signed-off-by: Jorge Cisneros <jorge.cisneros@hpe.com>
[snip]
> diff --git a/arch/arm/mach-hpe/gsc/Kconfig b/arch/arm/mach-hpe/gsc/Kconfig
> new file mode 100644
> index 00000000000..9821bf6149f
> --- /dev/null
> +++ b/arch/arm/mach-hpe/gsc/Kconfig
> @@ -0,0 +1,27 @@
> +if HPE_GSC
> +
> +config SOC_GSC
> +	bool
> +	select ARM64
> +
> +config SYS_SOC
> +	default "gsc"
> +
> +config GSC_I3C_HUB_DT
> +	bool "Fix up the I3C Hub Node in Kernel DTS"
> +	default n

Globally, "default n" is the default, so we don't need to add this line.

-- 
Tom

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Re: [PATCH 3/9] arm: dts: Add HPE GSC device tree

[Tom Rini]

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On Wed, Apr 08, 2026 at 07:24:15PM +0000, Jorge Cisneros wrote:

> Add device tree for the HPE GSC SoC including:
> - Dual Cortex-A35 cores with spin-table enable method
> - GICv3 interrupt controller
> - NS16550A compatible UART
> - GXP timer and SPI/I2C controllers (shared IP blocks)
> - Two Cadence GEM Ethernet MACs with SGMII PHYs
> - Synopsys DWC MSHC eMMC controller
> - GSC watchdog timer
> - Memory-mapped virtual EEPROM for VPD storage
> - Fixed clock definitions for peripheral buses
> 
> Signed-off-by: Jorge Cisneros <jorge.cisneros@hpe.com>
> ---
>  arch/arm/dts/hpe-gsc.dts | 146 +++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 146 insertions(+)

What is the status of getting this supported in the upstream kernel?
I do see dts/upstream/src/arm/hpe/hpe-gxp.dtsi for example.  Thanks.

-- 
Tom

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Re: [PATCH 7/9] board: hpe: Add GSC board support

[Tom Rini]

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On Wed, Apr 08, 2026 at 07:24:19PM +0000, Jorge Cisneros wrote:

> Add board support for the HPE GSC (Gen Server Controller), the BMC
> SoC used in HPE Gen12 ProLiant and Synergy servers.
> 
> Board files include:
> - gsc_board.c: Board init, DRAM sizing from Denali memory controller,
>   MAC address provisioning from memory-mapped EEPROM, and FDT fixups
>   for network configuration based on CPLD xregisters
> - common-phy.c: Shared Ethernet/DisplayPort PHY initialization with
>   configurable transmitter amplitude and de-emphasis
> - server_id.c: Custom command to read server identification from CPLD
> - gsc.env: Default SPI flash boot environment
> - gsc.h: Board configuration header with GICv3 and spin-table addresses
> 
> Signed-off-by: Jorge Cisneros <jorge.cisneros@hpe.com>
[snip]
> +int board_init(void)
> +{
> +	return 0;
> +}

I think you can just disable CONFIG_BOARD_INIT in the defconfig instead.

-- 
Tom

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Re: [PATCH 8/9] configs: Add gsc_defconfig for HPE GSC SoC

[Tom Rini]

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On Wed, Apr 08, 2026 at 07:24:20PM +0000, Jorge Cisneros wrote:

> Add default configuration for the HPE GSC (Gen Server Controller)
> board. This is an ARM64 BMC SoC used in HPE Gen12 ProLiant and
> Synergy servers.
> 
> Key features enabled:
> - ARMv8 spin-table multicore with GICv3
> - FIT image boot from SPI flash
> - GXP timer, I2C, and SPI drivers (shared IP blocks)
> - Cadence MACB GEM Ethernet with Marvell PHY
> - GSC watchdog and memory-mapped EEPROM
> - FDT fixups for I3C hub and VPD provisioning
> 
> Signed-off-by: Jorge Cisneros <jorge.cisneros@hpe.com>
> ---
>  configs/gsc_defconfig | 88 +++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 88 insertions(+)

This should be part of the patch that adds the platform itself.

-- 
Tom

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