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From: Pranav Tilak <pranav.vinaytilak@amd.com>
To: <u-boot@lists.denx.de>, <michal.simek@amd.com>
Cc: <git@amd.com>, <padmarao.begari@amd.com>,
	Pranav Tilak <pranav.vinaytilak@amd.com>
Subject: [PATCH 1/3] net: zynq_gem: add SPEED_10000 case in clock rate selection
Date: Fri, 10 Apr 2026 15:00:16 +0530	[thread overview]
Message-ID: <20260410093018.1461732-2-pranav.vinaytilak@amd.com> (raw)
In-Reply-To: <20260410093018.1461732-1-pranav.vinaytilak@amd.com>

Add SPEED_10000 case in the speed switch with the fixed 150 MHz
tx_clk rate. Without this, clk_rate stays 0 for 10000 Mbps and
clk_set_rate(0) on a fixed clock aborts initialization.

Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com>
---
 drivers/net/zynq_gem.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index a50d5aee03f..c06d114af68 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -134,6 +134,7 @@
 #define ZYNQ_GEM_FREQUENCY_10	2500000UL
 #define ZYNQ_GEM_FREQUENCY_100	25000000UL
 #define ZYNQ_GEM_FREQUENCY_1000	125000000UL
+#define ZYNQ_GEM_FREQUENCY_10000	150000000UL
 
 #define RXCLK_EN		BIT(0)
 
@@ -602,6 +603,9 @@ static int zynq_gem_init(struct udevice *dev)
 	}
 
 	switch (priv->phydev->speed) {
+	case SPEED_10000:
+		clk_rate = ZYNQ_GEM_FREQUENCY_10000;
+		break;
 	case SPEED_1000:
 		nwconfig |= ZYNQ_GEM_NWCFG_SPEED1000;
 		clk_rate = ZYNQ_GEM_FREQUENCY_1000;
-- 
2.43.0


  reply	other threads:[~2026-04-10  9:31 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-10  9:30 [PATCH 0/3] fix 10GBE support for AMD Versal Gen 2 Pranav Tilak
2026-04-10  9:30 ` Pranav Tilak [this message]
2026-04-10  9:30 ` [PATCH 2/3] net: zynq_gem: set 128-bit AXI bus width for 10GBE Pranav Tilak
2026-04-10  9:30 ` [PATCH 3/3] net: zynq_gem: reinitialize RX BDs on every init Pranav Tilak

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