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[187.191.8.235]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-69d83709124sm6535671eaf.5.2026.05.26.07.03.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 May 2026 07:03:16 -0700 (PDT) Date: Tue, 26 May 2026 08:03:13 -0600 From: Tom Rini To: Krzysztof Kozlowski Cc: u-boot@lists.denx.de, Ilias Apalodimas Subject: Re: [PATCH 0/1] armv8: reduce core errata dispatch work Message-ID: <20260526140313.GR1858239@bill-the-cat> References: <20260524123822.7244-1-josh2@disroot.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="Ga12fJ5eaDN4nGwv" Content-Disposition: inline In-Reply-To: X-Clacks-Overhead: GNU Terry Pratchett X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean --Ga12fJ5eaDN4nGwv Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, May 26, 2026 at 08:01:16AM +0200, Krzysztof Kozlowski wrote: > On 24/05/2026 14:38, Josh Law wrote: > > Hey folks, > >=20 > > apply_core_errata() runs during early ARMv8 CPU entry, before > > lowlevel_init(). Today it still checks the Cortex-A53 and Cortex-A57 > > paths even when the build has no matching core erratum enabled. > >=20 > > This patch leaves that dispatch code out unless one of the supported > > errata is enabled. For the A57 errata case, it reads MIDR_EL1 once and > > reuses the extracted CPU part number. > >=20 > > The erratum register writes stay behind the same CPU checks as before. > > For qemu_arm64_defconfig, where none of these errata are enabled, > > apply_core_errata() goes from 15 dispatch instructions to a single ret. > > For ls2080aqds_qspi_defconfig, which keeps the A57 path, the dispatch > > side goes from 33 instructions to 26. A KVM microbench of the same > > dispatch sequences showed 1.30x for the no errata case and 1.09x for > > the A57 miss case. > >=20 > > Josh Law (1): > > armv8: reduce core errata dispatch work >=20 > That's another identity from Josh Law, since all previous got NAKed, and > 100% AI generated code without review and without tests (I don't believe > what was claimed above). >=20 > I recommend ignoring and here is some background: >=20 > https://lore.kernel.org/all/cbd0aafa-bd45-4f4d-a2dd-440473657dba@lucifer.= local/ Well crap. Thanks for the link! I've moved all of the submissions to Deferred in patchwork. --=20 Tom --Ga12fJ5eaDN4nGwv Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTzzqh0PWDgGS+bTHor4qD1Cr/kCgUCahWoHQAKCRAr4qD1Cr/k CqoIAQCKQN7W5U5mdy3WP9yybiCkCPLb/M6qIVb8Bmja4wuUnAD+MP5Ybj2zGEqp xris1+hOco/3FKkTVX4iHvGBQH3+cAo= =Ef5j -----END PGP SIGNATURE----- --Ga12fJ5eaDN4nGwv--