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[87.92.251.137]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-39b1da4ca90sm4905721fa.31.2026.06.30.05.39.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jun 2026 05:39:54 -0700 (PDT) From: Md Shofiqul Islam To: u-boot@lists.denx.de Cc: ian.ray@gehealthcare.com, HuanWang@gehealthcare.com, brian.ruley@gehealthcare.com, martyn.welch@collabora.com, hs@nabladev.com, lukma@denx.de, sbabic@nabladev.com, festevam@gmail.com, Md Shofiqul Islam Subject: [PATCH v2 1/2] clk: imx6q: guard LDB clock init with appropriate video config Date: Tue, 30 Jun 2026 15:39:50 +0300 Message-ID: <20260630123951.13385-2-shofiqtest@gmail.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20260630123951.13385-1-shofiqtest@gmail.com> References: <20260630123951.13385-1-shofiqtest@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Tue, 30 Jun 2026 14:50:53 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Guard calls to select_ldb_di_clock_source() with the correct video Kconfig symbol rather than the broad !CONFIG_SPL_BUILD guard. SPL can support VIDEO, PANEL, and SPLASH_SCREEN so !CONFIG_SPL_BUILD excluded SPL builds that legitimately need to configure the LDB clocks. - board/ge/b1x5v2: guard with CONFIG_SPL_VIDEO — LDB init is needed in SPL only when display support is enabled - board/aristainetos: guard with CONFIG_VIDEO_IPUV3 — this board does not use SPL so CONFIG_SPL_VIDEO is not the right guard here - drivers/clk/imx/clk-imx6q: update both the definition of imx6q_init_ldb_clks() and its call site to use (!CONFIG_SPL_BUILD || CONFIG_SPL_VIDEO) — the function is needed in SPL when CONFIG_SPL_VIDEO is set, and on all non-SPL builds Signed-off-by: Md Shofiqul Islam --- board/aristainetos/aristainetos.c | 2 ++ board/ge/b1x5v2/b1x5v2.c | 3 ++- drivers/clk/imx/clk-imx6q.c | 4 ++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 4a2349e165b..c163b49209e 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -218,7 +218,9 @@ static void set_gpr_register(void) int board_early_init_f(void) { +#if defined(CONFIG_VIDEO_IPUV3) select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK); +#endif set_gpr_register(); /* diff --git a/board/ge/b1x5v2/b1x5v2.c b/board/ge/b1x5v2/b1x5v2.c index f7751fd6fb1..da7cb880eeb 100644 --- a/board/ge/b1x5v2/b1x5v2.c +++ b/board/ge/b1x5v2/b1x5v2.c @@ -320,8 +320,9 @@ int overwrite_console(void) int board_early_init_f(void) { +#if defined(CONFIG_SPL_VIDEO) select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK); - +#endif return 0; } diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index a4649a1a9d9..5be303468a9 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -156,6 +156,7 @@ static struct clk_div_table video_div_table[] = { static unsigned int share_count_mipi_core_cfg; +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_VIDEO) static void of_assigned_ldb_sels(struct udevice *dev, int *ldb_di0_sel, int *ldb_di1_sel) { @@ -270,6 +271,7 @@ static void imx6q_init_ldb_clks(struct udevice *dev) select_ldb_di_clock_source(ldb_di_clk[0], ldb_di_clk[1]); } +#endif /* !CONFIG_SPL_BUILD || CONFIG_SPL_VIDEO */ static int imx6q_clk_probe(struct udevice *dev) { @@ -488,7 +490,9 @@ static int imx6q_clk_probe(struct udevice *dev) * Need to set the clocks now and make them read-only due to a * hardware bug. Fixed on the i.MX6 QuadPlus */ +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_VIDEO) imx6q_init_ldb_clks(dev); +#endif clk_dm(IMX6QDL_CLK_LDB_DI0_SEL, imx_clk_mux_flags(dev, "ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), -- 2.51.1