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From: Billy Tsai <billy_tsai@aspeedtech.com>
To: Aspeed BMC SW team <BMC-SW@aspeedtech.com>,
	Joel Stanley <joel@jms.id.au>,  <u-boot@lists.denx.de>
Cc: Tom Rini <trini@konsulko.com>,
	Ryan Chen <ryan_chen@aspeedtech.com>,
	Chia-Wei Wang <chiawei_wang@aspeedtech.com>,
	Peng Fan <peng.fan@nxp.com>,
	"Dan Carpenter" <dan.carpenter@linaro.org>,
	Michael Trimarchi <michael@amarulasolutions.com>,
	Yao Zi <me@ziyao.cc>, Sean Anderson <sean.anderson@linux.dev>,
	Michal Simek <michal.simek@amd.com>,
	"Leo Yu-Chi Liang" <ycliang@andestech.com>,
	Billy Tsai <billy_tsai@aspeedtech.com>
Subject: [PATCH 0/4] pinctrl: aspeed: Add AST2700 pinctrl drivers
Date: Thu, 2 Jul 2026 18:08:33 +0800	[thread overview]
Message-ID: <20260702-pinctrl-v1-0-4d2bd89fc213@aspeedtech.com> (raw)

The AST2700 is Aspeed's 7th-generation BMC SoC with a dual-die
architecture: SoC0 (CPU die) and SoC1 (I/O die) each have their own SCU
with independent multi-function pin controls. Initial AST2700 platform
support is already merged in next, including the ast2700.dtsi pinctrl0
and pinctrl1 nodes, but no pinctrl driver backs them yet.

This series adds one pinctrl driver per die, each followed by a patch
adding its pin configuration support. Both drivers use the generic
pinctrl framework and are compatible with the Linux kernel device tree
bindings, using the same group and function names as the Linux
aspeed,ast2700-soc0/soc1-pinctrl drivers so pin states can be shared
between the kernel and U-Boot device trees.

Patch 1 adds the SoC0 driver, which models each (function, group) pair
as a flat register mask/value table covering eMMC, VB, VGA DDC, JTAG
master port select, PCIe RC PERST and USB2/USB3 port routing. Patch 2
adds SoC0 pin configuration support: every GPIO18A/GPIO18B ball has
its own IO control register providing a 3 mA to 41 mA drive strength
selector and bias control.

Patch 3 adds the SoC1 driver, porting the per-pin 4-bit multi-function
selector scheme (220 pins, 238 groups, 217 functions) together with
the virtual pins for PCIe RC2 PERST, the USB2 port C/D mode and SGMII
controls. Patch 4 adds SoC1 pin configuration support: a per-pin bias
enable bit and sparse 2-bit drive strength fields (4 mA to 16 mA in
4 mA steps) mirroring the Linux driver layout.

The bias-disable, bias-pull-down, bias-pull-up and drive-strength
properties can be applied per pin or per group. Both drivers implement
gpio_request_enable so the GPIO driver can reclaim pins through the
gpio-ranges already present in ast2700.dtsi, and provide
get_pin_muxing so "pinmux status" reports the active signal of every
pin.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
Billy Tsai (4):
      pinctrl: aspeed: Add AST2700 SoC0 pinctrl driver
      pinctrl: aspeed: Add AST2700 SoC0 pinconf support
      pinctrl: aspeed: Add AST2700 SoC1 pinctrl driver
      pinctrl: aspeed: Add AST2700 SoC1 pinconf support

 drivers/pinctrl/Kconfig                       |   20 +
 drivers/pinctrl/aspeed/Makefile               |    2 +
 drivers/pinctrl/aspeed/pinctrl_ast2700_soc0.c |  623 ++++++++++
 drivers/pinctrl/aspeed/pinctrl_ast2700_soc1.c | 1642 +++++++++++++++++++++++++
 4 files changed, 2287 insertions(+)
---
base-commit: e800cc67f5b6cb50a20f37c993ec1cd4063bdbd3
change-id: 20260702-pinctrl-03aff21bdf43

Best regards,
-- 
Billy Tsai <billy_tsai@aspeedtech.com>


             reply	other threads:[~2026-07-02 10:08 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-02 10:08 Billy Tsai [this message]
2026-07-02 10:08 ` [PATCH 1/4] pinctrl: aspeed: Add AST2700 SoC0 pinctrl driver Billy Tsai
2026-07-02 10:08 ` [PATCH 2/4] pinctrl: aspeed: Add AST2700 SoC0 pinconf support Billy Tsai
2026-07-02 10:08 ` [PATCH 3/4] pinctrl: aspeed: Add AST2700 SoC1 pinctrl driver Billy Tsai
2026-07-02 10:08 ` [PATCH 4/4] pinctrl: aspeed: Add AST2700 SoC1 pinconf support Billy Tsai

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