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From: James Hilliard <james.hilliard1@gmail.com>
To: Svyatoslav Ryhel <clamor95@gmail.com>,
	Ion Agorria <ion@agorria.com>,
	 u-boot@lists.denx.de, Aspeed BMC SW team <BMC-SW@aspeedtech.com>,
	 Joel Stanley <joel@jms.id.au>
Cc: Chen-Yu Tsai <wens@kernel.org>,
	Samuel Holland <samuel@sholland.org>,
	 Tom Rini <trini@konsulko.com>, Simon Glass <sjg@chromium.org>,
	 Thierry Reding <treding@nvidia.com>,
	 Quentin Schulz <quentin.schulz@cherry.de>,
	 Marek Vasut <marek.vasut+renesas@mailbox.org>,
	 Rasmus Villemoes <ravi@prevas.dk>,
	Aristo Chen <aristo.chen@canonical.com>,
	 Anton Ivanov <anton@binarly.io>,
	Daniel Golle <daniel@makrotopia.org>,
	 Francois Berder <fberder@outlook.fr>,
	Peng Fan <peng.fan@nxp.com>,
	 Neil Armstrong <neil.armstrong@linaro.org>,
	Randolph Sapp <rs@ti.com>,  Jonas Karlman <jonas@kwiboo.se>,
	 Wolfgang Wallner <wolfgang.wallner@at.abb.com>,
	 Alexey Charkov <alchark@gmail.com>,
	 Ilias Apalodimas <ilias.apalodimas@linaro.org>,
	 Heiko Schocher <hs@nabladev.com>,
	 "Kory Maincent (TI.com)" <kory.maincent@bootlin.com>,
	 Anshul Dalal <anshuld@ti.com>, Johan Jonker <jbx6244@gmail.com>,
	 Francesco Valla <francesco@valla.it>,
	 Heinrich Schuchardt <xypron.glpk@gmx.de>,
	Michael Walle <mwalle@kernel.org>,
	 Andre Przywara <andre.przywara@arm.com>,
	Lukasz Majewski <lukma@denx.de>,
	 Richard Genoud <richard.genoud@bootlin.com>,
	 Michael Trimarchi <michael@amarulasolutions.com>,
	 E Shattow <e@freeshell.de>,
	Enric Balletbo i Serra <eballetbo@kernel.org>,
	 Mattijs Korpershoek <mkorpershoek@kernel.org>,
	 Lucas Dietrich <ld.adecy@gmail.com>,
	David Lechner <dlechner@baylibre.com>,
	 Julien Stephan <jstephan@baylibre.com>,
	 Kuan-Wei Chiu <visitorckw@gmail.com>,
	 Bastien Curutchet <bastien.curutchet@bootlin.com>,
	 Raymond Mao <raymond.mao@riscstar.com>,
	 Ryan Chen <ryan_chen@aspeedtech.com>,
	 Chia-Wei Wang <chiawei_wang@aspeedtech.com>,
	 "Lucien.Jheng" <lucienzx159@gmail.com>,
	 Mateusz Furdyna <mateusz.furdyna@nokia.com>,
	 Dinesh Maniyam <dinesh.maniyam@altera.com>,
	 Heiko Stuebner <heiko@sntech.de>,
	 James Hilliard <james.hilliard1@gmail.com>
Subject: [PATCH v4 10/14] clk: sunxi: add H6/H616 CE gates and reset
Date: Mon, 13 Jul 2026 00:43:07 -0600	[thread overview]
Message-ID: <20260713-submit-ce-series-v2-v4-10-ff7edc705b8a@gmail.com> (raw)
In-Reply-To: <20260713-submit-ce-series-v2-v4-0-ff7edc705b8a@gmail.com>

The H6 and H616 devicetrees describe the Crypto Engine with module, bus
and MBUS clocks plus a bus reset. Add the corresponding gate and reset
entries so drivers can enable the CE through the normal clock and reset
uclasses in U-Boot proper.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
---
Changes v1 -> v2:
  - Add Simon's Reviewed-by tag
---
 drivers/clk/sunxi/clk_h6.c   | 5 +++++
 drivers/clk/sunxi/clk_h616.c | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index 81deb5728e5..27ed5705a14 100644
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -20,6 +20,10 @@ static struct ccu_clk_gate h6_gates[] = {
 	[CLK_DE]		= GATE(0x600, BIT(31)),
 	[CLK_BUS_DE]		= GATE(0x60c, BIT(0)),
 
+	[CLK_CE]		= GATE(0x680, BIT(31)),
+	[CLK_BUS_CE]		= GATE(0x68c, BIT(0)),
+
+	[CLK_MBUS_CE]		= GATE(0x804, BIT(2)),
 	[CLK_MBUS_NAND]		= GATE(0x804, BIT(5)),
 
 	[CLK_NAND0]		= GATE(0x810, BIT(31)),
@@ -77,6 +81,7 @@ static struct ccu_clk_gate h6_gates[] = {
 
 static struct ccu_reset h6_resets[] = {
 	[RST_BUS_DE]		= RESET(0x60c, BIT(16)),
+	[RST_BUS_CE]		= RESET(0x68c, BIT(16)),
 	[RST_BUS_NAND]		= RESET(0x82c, BIT(16)),
 
 	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
index 3e7eea25bfe..d5b659d0bb2 100644
--- a/drivers/clk/sunxi/clk_h616.c
+++ b/drivers/clk/sunxi/clk_h616.c
@@ -19,6 +19,10 @@ static struct ccu_clk_gate h616_gates[] = {
 	[CLK_DE]		= GATE(0x600, BIT(31)),
 	[CLK_BUS_DE]		= GATE(0x60c, BIT(0)),
 
+	[CLK_CE]		= GATE(0x680, BIT(31)),
+	[CLK_BUS_CE]		= GATE(0x68c, BIT(0)),
+
+	[CLK_MBUS_CE]		= GATE(0x804, BIT(2)),
 	[CLK_MBUS_NAND]		= GATE(0x804, BIT(5)),
 
 	[CLK_NAND0]		= GATE(0x810, BIT(31)),
@@ -86,6 +90,7 @@ static struct ccu_clk_gate h616_gates[] = {
 
 static struct ccu_reset h616_resets[] = {
 	[RST_BUS_DE]		= RESET(0x60c, BIT(16)),
+	[RST_BUS_CE]		= RESET(0x68c, BIT(16)),
 	[RST_BUS_NAND]		= RESET(0x82c, BIT(16)),
 
 	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),

-- 
2.53.0


  parent reply	other threads:[~2026-07-13 13:22 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-13  6:42 [PATCH v4 00/14] crypto: allwinner: enable sun8i-ce FIT crypto James Hilliard
2026-07-13  6:42 ` [PATCH v4 01/14] cmd: aes: fix DM operation handling James Hilliard
2026-07-13  6:42 ` [PATCH v4 02/14] crypto: hash: use DM providers from hash command James Hilliard
2026-07-13  6:43 ` [PATCH v4 03/14] crypto: aes: allow DM AES in SPL James Hilliard
2026-07-13  6:43 ` [PATCH v4 04/14] crypto: hash: allow DM hash " James Hilliard
2026-07-13  6:43 ` [PATCH v4 05/14] boot: image: try all DM hash providers James Hilliard
2026-07-13  6:43 ` [PATCH v4 06/14] crypto: aes: fix software key-size handling James Hilliard
2026-07-13  6:43 ` [PATCH v4 07/14] crypto: aes: add software-key provider dispatch James Hilliard
2026-07-13  6:43 ` [PATCH v4 08/14] boot: image: add FIT decrypt-to-buffer helper James Hilliard
2026-07-13  6:43 ` [PATCH v4 09/14] spl: fit: support encrypted payloads James Hilliard
2026-07-13  6:43 ` James Hilliard [this message]
2026-07-13  6:43 ` [PATCH v4 11/14] lib: ecdsa: support additional curve sizes James Hilliard
2026-07-13  6:43 ` [PATCH v4 12/14] crypto: allwinner: add sun8i-ce AES driver James Hilliard
2026-07-13  6:43 ` [PATCH v4 13/14] crypto: allwinner: add sun8i-ce ECDSA verifier James Hilliard
2026-07-13  6:43 ` [PATCH v4 14/14] crypto: allwinner: add sun8i-ce hash driver James Hilliard

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