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[144.178.202.142]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c168716f6dbsm59145766b.15.2026.07.15.08.17.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 08:17:49 -0700 (PDT) From: Luca Weiss Date: Wed, 15 Jul 2026 17:17:40 +0200 Subject: [PATCH 1/4] clk/qcom: Add MSM8953 clock driver MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260715-msm8953-basic-v1-1-bc4cb5099d8e@fairphone.com> References: <20260715-msm8953-basic-v1-0-bc4cb5099d8e@fairphone.com> In-Reply-To: <20260715-msm8953-basic-v1-0-bc4cb5099d8e@fairphone.com> To: Sumit Garg , u-boot@lists.denx.de, u-boot-qcom@groups.io Cc: Tom Rini , Lukasz Majewski , Casey Connolly , Neil Armstrong , Biswapriyo Nath , Aswin Murugan , Varadarajan Narayanan , Quentin Schulz , Johan Jonker , Ilias Apalodimas , Antony Kurniawan Soemardi , Luca Weiss X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784128669; l=6421; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=NuXPG+T2txRS50qALbn8pmbo5sAdN1dPfHGLFyz6Q8A=; b=+y3gmtwwyxZtbGqp1qJVVl1eVxOXGmADpaFJ1jhw02WdmvdF6XUNkBpRBQk+Q9rmIuSEaKVva ka/yUcF5Xf4BgtAKMXMDOB2DUuLs9a9eJYw/m3v7PGU5z9Moc1BLK6r X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= X-Mailman-Approved-At: Thu, 16 Jul 2026 03:03:52 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add Clock driver for the GCC block found in the MSM8953 SoC. Signed-off-by: Luca Weiss --- drivers/clk/qcom/Kconfig | 8 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-msm8953.c | 141 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 150 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 9ad233c83ac..8d980acd0a7 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -55,6 +55,14 @@ config CLK_QCOM_MILOS on the Snapdragon Milos SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_MSM8953 + bool "Qualcomm MSM8953 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon MSM8953 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + config CLK_QCOM_QCM2290 bool "Qualcomm QCM2290 GCC" select CLK_QCOM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index c0d95a6300e..4f7eae589cc 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o obj-$(CONFIG_CLK_QCOM_IPQ5424) += clock-ipq5424.o obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o obj-$(CONFIG_CLK_QCOM_MILOS) += clock-milos.o +obj-$(CONFIG_CLK_QCOM_MSM8953) += clock-msm8953.o obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o obj-$(CONFIG_CLK_QCOM_QCS8300) += clock-qcs8300.o diff --git a/drivers/clk/qcom/clock-msm8953.c b/drivers/clk/qcom/clock-msm8953.c new file mode 100644 index 00000000000..b8d04d7e3ee --- /dev/null +++ b/drivers/clk/qcom/clock-msm8953.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm MSM8953 + * + * Copyright (c) 2026 Luca Weiss + */ + +#include +#include +#include +#include +#include + +#include "clock-qcom.h" + +static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { + F(144000, CFG_CLK_SRC_CXO, 16, 3, 25), + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(20000000, (4 << 8) /*P_GPLL0_DIV2*/, 5, 1, 4), + F(25000000, (4 << 8) /*P_GPLL0_DIV2*/, 16, 0, 0), + F(50000000, CFG_CLK_SRC_GPLL0, 16, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0, 8, 0, 0), + F(177770000, CFG_CLK_SRC_GPLL0, 4.5, 0, 0), + F(192000000, (2 << 8) /*P_GPLL4*/, 6, 0, 0), + F(384000000, (2 << 8) /*P_GPLL4*/, 3, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = { + F(144000, CFG_CLK_SRC_CXO, 16, 3, 25), + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(20000000, (4 << 8) /*P_GPLL0_DIV2*/, 5, 1, 4), + F(25000000, (4 << 8) /*P_GPLL0_DIV2*/, 16, 0, 0), + F(50000000, CFG_CLK_SRC_GPLL0, 16, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0, 8, 0, 0), + F(177770000, CFG_CLK_SRC_GPLL0, 4.5, 0, 0), + F(192000000, (2 << 8) /*P_GPLL4*/, 6, 0, 0), + F(200000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_usb30_master_clk_src[] = { + F(80000000, (2 << 8) /*P_GPLL0_DIV2*/, 5, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0, 8, 0, 0), + F(133330000, CFG_CLK_SRC_GPLL0, 6, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(60000000, (2 << 8) /*P_GPLL6_DIV2*/, 9, 1, 1), + { } +}; + +static ulong msm8953_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; + + switch (clk->id) { + case GCC_SDCC1_APPS_CLK: /* SDC1 */ + freq = qcom_find_freq(ftbl_sdcc1_apps_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x42004, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_SDCC2_APPS_CLK: /* SDC2 */ + freq = qcom_find_freq(ftbl_sdcc2_apps_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x43004, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB30_MASTER_CLK: + freq = qcom_find_freq(ftbl_usb30_master_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x3f00c, + freq->pre_div, freq->m, freq->n, freq->src, 0); + return freq->freq; + case GCC_USB30_MOCK_UTMI_CLK: + freq = qcom_find_freq(ftbl_usb30_mock_utmi_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x3f020, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + default: + return 0; + } +} + +static const struct gate_clk msm8953_clks[] = { + GATE_CLK_POLLED(GCC_SDCC1_AHB_CLK, 0x4201c, BIT(0), 0x4201c), + GATE_CLK_POLLED(GCC_SDCC1_APPS_CLK, 0x42018, BIT(0), 0x42018), + GATE_CLK_POLLED(GCC_SDCC2_AHB_CLK, 0x4301c, BIT(0), 0x4301c), + GATE_CLK_POLLED(GCC_SDCC2_APPS_CLK, 0x43018, BIT(0), 0x43018), + GATE_CLK_POLLED(GCC_USB30_MASTER_CLK, 0x3f000, BIT(0), 0x3f000), + GATE_CLK_POLLED(GCC_USB30_SLEEP_CLK, 0x3f004, BIT(0), 0x3f004), + GATE_CLK_POLLED(GCC_USB30_MOCK_UTMI_CLK, 0x3f008, BIT(0), 0x3f008), + GATE_CLK_POLLED(GCC_PCNOC_USB3_AXI_CLK, 0x3f038, BIT(0), 0x3f038), + GATE_CLK_POLLED(GCC_USB_PHY_CFG_AHB_CLK, 0x3f080, BIT(0), 0x3f080), +}; + +static int msm8953_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + return qcom_gate_clk_en(priv, clk->id); +} + +static const struct qcom_reset_map msm8953_resets[] = { + [GCC_QUSB2_PHY_BCR] = { 0x4103c }, +}; + +static const struct qcom_power_map msm8953_gdscs[] = { + [USB30_GDSC] = { .reg = 0x3f078, .flags = ALWAYS_ON }, +}; + +static struct msm_clk_data msm8953_clk_data = { + .resets = msm8953_resets, + .num_resets = ARRAY_SIZE(msm8953_resets), + + .clks = msm8953_clks, + .num_clks = ARRAY_SIZE(msm8953_clks), + + .power_domains = msm8953_gdscs, + .num_power_domains = ARRAY_SIZE(msm8953_gdscs), + + .enable = msm8953_enable, + .set_rate = msm8953_set_rate, +}; + +static const struct udevice_id gcc_msm8953_of_match[] = { + { + .compatible = "qcom,gcc-msm8953", + .data = (ulong)&msm8953_clk_data, + }, + {} +}; + +U_BOOT_DRIVER(gcc_msm8953) = { + .name = "gcc_msm8953", + .id = UCLASS_NOP, + .of_match = gcc_msm8953_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC, +}; -- 2.55.0