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[71.218.31.69]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7f00d94389dsm271103a34.21.2026.07.28.10.44.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2026 10:44:11 -0700 (PDT) From: James Hilliard Date: Tue, 28 Jul 2026 11:41:52 -0600 Subject: [PATCH v6 09/13] clk: sunxi: add H6/H616 CE gates and reset MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260728-submit-ce-series-v2-v6-9-80c1f7daffa5@gmail.com> References: <20260728-submit-ce-series-v2-v6-0-80c1f7daffa5@gmail.com> In-Reply-To: <20260728-submit-ce-series-v2-v6-0-80c1f7daffa5@gmail.com> To: Svyatoslav Ryhel , Ion Agorria , Aspeed BMC SW team , Joel Stanley , u-boot@lists.u-boot-project.org Cc: Chen-Yu Tsai , Samuel Holland , Tom Rini , Simon Glass , James Hilliard , Thierry Reding , Quentin Schulz , Quentin Schulz , Marek Vasut , Marek Vasut , Rasmus Villemoes , Rasmus Villemoes , Aristo Chen , Anton Ivanov , Daniel Golle , Francois Berder , Peng Fan , Neil Armstrong , Randolph Sapp , Jonas Karlman , Wolfgang Wallner , Alexey Charkov , Ilias Apalodimas , Heiko Schocher , "Kory Maincent (TI.com)" , Anshul Dalal , Johan Jonker , Francesco Valla , Heinrich Schuchardt , Michael Walle , Andre Przywara , Lukasz Majewski , Richard Genoud , Michael Trimarchi , E Shattow , Enric Balletbo i Serra , Mattijs Korpershoek , Lucas Dietrich , David Lechner , Julien Stephan , Kuan-Wei Chiu , Bastien Curutchet , Raymond Mao , Ryan Chen , Chia-Wei Wang , "Lucien.Jheng" , Mateusz Furdyna , Dinesh Maniyam , Heiko Stuebner , Vincent Jardin X-Mailer: b4 0.15.2 X-Mailman-Approved-At: Wed, 29 Jul 2026 04:55:22 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785260652; x=1785865452; darn=lists.u-boot-project.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=O7Q3E5koZI/qBjSbZlBOEVkl/RbDviEV4YXV6llWwXM=; b=Ji8Vmjh2clkC4tudLw2ax3dhPzKthzf171j5yIv5DHD0Lz1+5Qo/IpAVybh6maqaiT Qzh5pUs31BOXK4PIV966ydgJ1FaxwxkdJ3XOP4xWgJ1SLZXQLKifuCiztVV/CTz5+Hdv kvva6y69WCa/vTPEkpUUCPHhsWchsJ9+QczbF2UUC87ReBb0VryAIko9KCjgq4tjF6ww DVo0rLbxkfr4D1mGnguDmEVXxhnPfSh4Erp3W3IOW+fvGr1dxxkbksqrgEDuj3zdlNlz EjfnLx3eYxNmv0idLAhtZn4QDkjdNRJzhtuz3cf+JZBfxA+ZwnoQGVSx1ZO0qauYxPsA FWPQ== X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dmarc=pass (p=none dis=none) header.from=gmail.com X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20251104 header.b=Ji8Vmjh2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Sender: "U-Boot" The H6 and H616 devicetrees describe the Crypto Engine with module, bus and MBUS clocks plus a bus reset. Add the corresponding gate and reset entries so drivers can enable the CE through the normal clock and reset uclasses in U-Boot proper. Reviewed-by: Simon Glass Signed-off-by: James Hilliard --- Changes v1 -> v2: - Add Simon's Reviewed-by tag --- drivers/clk/sunxi/clk_h6.c | 5 +++++ drivers/clk/sunxi/clk_h616.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c index 81deb5728e5..27ed5705a14 100644 --- a/drivers/clk/sunxi/clk_h6.c +++ b/drivers/clk/sunxi/clk_h6.c @@ -20,6 +20,10 @@ static struct ccu_clk_gate h6_gates[] = { [CLK_DE] = GATE(0x600, BIT(31)), [CLK_BUS_DE] = GATE(0x60c, BIT(0)), + [CLK_CE] = GATE(0x680, BIT(31)), + [CLK_BUS_CE] = GATE(0x68c, BIT(0)), + + [CLK_MBUS_CE] = GATE(0x804, BIT(2)), [CLK_MBUS_NAND] = GATE(0x804, BIT(5)), [CLK_NAND0] = GATE(0x810, BIT(31)), @@ -77,6 +81,7 @@ static struct ccu_clk_gate h6_gates[] = { static struct ccu_reset h6_resets[] = { [RST_BUS_DE] = RESET(0x60c, BIT(16)), + [RST_BUS_CE] = RESET(0x68c, BIT(16)), [RST_BUS_NAND] = RESET(0x82c, BIT(16)), [RST_BUS_MMC0] = RESET(0x84c, BIT(16)), diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c index 3e7eea25bfe..d5b659d0bb2 100644 --- a/drivers/clk/sunxi/clk_h616.c +++ b/drivers/clk/sunxi/clk_h616.c @@ -19,6 +19,10 @@ static struct ccu_clk_gate h616_gates[] = { [CLK_DE] = GATE(0x600, BIT(31)), [CLK_BUS_DE] = GATE(0x60c, BIT(0)), + [CLK_CE] = GATE(0x680, BIT(31)), + [CLK_BUS_CE] = GATE(0x68c, BIT(0)), + + [CLK_MBUS_CE] = GATE(0x804, BIT(2)), [CLK_MBUS_NAND] = GATE(0x804, BIT(5)), [CLK_NAND0] = GATE(0x810, BIT(31)), @@ -86,6 +90,7 @@ static struct ccu_clk_gate h616_gates[] = { static struct ccu_reset h616_resets[] = { [RST_BUS_DE] = RESET(0x60c, BIT(16)), + [RST_BUS_CE] = RESET(0x68c, BIT(16)), [RST_BUS_NAND] = RESET(0x82c, BIT(16)), [RST_BUS_MMC0] = RESET(0x84c, BIT(16)), -- 2.53.0