[PATCH] clk: rockchip: rk3066: set up the PLLs in U-Boot proper without TPL

["Yalçın Can" <ylcncn@gmail.com>]

The PLLs are set up by TPL. When U-Boot proper is started straight by the
boot ROM after a vendor DRAM init (no TPL), GPLL is still in slow mode and
the peripheral clocks run from the 24 MHz oscillator.

Also run rk3066_clk_init() in U-Boot proper when GPLL is found in slow
mode.

Tested on an MK808B (RK3066) with the vendor DRAM init and U-Boot from the
NAND ID blocks.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Signed-off-by: Yalçın Can <ylcncn@gmail.com>
---
 drivers/clk/rockchip/clk_rk3066.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3066.c b/drivers/clk/rockchip/clk_rk3066.c
index f7dea785..d48e4818 100644
--- a/drivers/clk/rockchip/clk_rk3066.c
+++ b/drivers/clk/rockchip/clk_rk3066.c
@@ -657,7 +657,13 @@ static int rk3066_clk_probe(struct udevice *dev)
 	priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
 #endif
 
-	if (IS_ENABLED(CONFIG_TPL_BUILD)) {
+	/*
+	 * Normally TPL sets up the PLLs. When U-Boot proper is started straight by the
+	 * boot ROM after a vendor DRAM init (no TPL), GPLL is still in slow mode: do it here.
+	 */
+	if (IS_ENABLED(CONFIG_TPL_BUILD) ||
+	    (!IS_ENABLED(CONFIG_XPL_BUILD) &&
+	     FIELD_GET(GPLL_MODE_MASK, readl(&priv->cru->cru_mode_con)) == PLL_MODE_SLOW)) {
 		rk3066_clk_init(priv->cru, priv->grf);
 
 		/* Init CPU frequency. */
-- 
2.47.3