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Mon, 2 Nov 2026 20:51:43 +0100 (CET) From: E Shattow To: u-boot@lists.u-boot-project.org, Sumit Garg , Yixun Lan , Tim Ouyang , Leo Liang , Yao Zi , Tom Rini , Guodong Xu Cc: Junhui Liu Subject: [PATCH v2 2/3] riscv: dts: spacemit: k3: Drop guest properties from M-level IMSIC Date: Mon, 2 Nov 2026 11:50:41 -0800 Message-ID: <20261102195101.103363-3-e@freeshell.de> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261102195101.103363-1-e@freeshell.de> References: <20261102195101.103363-1-e@freeshell.de> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Archive: List-Post: List-Help: List-Subscribe: , X-Spam-Status: No, score=-18.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Junhui Liu The mimsic node describes the machine-level IMSIC, whose MMIO region is 0x10000 (64 KiB) for all 8 harts. However, the node also specifies riscv,guest-index-bits = <6>, and per the AIA specification the per-hart stride is 2^(guest-index-bits + 12) bytes when guest interrupt files exist, i.e. 2^(6 + 12) = 256 KiB per hart and 2 MiB for all 8 harts. The described region cannot hold even a single hart's files, so the node contradicts itself. OpenSBI enforces exactly this constraint in imsic_data_check() and rejects the node with -EINVAL, preventing the M-level IMSIC from initializing: fdt_driver_init_by_offset: interrupt-controller@f1000000 (riscv,imsics) init failed: -3 init_coldboot: irqchip init failed (error -3) Moreover, guest interrupt files exist to act as the supervisor-level interrupt files of virtual harts; there is no machine-level counterpart. riscv,num-guest-ids is equally meaningless for the machine-level IMSIC. Drop both "riscv,guest-index-bits" and "riscv,num-guest-ids" properties from the mimsic node so the node matches the actual hardware layout. Fixes: 56f37e391a62 ("riscv: dts: spacemit: add initial support for K3 SoC") Signed-off-by: Junhui Liu Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260729-k3-mimsic-fix-v1-1-368c0aec04b9@pigmoral.tech Signed-off-by: Yixun Lan [ upstream commit: 01e2f07c44fc46180bdb10e70506f8acf44a53dd ] (cherry picked from commit d44cd4bcf93bb5c99a4762ed5f11656b93f9e5cc) --- dts/upstream/src/riscv/spacemit/k3.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/dts/upstream/src/riscv/spacemit/k3.dtsi b/dts/upstream/src/riscv/spacemit/k3.dtsi index c3f2dce0969c..2d022e1364f1 100644 --- a/dts/upstream/src/riscv/spacemit/k3.dtsi +++ b/dts/upstream/src/riscv/spacemit/k3.dtsi @@ -1287,9 +1287,7 @@ <&cpu4_intc 11>, <&cpu5_intc 11>, <&cpu6_intc 11>, <&cpu7_intc 11>; msi-controller; - riscv,guest-index-bits = <6>; riscv,hart-index-bits = <4>; - riscv,num-guest-ids = <511>; riscv,num-ids = <511>; status = "reserved"; }; -- 2.53.0