[PATCH 0/2] rockchip: ringneck-px30: always reset STM32 companion controller on boot

[PATCH 0/2] rockchip: ringneck-px30: always reset STM32 companion controller on boot

[Quentin Schulz]

It's happened that glitches on the STM32_RST and STM32_BOOT lines have
put the STM32 companion microcontroller into DFU mode making it not boot
its FW, rendering it useless for the user.

Considering that the STM32 companion microcontroller is always reset on
a reboot or power cycle, resetting it once again in U-Boot SPL isn't
going to hurt it any more.

For ATtiny companion microcontroller, the situation is a bit different
because a reboot or power cycle doesn't reset it. Additionally, since it
can only be reset with a UPDI reset on the STM32_RST line, and that is
virtually impossible to mistakenly trigger, the ATtiny is unlikely to be
in unwanted reset or enter reset because U-Boot toggles STM32_RST line.

This series adds this (sometimes) required reset of the MCU in U-Boot
SPL on Ringneck PX30 to recover from this unwanted DFU state.

Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
---
Quentin Schulz (2):
      rockchip: ringneck-px30: always reset STM32 companion controller on boot
      rockchip: ringneck-px30: enable SPL_BOARD_INIT

 .../ringneck_px30/ringneck-px30.c                  | 52 ++++++++++++++++++++++
 configs/ringneck-px30_defconfig                    |  1 +
 2 files changed, 53 insertions(+)
---
base-commit: 351da15f71e3d70dbc63e90781b403415452d864
change-id: 20231024-ringneck-stm32-reset-b5b7e7355ae4

Best regards,
-- 
Quentin Schulz <quentin.schulz@theobroma-systems.com>

[PATCH 1/2] rockchip: ringneck-px30: always reset STM32 companion controller on boot

[Quentin Schulz]

From: Quentin Schulz <quentin.schulz@theobroma-systems.com>

It's happened that glitches on the STM32_RST and STM32_BOOT lines have
put the STM32 companion microcontroller into DFU mode making it not boot
its FW, rendering it useless for the user.

Considering that the STM32 companion microcontroller is always reset on
a reboot or power cycle, resetting it once again in U-Boot SPL isn't
going to hurt it any more.

For ATtiny companion microcontroller, the situation is a bit different
because a reboot or power cycle doesn't reset it. Additionally, since it
can only be reset with a UPDI reset on the STM32_RST line, and that is
virtually impossible to mistakenly trigger, the ATtiny is unlikely to be
in unwanted reset or enter reset because U-Boot toggles STM32_RST line.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
---
 .../ringneck_px30/ringneck-px30.c                  | 52 ++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/board/theobroma-systems/ringneck_px30/ringneck-px30.c b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
index bb1bb4acf5c..804a991e281 100644
--- a/board/theobroma-systems/ringneck_px30/ringneck-px30.c
+++ b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
@@ -16,12 +16,14 @@
 #include <usb.h>
 #include <dm/pinctrl.h>
 #include <dm/uclass-internal.h>
+#include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/setup.h>
 #include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/hardware.h>
 #include <asm/arch-rockchip/periph.h>
 #include <asm/arch-rockchip/misc.h>
+#include <linux/delay.h>
 #include <power/regulator.h>
 #include <u-boot/sha256.h>
 
@@ -169,3 +171,53 @@ int misc_init_r(void)
 
 	return 0;
 }
+
+#define STM32_RST	100 // GPIO3_A4
+#define STM32_BOOT	101 // GPIO3_A5
+
+void spl_board_init(void)
+{
+	/*
+	 * Glitches on STM32_BOOT and STM32_RST lines during poweroff or power
+	 * on may put the STM32 companion microcontroller into DFU mode, let's
+	 * always reset it into normal mode instead.
+	 * Toggling the STM32_RST line is safe to do with the ATtiny companion
+	 * microcontroller variant because it will not trigger an MCU reset
+	 * since only a UPDI reset command will. Since a UPDI reset is difficult
+	 * to mistakenly trigger, glitches to the lines are theoretically also
+	 * incapable of triggering an actual ATtiny reset.
+	 */
+	int ret = gpio_request(STM32_RST, "STM32_RST");
+
+	if (ret) {
+		debug("Failed to request STM32_RST\n");
+		return;
+	}
+
+	ret = gpio_request(STM32_BOOT, "STM32_BOOT");
+	if (ret) {
+		debug("Failed to request STM32_BOOT\n");
+		return;
+	}
+
+	// Rely on HW pull-down for inactive level
+	ret = gpio_direction_input(STM32_BOOT);
+	if (ret) {
+		debug("Failed to configure STM32_BOOT\n");
+		return;
+	}
+
+	ret = gpio_direction_output(STM32_RST, 0);
+	if (ret) {
+		debug("Failed to configure STM32_RST\n");
+		return;
+	}
+
+	mdelay(1);
+
+	ret = gpio_direction_output(STM32_RST, 1);
+	if (ret) {
+		debug("Failed to configure STM32_RST\n");
+		return;
+	}
+}

-- 
2.41.0

[PATCH 2/2] rockchip: ringneck-px30: enable SPL_BOARD_INIT

[Quentin Schulz]

From: Quentin Schulz <quentin.schulz@theobroma-systems.com>

Now that Ringneck requires some board-specific code (namely resetting
the MCU companion controller) to be run during SPL stage, let's enable
SPL_BOARD_INIT.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
---
 configs/ringneck-px30_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index b4666d0e90f..420c9cd1e89 100644
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -38,6 +38,7 @@ CONFIG_SPL_PAD_TO=0x0
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x4000000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
+CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set

-- 
2.41.0

Re: [PATCH 1/2] rockchip: ringneck-px30: always reset STM32 companion controller on boot

[Heiko Stübner]

Hi Quentin,

Am Mittwoch, 25. Oktober 2023, 11:51:14 CEST schrieb Quentin Schulz:
> From: Quentin Schulz <quentin.schulz@theobroma-systems.com>
> 
> It's happened that glitches on the STM32_RST and STM32_BOOT lines have
> put the STM32 companion microcontroller into DFU mode making it not boot
> its FW, rendering it useless for the user.
> 
> Considering that the STM32 companion microcontroller is always reset on
> a reboot or power cycle, resetting it once again in U-Boot SPL isn't
> going to hurt it any more.
> 
> For ATtiny companion microcontroller, the situation is a bit different
> because a reboot or power cycle doesn't reset it. Additionally, since it
> can only be reset with a UPDI reset on the STM32_RST line, and that is
> virtually impossible to mistakenly trigger, the ATtiny is unlikely to be
> in unwanted reset or enter reset because U-Boot toggles STM32_RST line.
> 
> Cc: Quentin Schulz <foss+uboot@0leil.net>
> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
> ---
>  .../ringneck_px30/ringneck-px30.c                  | 52 ++++++++++++++++++++++
>  1 file changed, 52 insertions(+)
> 
> diff --git a/board/theobroma-systems/ringneck_px30/ringneck-px30.c b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
> index bb1bb4acf5c..804a991e281 100644
> --- a/board/theobroma-systems/ringneck_px30/ringneck-px30.c
> +++ b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
> @@ -16,12 +16,14 @@
>  #include <usb.h>
>  #include <dm/pinctrl.h>
>  #include <dm/uclass-internal.h>
> +#include <asm/gpio.h>
>  #include <asm/io.h>
>  #include <asm/setup.h>
>  #include <asm/arch-rockchip/clock.h>
>  #include <asm/arch-rockchip/hardware.h>
>  #include <asm/arch-rockchip/periph.h>
>  #include <asm/arch-rockchip/misc.h>
> +#include <linux/delay.h>
>  #include <power/regulator.h>
>  #include <u-boot/sha256.h>
>  
> @@ -169,3 +171,53 @@ int misc_init_r(void)
>  
>  	return 0;
>  }
> +
> +#define STM32_RST	100 // GPIO3_A4
> +#define STM32_BOOT	101 // GPIO3_A5

is "//" the preferred comment style in u-boot?
I'd somehow expect  "/* GPIO3_A4 */"


> +void spl_board_init(void)
> +{
> +	/*
> +	 * Glitches on STM32_BOOT and STM32_RST lines during poweroff or power
> +	 * on may put the STM32 companion microcontroller into DFU mode, let's
> +	 * always reset it into normal mode instead.
> +	 * Toggling the STM32_RST line is safe to do with the ATtiny companion
> +	 * microcontroller variant because it will not trigger an MCU reset
> +	 * since only a UPDI reset command will. Since a UPDI reset is difficult
> +	 * to mistakenly trigger, glitches to the lines are theoretically also
> +	 * incapable of triggering an actual ATtiny reset.
> +	 */
> +	int ret = gpio_request(STM32_RST, "STM32_RST");
> +

nit: int ret;
ret = gpio_request()

so that is connects to the if(ret) below it, like the others?

> +	if (ret) {
> +		debug("Failed to request STM32_RST\n");
> +		return;
> +	}
> +
> +	ret = gpio_request(STM32_BOOT, "STM32_BOOT");
> +	if (ret) {
> +		debug("Failed to request STM32_BOOT\n");
> +		return;
> +	}
> +
> +	// Rely on HW pull-down for inactive level

nit: /* foo */ ?

> +	ret = gpio_direction_input(STM32_BOOT);
> +	if (ret) {
> +		debug("Failed to configure STM32_BOOT\n");
> +		return;
> +	}
> +
> +	ret = gpio_direction_output(STM32_RST, 0);
> +	if (ret) {
> +		debug("Failed to configure STM32_RST\n");
> +		return;
> +	}
> +
> +	mdelay(1);
> +
> +	ret = gpio_direction_output(STM32_RST, 1);
> +	if (ret) {
> +		debug("Failed to configure STM32_RST\n");
> +		return;
> +	}
> +}


Heiko

Re: [PATCH 2/2] rockchip: ringneck-px30: enable SPL_BOARD_INIT

[Heiko Stübner]

Am Mittwoch, 25. Oktober 2023, 11:51:15 CEST schrieb Quentin Schulz:
> From: Quentin Schulz <quentin.schulz@theobroma-systems.com>
> 
> Now that Ringneck requires some board-specific code (namely resetting
> the MCU companion controller) to be run during SPL stage, let's enable
> SPL_BOARD_INIT.
> 
> Cc: Quentin Schulz <foss+uboot@0leil.net>
> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

> ---
>  configs/ringneck-px30_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
> index b4666d0e90f..420c9cd1e89 100644
> --- a/configs/ringneck-px30_defconfig
> +++ b/configs/ringneck-px30_defconfig
> @@ -38,6 +38,7 @@ CONFIG_SPL_PAD_TO=0x0
>  CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
>  CONFIG_SPL_BSS_START_ADDR=0x4000000
>  CONFIG_SPL_BSS_MAX_SIZE=0x4000
> +CONFIG_SPL_BOARD_INIT=y
>  CONFIG_SPL_BOOTROM_SUPPORT=y
>  # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
>  # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
> 
>