From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00C68C433FE for ; Wed, 9 Nov 2022 07:32:37 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 52E5D84E7F; Wed, 9 Nov 2022 08:32:35 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="NgRdE/IZ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 2335784E7F; Wed, 9 Nov 2022 08:32:34 +0100 (CET) Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1476084FF9 for ; Wed, 9 Nov 2022 08:32:28 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=macpaul.lin@mediatek.com X-UUID: b1ba1811d6e946aa8d0c520126d45c31-20221109 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From:References:CC:To:Subject:MIME-Version:Date:Message-ID; bh=VVC4GY4HBNbzbwRtuYpupx2X4olzLrFu+e+vhE9Avt4=; b=NgRdE/IZ1abUEfj2N4h+kaYDDs9QHQhLd9h5MwIR9+crRc2Jyth3wUvc6nphReEaN76QyAevwbfL0eW7gF3SI3/9xf+m/YMTX19Dra/tzhBZwVrykb7alb4uy4hzh/jpQ4CrHZv/a/IYvcB5QRcJxRLEaok9rxqcqM16oTn0Sdc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12, REQID:debceb77-6943-4020-bbba-bba4bc8eedfb, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:62cd327, CLOUDID:ba610c91-1a78-4832-bd08-74b1519dcfbf, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: b1ba1811d6e946aa8d0c520126d45c31-20221109 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1495824136; Wed, 09 Nov 2022 15:32:08 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 9 Nov 2022 15:32:06 +0800 Received: from [172.21.84.99] (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 9 Nov 2022 15:32:03 +0800 Message-ID: <20b70a87-182e-d839-13d8-c8a21a254d4e@mediatek.com> Date: Wed, 9 Nov 2022 15:32:02 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH 1/2] arm: mediatek: add mt8195 SOC support Content-Language: en-US To: =?UTF-8?B?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= , "fparent@baylibre.com" , "marex@denx.de" , "sjg@chromium.org" , "marcel.ziswiler@toradex.com" , "aouledameur@baylibre.com" , "frieder.schrempf@kontron.de" , "philippe.reynes@softathome.com" , "u-boot@lists.denx.de" , GSS_MTK_Uboot_upstream , "william.zhang@broadcom.com" , "samuel@sholland.org" , "festevam@denx.de" , =?UTF-8?B?V2VpamllIEdhbyAo6auY5oOf5p2wKQ==?= , Ryder Lee , "paul.liu@linaro.org" CC: =?UTF-8?B?TWlsZXMgQ2hlbiAo6Zmz5rCR5qi6KQ==?= , =?UTF-8?B?QmVhciBXYW5nICjokKnljp/mg5/lvrcp?= , "macpaul@gmail.com" , =?UTF-8?B?UGFibG8gU3VuICjlravmr5Pnv5Qp?= References: <20221108032149.22447-1-macpaul.lin@mediatek.com> <603e4a1b8fea79d47e9de49fd20d14f76c14fe4b.camel@mediatek.com> From: Macpaul Lin In-Reply-To: <603e4a1b8fea79d47e9de49fd20d14f76c14fe4b.camel@mediatek.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On 11/9/22 10:07, Chunfeng Yun (云春峰) wrote: > On Tue, 2022-11-08 at 11:21 +0800, Macpaul Lin wrote: >> From: Fabien Parent >> >> The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 >> and >> a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and >> hosts, >> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 >> and LPDDR4 options. >> >> Signed-off-by: Fabien Parent >> Signed-off-by: Macpaul Lin >> --- >> MAINTAINERS | 2 + >> arch/arm/dts/mt8195.dtsi | 317 >> +++++++++++++++++++++++++ >> arch/arm/mach-mediatek/Kconfig | 13 +- >> arch/arm/mach-mediatek/Makefile | 1 + >> arch/arm/mach-mediatek/mt8195/Makefile | 3 + >> arch/arm/mach-mediatek/mt8195/init.c | 81 +++++++ >> 6 files changed, 416 insertions(+), 1 deletion(-) >> create mode 100644 arch/arm/dts/mt8195.dtsi >> create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile >> create mode 100644 arch/arm/mach-mediatek/mt8195/init.c [deleted] >> + u3phy0: usb-phy@11f40000 { > change node name as t-phy as u3phy3? > Got it, will fix it in next version. >> + compatible = "mediatek,generic-tphy-v2"; > prefer to add "mediatek,mt8195-tphy" before generic's > Will fix it in next version. >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0 0 0x11e40000 0xe00>; >> + status = "okay"; >> + >> + u2port0: usb-phy@0 { >> + reg = <0 0x700>; >> + clocks = <&clk26m>, >> + <&clk26m>; >> + clock-names = "ref", "da_ref"; > these two clocks are optional, if sw can't control it, no need add it > here. MediaTek's clock driver developer will upstream clock driver when refactoring work has been completed. Before clock driver is applied to trunk, we can use clk26m only. Will fix it in next version. >> + #phy-cells = <1>; >> + status = "okay"; >> + }; >> + >> + u3port0: usb-phy@700 { >> + reg = <0x700 0x700>; >> + clocks = <&clk26m>, >> + <&clk26m>; >> + clock-names = "ref", "da_ref"; > ditto > Will fix it in next version. >> + #phy-cells = <1>; >> + status = "okay"; >> + }; >> + }; >> + >> + usb: usb@11200000 { >> + compatible ="mediatek,mt8195-mtu3", >> "mediatek,mtu3"; >> + reg = <0 0x11200000 0 0x3e00>, >> + <0 0x11203e00 0 0x0100>; >> + reg-names = "mac", "ippc"; > "mac" can be removed, the driver get it from the first child node > Will fix it in next version. >> + phys = <&u2port0 PHY_TYPE_USB2>; >> + clocks = <&clk26m>, >> + <&clk26m>, >> + <&clk26m>; >> + clock-names = "sys_ck", "ref_ck", "mcu_ck"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + status = "disabled"; >> + >> + ssusb: ssusb@11200000 { >> + compatible = "mediatek,ssusb"; >> + reg = <0 0x11200000 0 0x3e00>; >> + reg-names = "mac"; >> + interrupts = > IRQ_TYPE_LEVEL_LOW>; >> + status = "disabled"; >> + }; >> + >> + xhci0: xhci@11200000 { >> + compatible = "mediatek,mtk-xhci"; >> + reg = <0 0x11200000 0 0x1000>; >> + reg-names = "mac"; >> + interrupts = > IRQ_TYPE_LEVEL_LOW>; >> + clocks = <&clk26m>, >> + <&clk26m>, >> + <&clk26m>, >> + <&clk26m>; >> + clock-names = "sys_ck", "xhci_ck", >> "ref_ck", "mcu_ck"; >> + status = "disabled"; >> + }; >> + }; >> + >> + u3phy3: t-phy@11c50000 { >> + compatible = "mediatek,generic-tphy-v2"; > add specific one > Will fix it in next version. >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0 0 0x11c50000 0x700>; >> + status = "okay"; >> + >> + u2port3: usb-phy@0 { >> + reg = <0x0 0x700>; >> + clocks = <&clk26m>; >> + clock-names = "ref"; >> + #phy-cells = <1>; >> + }; >> + }; >> + >> + xhci3: xhci3@112b0000 { > change node name as xhci? prefer to use the same name > Since there are other board manufacturers will use the other HOST ports, like xhci1 or xhci2 with USB mass storage function by their needs. I'll add these 2 node in dtsi in next version. >> + compatible = "mediatek,mt8195-xhci", >> + "mediatek,mtk-xhci"; >> + reg = <0 0x112b0000 0 0x1000>, >> + <0 0x112b3e00 0 0x0100>; >> + reg-names = "mac", "ippc"; > remove "mac" Will fix it in next version. >> + interrupts = ; >> + phys = <&u2port3 PHY_TYPE_USB2>; >> + clocks = <&clk26m>, >> + <&clk26m>, >> + <&clk26m>; >> + clock-names = "sys_ck", "xhci_ck", "ref_ck"; >> + usb2-lpm-disable; >> + status = "disabled"; >> + }; >> + }; >> +}; >> diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach- >> mediatek/Kconfig >> index 04aa2fd97f..3a2af1cdee 100644 >> --- a/arch/arm/mach-mediatek/Kconfig >> +++ b/arch/arm/mach-mediatek/Kconfig >> @@ -67,6 +67,15 @@ config TARGET_MT8183 >> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several >> LPDDR3 >> and LPDDR4 options. >> >> +config TARGET_MT8195 >> + bool "MediaTek MT8195 SoC" >> + select ARM64 >> + help >> + The MediaTek MT8195 is a ARM64-based SoC with a quad-core >> Cortex-A73 and >> + a quad-core Cortex-A53. It is including UART, SPI, USB3.0 >> device and hosts, >> + SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several >> LPDDR3 >> + and LPDDR4 options. >> + >> config TARGET_MT8512 >> bool "MediaTek MT8512 M1 Board" >> select ARM64 >> @@ -105,6 +114,7 @@ config SYS_BOARD >> default "mt7981" if TARGET_MT7981 >> default "mt7986" if TARGET_MT7986 >> default "mt8183" if TARGET_MT8183 >> + default "mt8195" if TARGET_MT8195 >> default "mt8512" if TARGET_MT8512 >> default "mt8516" if TARGET_MT8516 >> default "mt8518" if TARGET_MT8518 >> @@ -122,6 +132,7 @@ config SYS_CONFIG_NAME >> default "mt7981" if TARGET_MT7981 >> default "mt7986" if TARGET_MT7986 >> default "mt8183" if TARGET_MT8183 >> + default "mt8195" if TARGET_MT8195 >> default "mt8512" if TARGET_MT8512 >> default "mt8516" if TARGET_MT8516 >> default "mt8518" if TARGET_MT8518 >> @@ -134,7 +145,7 @@ config SYS_CONFIG_NAME >> config MTK_BROM_HEADER_INFO >> string >> default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || >> TARGET_MT7629 || TARGET_MT7622 >> - default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || >> TARGET_MT8183 >> + default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || >> TARGET_MT8183 || TARGET_MT8195 >> default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || >> TARGET_MT7986 >> default "lk=1" if TARGET_MT7623 >> >> diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach- >> mediatek/Makefile >> index fc85293f71..fbbb5431d1 100644 >> --- a/arch/arm/mach-mediatek/Makefile >> +++ b/arch/arm/mach-mediatek/Makefile >> @@ -10,5 +10,6 @@ obj-$(CONFIG_TARGET_MT7629) += mt7629/ >> obj-$(CONFIG_TARGET_MT7981) += mt7981/ >> obj-$(CONFIG_TARGET_MT7986) += mt7986/ >> obj-$(CONFIG_TARGET_MT8183) += mt8183/ >> +obj-$(CONFIG_TARGET_MT8195) += mt8195/ >> obj-$(CONFIG_TARGET_MT8516) += mt8516/ >> obj-$(CONFIG_TARGET_MT8518) += mt8518/ >> diff --git a/arch/arm/mach-mediatek/mt8195/Makefile b/arch/arm/mach- >> mediatek/mt8195/Makefile >> new file mode 100644 >> index 0000000000..886ab7e4eb >> --- /dev/null >> +++ b/arch/arm/mach-mediatek/mt8195/Makefile >> @@ -0,0 +1,3 @@ >> +# SPDX-License-Identifier: GPL-2.0 >> + >> +obj-y += init.o >> diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach- >> mediatek/mt8195/init.c >> new file mode 100644 >> index 0000000000..1eb4ade6c5 >> --- /dev/null >> +++ b/arch/arm/mach-mediatek/mt8195/init.c >> @@ -0,0 +1,81 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Copyright (C) 2022 MediaTek Inc. >> + * Copyright (C) 2022 BayLibre, SAS >> + * Author: Macpaul Lin >> + * Author: Fabien Parent >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +DECLARE_GLOBAL_DATA_PTR; >> + >> +int dram_init(void) >> +{ >> + int ret; >> + >> + ret = fdtdec_setup_memory_banksize(); >> + if (ret) >> + return ret; >> + >> + return fdtdec_setup_mem_size_base(); >> +} >> + >> +int dram_init_banksize(void) >> +{ >> + gd->bd->bi_dram[0].start = gd->ram_base; >> + gd->bd->bi_dram[0].size = gd->ram_size; >> + >> + return 0; >> +} >> + >> +int mtk_pll_early_init(void) >> +{ >> + return 0; >> +} >> + >> +int mtk_soc_early_init(void) >> +{ >> + return 0; >> +} >> + >> +void reset_cpu(ulong addr) >> +{ >> + psci_system_reset(); >> +} >> + >> +int print_cpuinfo(void) >> +{ >> + printf("CPU: MediaTek MT8195\n"); >> + return 0; >> +} >> + >> +static struct mm_region mt8195_mem_map[] = { >> + { >> + /* DDR */ >> + .virt = 0x40000000UL, >> + .phys = 0x40000000UL, >> + .size = 0x80000000UL, >> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | >> PTE_BLOCK_OUTER_SHARE, >> + }, { >> + .virt = 0x00000000UL, >> + .phys = 0x00000000UL, >> + .size = 0x20000000UL, >> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | >> + PTE_BLOCK_NON_SHARE | >> + PTE_BLOCK_PXN | PTE_BLOCK_UXN >> + }, { >> + 0, >> + } >> +}; >> + >> +struct mm_region *mem_map = mt8195_mem_map; Thanks a lot! Macpaul Lin