From mboxrd@z Thu Jan 1 00:00:00 1970 From: Philippe REYNES Date: Mon, 9 Mar 2020 19:48:10 +0100 (CET) Subject: [PATCH 1/3] nand: brcmnand: add bcmbca support In-Reply-To: <20200220121808.15970-2-nicolas.heemeryck@gmail.com> References: <20200220121808.15970-1-nicolas.heemeryck@gmail.com> <20200220121808.15970-2-nicolas.heemeryck@gmail.com> Message-ID: <214154585.1280423.1583779690848.JavaMail.zimbra@softathome.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de > Almost all Broadcom BCA (Broadband Carrier Access) platforms based on > ARM use the same nand controller. > So rather than adding a bcm6xxx_nand.c per Broadcom SoC, use a unified > nand controller based on the existing one and selectable through > NAND_BRCMNAND_BCMBCA. > > The bcmbca controller should support all ARM based bcm63xxx, bcm68xx, > bcm67xx and bcm490x SoCs. > > Signed-off-by: Nicolas Heemeryck > Cc: Philippe Reynes Reviewed-by: Philippe Reynes > --- > drivers/mtd/nand/raw/Kconfig | 6 + > drivers/mtd/nand/raw/brcmnand/Makefile | 1 + > drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c | 124 ++++++++++++++++++++ > 3 files changed, 131 insertions(+) > create mode 100644 drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c > > diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig > index 23201ca720..c37e2e96c2 100644 > --- a/drivers/mtd/nand/raw/Kconfig > +++ b/drivers/mtd/nand/raw/Kconfig > @@ -102,6 +102,12 @@ config NAND_BRCMNAND_63158 > help > Enable support for broadcom nand driver on bcm63158. > > +config NAND_BRCMNAND_BCMBCA > + bool "Support Broadcom NAND controller for BCA platforms" > + depends on NAND_BRCMNAND && (ARM64 || CPU_V7A) > + help > + Enable support for broadcom nand driver for BCA platforms. > + > config NAND_DAVINCI > bool "Support TI Davinci NAND controller" > help > diff --git a/drivers/mtd/nand/raw/brcmnand/Makefile > b/drivers/mtd/nand/raw/brcmnand/Makefile > index 5d9e7e3f3b..61203bf5ff 100644 > --- a/drivers/mtd/nand/raw/brcmnand/Makefile > +++ b/drivers/mtd/nand/raw/brcmnand/Makefile > @@ -5,5 +5,6 @@ obj-$(CONFIG_NAND_BRCMNAND_63158) += bcm63158_nand.o > obj-$(CONFIG_NAND_BRCMNAND_68360) += bcm68360_nand.o > obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o > obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o > +obj-$(CONFIG_NAND_BRCMNAND_BCMBCA) += bcmbca_nand.o > obj-$(CONFIG_NAND_BRCMNAND) += brcmnand.o > obj-$(CONFIG_NAND_BRCMNAND) += brcmnand_compat.o > diff --git a/drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c > b/drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c > new file mode 100644 > index 0000000000..91b0a33397 > --- /dev/null > +++ b/drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c > @@ -0,0 +1,124 @@ > +// SPDX-License-Identifier: GPL-2.0+ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "brcmnand.h" > + > +struct bcmbca_nand_soc { > + struct brcmnand_soc soc; > + void __iomem *base; > +}; > + > +#define BCMBCA_NAND_INT 0x00 > +#define BCMBCA_NAND_STATUS_SHIFT 0 > +#define BCMBCA_NAND_STATUS_MASK (0xfff << BCMBCA_NAND_STATUS_SHIFT) > + > +#define BCMBCA_NAND_INT_EN 0x04 > +#define BCMBCA_NAND_ENABLE_SHIFT 0 > +#define BCMBCA_NAND_ENABLE_MASK (0xffff << BCMBCA_NAND_ENABLE_SHIFT) > + > +enum { > + BCMBCA_NP_READ = BIT(0), > + BCMBCA_BLOCK_ERASE = BIT(1), > + BCMBCA_COPY_BACK = BIT(2), > + BCMBCA_PAGE_PGM = BIT(3), > + BCMBCA_CTRL_READY = BIT(4), > + BCMBCA_DEV_RBPIN = BIT(5), > + BCMBCA_ECC_ERR_UNC = BIT(6), > + BCMBCA_ECC_ERR_CORR = BIT(7), > +}; > + > +static bool bcmbca_nand_intc_ack(struct brcmnand_soc *soc) > +{ > + struct bcmbca_nand_soc *priv = > + container_of(soc, struct bcmbca_nand_soc, soc); > + void __iomem *mmio = priv->base + BCMBCA_NAND_INT; > + u32 val = brcmnand_readl(mmio); > + > + if (val & (BCMBCA_CTRL_READY << BCMBCA_NAND_STATUS_SHIFT)) { > + /* Ack interrupt */ > + val &= ~BCMBCA_NAND_STATUS_MASK; > + val |= BCMBCA_CTRL_READY << BCMBCA_NAND_STATUS_SHIFT; > + brcmnand_writel(val, mmio); > + return true; > + } > + > + return false; > +} > + > +static void bcmbca_nand_intc_set(struct brcmnand_soc *soc, bool en) > +{ > + struct bcmbca_nand_soc *priv = > + container_of(soc, struct bcmbca_nand_soc, soc); > + void __iomem *mmio = priv->base + BCMBCA_NAND_INT_EN; > + u32 val = brcmnand_readl(mmio); > + > + /* Don't ack any interrupts */ > + val &= ~BCMBCA_NAND_STATUS_MASK; > + > + if (en) > + val |= BCMBCA_CTRL_READY << BCMBCA_NAND_ENABLE_SHIFT; > + else > + val &= ~(BCMBCA_CTRL_READY << BCMBCA_NAND_ENABLE_SHIFT); > + > + brcmnand_writel(val, mmio); > +} > + > +static int bcmbca_nand_probe(struct udevice *dev) > +{ > + struct udevice *pdev = dev; > + struct bcmbca_nand_soc *priv = dev_get_priv(dev); > + struct brcmnand_soc *soc; > + struct resource res; > + > + soc = &priv->soc; > + > + dev_read_resource_byname(pdev, "nand-int-base", &res); > + priv->base = devm_ioremap(dev, res.start, resource_size(&res)); > + if (IS_ERR(priv->base)) > + return PTR_ERR(priv->base); > + > + soc->ctlrdy_ack = bcmbca_nand_intc_ack; > + soc->ctlrdy_set_enabled = bcmbca_nand_intc_set; > + > + /* Disable and ack all interrupts */ > + brcmnand_writel(0, priv->base + BCMBCA_NAND_INT_EN); > + brcmnand_writel(0, priv->base + BCMBCA_NAND_INT); > + > + return brcmnand_probe(pdev, soc); > +} > + > +static const struct udevice_id bcmbca_nand_dt_ids[] = { > + { .compatible = "brcm,nand-bcmbca" }, > + { .compatible = "brcm,nand-bcm63158" }, > + { .compatible = "brcm,nand-bcm68360" }, > + { .compatible = "brcm,nand-bcm6858" }, > + { /* sentinel */ } > +}; > + > +U_BOOT_DRIVER(bcmbca_nand) = { > + .name = "bcmbca-nand", > + .id = UCLASS_MTD, > + .of_match = bcmbca_nand_dt_ids, > + .probe = bcmbca_nand_probe, > + .priv_auto_alloc_size = sizeof(struct bcmbca_nand_soc), > +}; > + > +void board_nand_init(void) > +{ > + struct udevice *dev; > + int ret; > + > + ret = uclass_get_device_by_driver(UCLASS_MTD, > + DM_GET_DRIVER(bcmbca_nand), &dev); > + if (ret && ret != -ENODEV) > + pr_err("Failed to initialize %s. (error %d)\n", dev->name, > + ret); > +} > -- > 2.20.1