From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31615C43334 for ; Thu, 23 Jun 2022 13:40:31 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7EAF883FF6; Thu, 23 Jun 2022 15:40:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=sntech.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 61949842E0; Thu, 23 Jun 2022 15:40:27 +0200 (CEST) Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B089380084 for ; Thu, 23 Jun 2022 15:40:24 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=heiko@sntech.de Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1o4N4F-0001wj-8l; Thu, 23 Jun 2022 15:40:19 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Rick Chen , Leo , Aurelien Jarno , Heinrich Schuchardt , u-boot@lists.denx.de Cc: Alexandre Ghiti , Alexandre Ghiti , Coelacanthus Subject: Re: [PATCH] riscv: Fix build against binutils 2.38 Date: Thu, 23 Jun 2022 15:40:18 +0200 Message-ID: <2249202.ElGaqSPkdT@diego> In-Reply-To: <20220128134713.2322800-1-alexandre.ghiti@canonical.com> References: <20220128134713.2322800-1-alexandre.ghiti@canonical.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Am Freitag, 28. Januar 2022, 14:47:13 CEST schrieb Alexandre Ghiti: > The following description is copied from the equivalent patch for the > Linux Kernel proposed by Aurelien Jarno: > > From version 2.38, binutils default to ISA spec version 20191213. This > means that the csr read/write (csrr*/csrw*) instructions and fence.i > instruction has separated from the `I` extension, become two standalone > extensions: Zicsr and Zifencei. As the kernel uses those instruction, > this causes the following build failure: > > arch/riscv/cpu/mtrap.S: Assembler messages: > arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' > arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' > arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' > arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' > > Signed-off-by: Alexandre Ghiti After upgrading my binutils to the recent snapshot package in Debian-unstable (2.38.50.20220622-1), I've also run into that issue: /home/devel/hstuebner/04_riscv/sun20i_d1_u-boot/drivers/timer/riscv_timer.c: Assembler messages: /home/devel/hstuebner/04_riscv/sun20i_d1_u-boot/drivers/timer/riscv_timer.c:24: Error: unrecognized opcode `csrr a0,0xc01', extension `zicsr' required make[3]: *** [/home/devel/hstuebner/04_riscv/sun20i_d1_u-boot/scripts/Makefile.build:254: drivers/timer/riscv_timer.o] Fehler 1 Is there progress in getting this patch applied to u-boot in some way? Also it looks like there was another patch with similar content submitted recently [0]. In any case: On a D1-Nezha it fixes the build (and boot) Tested-by: Heiko Stuebner Thanks Heiko [0] https://lore.kernel.org/all/PH7PR14MB5594FD11D1BE74284F554BEBCED49@PH7PR14MB5594.namprd14.prod.outlook.com/ > --- > arch/riscv/Makefile | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > index 0b80eb8d86..53d1194ffb 100644 > --- a/arch/riscv/Makefile > +++ b/arch/riscv/Makefile > @@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) > CMODEL = medany > endif > > -ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \ > +RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C) > + > +# Newer binutils versions default to ISA spec version 20191213 which moves some > +# instructions from the I extension to the Zicsr and Zifencei extensions. > +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei) > +ifeq ($(toolchain-need-zicsr-zifencei),y) > + RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei > +endif > + > +ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ > -mcmodel=$(CMODEL) > > PLATFORM_CPPFLAGS += $(ARCH_FLAGS) >