* [PATCH v2 1/3] bsh: update readme with instructions to build M2B
@ 2025-10-30 8:47 Andrea Calabrese
2025-10-30 8:47 ` [PATCH v2 2/3] bsh: imx6ulz_smm_m2: Update imx6ulz BSH SMM M2B board Andrea Calabrese
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Andrea Calabrese @ 2025-10-30 8:47 UTC (permalink / raw)
To: u-boot, michael, dario.binacchi, trini, festevam; +Cc: andrea.calabrese
readme was missing instructions to build M2B. Now added.
Signed-off-by: Andrea Calabrese <andrea.calabrese@amarulasolutions.com>
diff --git a/board/bsh/imx6ulz_smm_m2/README b/board/bsh/imx6ulz_smm_m2/README
deleted file mode 100644
index 03d01325a97..00000000000
--- a/board/bsh/imx6ulz_smm_m2/README
+++ /dev/null
@@ -1,67 +0,0 @@
-How to Update U-Boot on imx6ulz_smm_m2 board
---------------------------------------------
-
-Required software on the host PC:
-
-- UUU: https://github.com/NXPmicro/mfgtools
-
-Build U-Boot for m2:
-
-$ make mrproper
-$ make imx6ulz_smm_m2_defconfig
-$ make
-
-This generates the SPL and u-boot-dtb.img binaries.
-
-1. Loading U-Boot via USB Serial Download Protocol
-
-Copy SPL and u-boot-dtb.img to the uuu folder.
-
-Load the U-Boot via USB:
-
-$ sudo uuu -v -b nand_script.lst u-boot-with-spl.imx
-
-where nand_script.lst contains the following:
-
-uuu_version 1.2.39
-
-# @_flash.bin | bootloader
-# @_image [_flash.bin] | image burn to nand, default is the same as bootloader
-
-# This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ
-SDP: boot -f _flash.bin
-
-# This command will be run when ROM support stream mode
-# i.MX8QXP, i.MX8QM
-SDPS: boot -f _flash.bin
-
-# These commands will be run when use SPL and will be skipped if no spl
-# SDPU will be deprecated. please use SDPV instead of SDPU
-# {
-SDPU: delay 1000
-SDPU: write -f _flash.bin -offset 0x57c00
-SDPU: jump
-# }
-
-# These commands will be run when use SPL and will be skipped if no spl
-# if (SPL support SDPV)
-# {
-SDPV: delay 1000
-SDPV: write -f _flash.bin -offset 0x11000
-SDPV: jump
-# }
-
-FB: ucmd setenv fastboot_buffer ${loadaddr}
-FB: download -f _image
-FB: ucmd if test ! -n "$fastboot_bytes"; then setenv fastboot_bytes $filesize; else true; fi
-# Burn image to nandfit partition if needed
-FB: ucmd if env exists nandfit_part; then nand erase.part nandfit; nand write ${fastboot_buffer} nandfit ${fastboot_bytes}; else true; fi;
-FB: ucmd nandbcb init ${fastboot_buffer} nandboot ${fastboot_bytes}
-FB: Done
-
-Then U-Boot starts and its messages appear in the console program.
-
-Use the default environment variables:
-
-=> env default -f -a
-=> saveenv
diff --git a/doc/board/bsh/imx6ulz_bsh_smm_m2.rst b/doc/board/bsh/imx6ulz_bsh_smm_m2.rst
new file mode 100644
index 00000000000..c61dbfe2ae7
--- /dev/null
+++ b/doc/board/bsh/imx6ulz_bsh_smm_m2.rst
@@ -0,0 +1,85 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+How to Update U-Boot on imx6ulz_smm_m2 and imx6ulz_smm_m2b boards
+==================================================================================
+
+Required software on the host PC:
+
+- UUU: https://github.com/NXPmicro/mfgtools
+
+Build U-Boot for m2:
+
+.. code-block:: bash
+
+ $ make mrproper
+ $ make imx6ulz_smm_m2_defconfig
+ $ make
+
+Build U-Boot for m2b:
+
+.. code-block:: bash
+
+ $ make mrproper
+ $ make imx6ulz_smm_m2b_defconfig
+ $ make
+
+This generates the SPL and u-boot-dtb.img binaries.
+
+Loading U-Boot via USB Serial Download Protocol
+-----------------------------------------------
+
+Copy SPL and u-boot-dtb.img to the uuu folder.
+
+Load the U-Boot via USB:
+
+.. code-block:: bash
+
+ $ sudo uuu -v -b nand_script.lst u-boot-with-spl.imx
+
+where nand_script.lst contains the following:
+
+.. code-block::
+
+ uuu_version 1.2.39
+
+ # @_flash.bin | bootloader
+ # @_image [_flash.bin] | image burn to nand, default is the same as bootloader
+
+ # This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ
+ SDP: boot -f _flash.bin
+
+ # This command will be run when ROM support stream mode
+ # i.MX8QXP, i.MX8QM
+ SDPS: boot -f _flash.bin
+
+ # These commands will be run when use SPL and will be skipped if no spl
+ # SDPU will be deprecated. please use SDPV instead of SDPU
+ # {
+ SDPU: delay 1000
+ SDPU: write -f _flash.bin -offset 0x57c00
+ SDPU: jump
+ # }
+
+ # These commands will be run when use SPL and will be skipped if no spl
+ # if (SPL support SDPV)
+ # {
+ SDPV: delay 1000
+ SDPV: write -f _flash.bin -offset 0x11000
+ SDPV: jump
+ # }
+
+ FB: ucmd setenv fastboot_buffer ${loadaddr}
+ FB: download -f _image
+ FB: ucmd if test ! -n "$fastboot_bytes"; then setenv fastboot_bytes $filesize; else true; fi
+ # Burn image to nandfit partition if needed
+ FB: ucmd if env exists nandfit_part; then nand erase.part nandfit; nand write ${fastboot_buffer} nandfit ${fastboot_bytes}; else true; fi;
+ FB: ucmd nandbcb init ${fastboot_buffer} nandboot ${fastboot_bytes}
+ FB: Done
+
+Then U-Boot starts and its messages appear in the console program.
+
+Use the default environment variables:
+
+=> env default -f -a
+
+=> saveenv
diff --git a/doc/board/bsh/index.rst b/doc/board/bsh/index.rst
index 570ee4d72ed..e4f8b1f0b1c 100644
--- a/doc/board/bsh/index.rst
+++ b/doc/board/bsh/index.rst
@@ -7,3 +7,4 @@ BSH Hausgeraete GmbH
:maxdepth: 2
imx8mn_bsh_smm_s2
+ imx6ulz_bsh_smm_m2
--
2.48.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/3] bsh: imx6ulz_smm_m2: Update imx6ulz BSH SMM M2B board
2025-10-30 8:47 [PATCH v2 1/3] bsh: update readme with instructions to build M2B Andrea Calabrese
@ 2025-10-30 8:47 ` Andrea Calabrese
2025-10-30 8:47 ` [PATCH v2 3/3] bsh: imx6ulz_smm_m2: Add imx6ulz BSH SMM M2D board Andrea Calabrese
2025-10-30 13:36 ` [PATCH v2 1/3] bsh: update readme with instructions to build M2B Tom Rini
2 siblings, 0 replies; 5+ messages in thread
From: Andrea Calabrese @ 2025-10-30 8:47 UTC (permalink / raw)
To: u-boot, michael, dario.binacchi, trini, festevam; +Cc: andrea.calabrese
Improve support for the BSH SystemMaster (SMM) M2B board.
In particular, this patch adds the timing for the 512 MB version, and
the spi.c reflects it by removing the safe guards.
Signed-off-by: Andrea Calabrese <andrea.calabrese@amarulasolutions.com>
diff --git a/board/bsh/imx6ulz_smm_m2/Makefile b/board/bsh/imx6ulz_smm_m2/Makefile
index 233bbff4c16..5ab00a5ea75 100644
--- a/board/bsh/imx6ulz_smm_m2/Makefile
+++ b/board/bsh/imx6ulz_smm_m2/Makefile
@@ -4,4 +4,4 @@
obj-y := imx6ulz_smm_m2.o
obj-$(CONFIG_XPL_BUILD) += spl.o
obj-$(CONFIG_BSH_M2_MEMORY) += ddr3l_timing_512m.o ddr3l_timing_256m.o ddr3l_timing_128m.o
-obj-$(CONFIG_BSH_M2B_MEMORY) += ddr3l_timing_256m_m2b.o ddr3l_timing_128m_m2b.o
+obj-$(CONFIG_BSH_M2B_MEMORY) += ddr3l_timing_512m_m2b.o ddr3l_timing_256m_m2b.o ddr3l_timing_128m_m2b.o
diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m_m2b.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m_m2b.c
new file mode 100644
index 00000000000..04d39a9bdd6
--- /dev/null
+++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m_m2b.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "spl_mtypes.h"
+
+static const struct dram_cfg_param ddr_ddrc_cfg_512mb[] = {
+ /* ============================================================================= */
+ /* IOMUX */
+ /* ============================================================================= */
+ /* DDR IO TYPE: */
+ {0x020E04B4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
+ {0x020E04AC, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
+
+ /* CLOCK: */
+ {0x020E027C, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */
+
+ /* Control: */
+ {0x020E0250, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
+ {0x020E024C, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
+ {0x020E0490, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
+ {0x020E0288, 0x000C0030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
+ {0x020E0270, 0x00000000}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 */
+ /* DSE can be configured using Group Control Register: */
+ /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+ {0x020E0260, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */
+ {0x020E0264, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */
+ {0x020E04A0, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+
+ /* Data Strobes: */
+ {0x020E0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
+ {0x020E0280, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */
+ {0x020E0284, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */
+
+ /* Data: */
+ {0x020E04B0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
+ {0x020E0498, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
+ {0x020E04A4, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
+ {0x020E0244, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
+ {0x020E0248, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
+
+ /* ============================================================================= */
+ /* DDR Controller Registers */
+ /* ============================================================================= */
+ /* Manufacturer 1:NANYA */
+ /* Device Part Number 1:NT5CC256M16ER-EKI */
+ /* Manufacturer 2:MICRON */
+ /* Device Part Number 2:MT41K256M16TW-107 */
+ /* Clock Freq.: 400MHz */
+ /* Density per CS in Gb: 4 */
+ /* Chip Selects used:1 */
+ /* Total DRAM density (Gb)4 */
+ /* Number of Banks:8 */
+ /* Row address: 15 */
+ /* Column address: 10 */
+ /* Data bus width16 */
+ /* ============================================================================= */
+ {0x021B001C, 0x00008000}, /* [MMDC_MDSCR] MMDC Core Special Command Register */
+
+ /* ====================================================== */
+ /* Calibrations: */
+ /* ====================================================== */
+ {0x021B0800, 0xA1390003}, /* DDR_PHY_P0_MPZQHWCTRL, */
+ /* enable both one-time & periodic HW ZQ calibration. */
+
+ {0x021B080C, 0x00060002},
+ /* [MMDC_MPWLDECTRL0] MMDC PHY Write Leveling Delay Control Register 0 */
+ {0x021B083C, 0x41500158},
+ /* [MMDC_MPDGCTRL0] MMDC PHY Read DQS Gating Control Register 0 */
+ {0x021B0848, 0x40403A3E},
+ /* [MMDC_MPRDDLCTL] MMDC PHY Read delay-lines Configuration Register */
+ {0x021B0850, 0x40402E28},
+ /* [MMDC_MPWRDLCTL] MMDC PHY Write delay-lines Configuration Register */
+
+ {0x021B081C, 0x33333333}, /* [MMDC_MPRDDQBY0DL] MMDC PHY Read DQ Byte0 Delay Register */
+ {0x021B0820, 0x33333333}, /* [MMDC_MPRDDQBY1DL] MMDC PHY Read DQ Byte1 Delay Register */
+
+ {0x021B082C, 0xf3333333}, /* [MMDC_MPWRDQBY0DL] MMDC PHY Write DQ Byte0 Delay Register */
+ {0x021B0830, 0xf3333333}, /* [MMDC_MPWRDQBY1DL] MMDC PHY Write DQ Byte1 Delay Register */
+
+ {0x021B08C0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */
+
+ /* Complete calibration by forced measurement: */
+ {0x021B08B8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */
+
+ /* ====================================================== */
+ /* MMDC init: */
+ /* ====================================================== */
+ {0x021B0004, 0x0002002D}, /* MMDC0_MDPDC */
+ {0x021B0008, 0x1B333030}, /* MMDC0_MDOTC */
+ {0x021B000C, 0x616552F3}, /* MMDC0_MDCFG0 */
+ {0x021B0010, 0xB62C0A63}, /* MMDC0_MDCFG1 */
+ {0x021B0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */
+ {0x021B0018, 0x00201740}, /* MMDC0_MDMISC */
+ {0x021B002C, 0x000026D2}, /* MMDC0_MDRWD; recommend to maintain the default values */
+ {0x021B0030, 0x00651023}, /* MMDC0_MDOR */
+ {0x021B0040, 0x0000004F}, /* CS0_END */
+ {0x021B0000, 0x84180000}, /* MMDC0_MDCTL */
+
+ /* Mode register writes for CS0 */
+ {0x021B001C, 0x02008032}, /* MMDC0_MDSCR, MR2 write, CS0 */
+ {0x021B001C, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */
+ {0x021B001C, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */
+ {0x021B001C, 0x15208030}, /* MMDC0_MDSCR, MR0 write, CS0 */
+ {0x021B001C, 0x04008040},
+ /* MMDC0_MDSCR, ZQ calibration command sent to device on CS0 */
+
+ /* Mode register writes for CS, commented out automatically if only */
+ /* one chip select used */
+ /* {0x021B001C,0x0200803A}, */
+ /* {0x021B001C,0x0000803B}, */
+ /* {0x021B001C,0x00048039}, */
+ /* {0x021B001C,0x15208038}, */
+ /* {0x021B001C,0x04008048}, */
+
+ /* final DDR setup, before operation start: */
+ {0x021B0020, 0x00000800}, /* MMDC0_MDREF */
+ {0x021B0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */
+ {0x021B0004, 0x0002556D}, /* MMDC0_MDPDC now SDCTL power down enabled */
+ {0x021B0404, 0x00011006}, /* MMDC0_MAPSR ADOPT power down enabled */
+ {0x021B001C, 0x00000000}, /* MMDC0_MDSCR, clear this register */
+ /* (especially the configuration bit as initialization is complete) */
+};
+
+struct dram_timing_info bsh_dram_timing_512mb = {
+ .ddrc_cfg = ddr_ddrc_cfg_512mb,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_512mb),
+ .dram_size = SZ_512M,
+};
diff --git a/board/bsh/imx6ulz_smm_m2/spl.c b/board/bsh/imx6ulz_smm_m2/spl.c
index 7aea73f0f5d..580f5ab9dff 100644
--- a/board/bsh/imx6ulz_smm_m2/spl.c
+++ b/board/bsh/imx6ulz_smm_m2/spl.c
@@ -53,9 +53,7 @@ static void ddr_cfg_write(const struct dram_timing_info *dram_timing_info)
}
static const struct dram_timing_info *board_dram_timing[] = {
-#if defined(CONFIG_M2_MEMORY)
&bsh_dram_timing_512mb,
-#endif
&bsh_dram_timing_256mb,
&bsh_dram_timing_128mb,
};
--
2.48.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 3/3] bsh: imx6ulz_smm_m2: Add imx6ulz BSH SMM M2D board
2025-10-30 8:47 [PATCH v2 1/3] bsh: update readme with instructions to build M2B Andrea Calabrese
2025-10-30 8:47 ` [PATCH v2 2/3] bsh: imx6ulz_smm_m2: Update imx6ulz BSH SMM M2B board Andrea Calabrese
@ 2025-10-30 8:47 ` Andrea Calabrese
2025-10-30 13:36 ` [PATCH v2 1/3] bsh: update readme with instructions to build M2B Tom Rini
2 siblings, 0 replies; 5+ messages in thread
From: Andrea Calabrese @ 2025-10-30 8:47 UTC (permalink / raw)
To: u-boot, michael, dario.binacchi, trini, festevam; +Cc: andrea.calabrese
Introduce the BSH SystemMaster (SMM) M2D board. Notably, the M2D is
designed to leverage the existing device tree of its predecessors, the M2B
and the M2.
The primary distinction arises from memory incompatibilities with the M2B
and M2.
To address this, we've implemented a configuration system that allows for
selective inclusion of the desired memory components.
Signed-off-by: Andrea Calabrese <andrea.calabrese@amarulasolutions.com>
diff --git a/board/bsh/imx6ulz_smm_m2/Kconfig b/board/bsh/imx6ulz_smm_m2/Kconfig
index 20971aa4fe1..6c4321c3b5e 100644
--- a/board/bsh/imx6ulz_smm_m2/Kconfig
+++ b/board/bsh/imx6ulz_smm_m2/Kconfig
@@ -28,6 +28,12 @@ config BSH_M2B_MEMORY
If this option is enabled, U-Boot will be configured to support
imx6ulz bsh m2b revision memories.
+config BSH_M2D_MEMORY
+ bool "Enable for bsh m2d variant"
+ help
+ If this option is enabled, U-Boot will be configured to support
+ imx6ulz bsh m2d revision memories.
+
endchoice
endif
diff --git a/board/bsh/imx6ulz_smm_m2/MAINTAINERS b/board/bsh/imx6ulz_smm_m2/MAINTAINERS
index a75cddd72f8..098b992b07a 100644
--- a/board/bsh/imx6ulz_smm_m2/MAINTAINERS
+++ b/board/bsh/imx6ulz_smm_m2/MAINTAINERS
@@ -5,3 +5,4 @@ F: board/bsh/imx6ulz_smm_m2/
F: include/configs/imx6ulz_smm_m2.h
F: configs/imx6ulz_smm_m2_defconfig
F: configs/imx6ulz_smm_m2b_defconfig
+F: configs/imx6ulz_smm_m2d_defconfig
diff --git a/board/bsh/imx6ulz_smm_m2/Makefile b/board/bsh/imx6ulz_smm_m2/Makefile
index 5ab00a5ea75..81e47e3735e 100644
--- a/board/bsh/imx6ulz_smm_m2/Makefile
+++ b/board/bsh/imx6ulz_smm_m2/Makefile
@@ -5,3 +5,4 @@ obj-y := imx6ulz_smm_m2.o
obj-$(CONFIG_XPL_BUILD) += spl.o
obj-$(CONFIG_BSH_M2_MEMORY) += ddr3l_timing_512m.o ddr3l_timing_256m.o ddr3l_timing_128m.o
obj-$(CONFIG_BSH_M2B_MEMORY) += ddr3l_timing_512m_m2b.o ddr3l_timing_256m_m2b.o ddr3l_timing_128m_m2b.o
+obj-$(CONFIG_BSH_M2D_MEMORY) += ddr3l_timing_512m_m2d.o ddr3l_timing_256m_m2d.o ddr3l_timing_128m_m2d.o
\ No newline at end of file
diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m_m2d.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m_m2d.c
new file mode 100644
index 00000000000..5910858a930
--- /dev/null
+++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m_m2d.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "spl_mtypes.h"
+
+static const struct dram_cfg_param ddr_ddrc_cfg_128mb[] = {
+ /* IOMUX */
+
+ /* DDR IO TYPE: */
+ {0x020E04B4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
+ {0x020E04AC, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
+
+ /* CLOCK: */
+ {0x020E027C, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */
+
+ /* Control: */
+ {0x020E0250, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
+ {0x020E024C, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
+ {0x020E0490, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
+ {0x020E0288, 0x000C0028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
+ {0x020E0270, 0x00000000}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured */
+ /* using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+ {0x020E0260, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */
+ {0x020E0264, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */
+ {0x020E04A0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+
+ /* Data Strobes: */
+ {0x020E0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
+ {0x020E0280, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */
+ {0x020E0284, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */
+
+ /* Data: */
+ {0x020E04B0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
+ {0x020E0498, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
+ {0x020E04A4, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
+ {0x020E0244, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
+ {0x020E0248, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
+
+ /* ============================================================================= */
+ /* DDR Controller Registers */
+ /* ============================================================================= */
+ /* Manufacturer:WINBOND */
+ /* Device Part Number:W631GU6RB-11 */
+ /* Clock Freq.: 400MHz */
+ /* Density per CS in Gb: 1 */
+ /* Chip Selects used:1 */
+ /* Total DRAM density (Gb)1 */
+ /* Number of Banks:8 */
+ /* Row address: 13 */
+ /* Column address: 10 */
+ /* Data bus width16 */
+ /* ============================================================================= */
+ {0x021B001C, 0x00008000}, /* [MMDC_MDSCR] MMDC Core Special Command Register */
+
+ /* ====================================================== */
+ /* Calibrations: */
+ /* ====================================================== */
+ {0x021B0800, 0xA1390003}, /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic */
+ /* HW ZQ calibration. */
+
+ {0x021B080C, 0x00060002}, /* [MMDC_MPWLDECTRL0] MMDC PHY Write Leveling Delay Control */
+ /* Register 0 */
+ {0x021B083C, 0x414C0150}, /* [MMDC_MPDGCTRL0] MMDC PHY Read DQS Gating Control */
+ /* Register 0 */
+ {0x021B0848, 0x4040363E}, /* [MMDC_MPRDDLCTL] MMDC PHY Read delay-lines Configuration */
+ /* Register */
+ {0x021B0850, 0x40402A28}, /* [MMDC_MPWRDLCTL] MMDC PHY Write delay-lines Configuration */
+ /* Register */
+
+ {0x021B081C, 0x33333333}, /* [MMDC_MPRDDQBY0DL] MMDC PHY Read DQ Byte0 Delay Register */
+ {0x021B0820, 0x33333333}, /* [MMDC_MPRDDQBY1DL] MMDC PHY Read DQ Byte1 Delay Register */
+
+ {0x021B082C, 0xf3333333}, /* [MMDC_MPWRDQBY0DL] MMDC PHY Write DQ Byte0 Delay Register */
+ {0x021B0830, 0xf3333333}, /* [MMDC_MPWRDQBY1DL] MMDC PHY Write DQ Byte1 Delay Register */
+
+ {0x021B08C0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */
+
+ /* Complete calibration by forced measurement: */
+ {0x021B08B8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */
+
+ /* ====================================================== */
+ /* MMDC init: */
+ /* ====================================================== */
+ {0x021B0004, 0x0002002D}, /* MMDC0_MDPDC */
+ {0x021B0008, 0x1B333030}, /* MMDC0_MDOTC */
+ {0x021B000C, 0x2B2F52F3}, /* MMDC0_MDCFG0 */
+ {0x021B0010, 0xB66D0A63}, /* MMDC0_MDCFG1 */
+ {0x021B0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */
+ {0x021B0018, 0x00201740}, /* MMDC0_MDMISC */
+ {0x021B002C, 0x000026D2}, /* MMDC0_MDRWD; recommend to maintain the default values */
+ {0x021B0030, 0x002F1023}, /* MMDC0_MDOR */
+ {0x021B0040, 0x00000043}, /* CS0_END */
+ {0x021B0000, 0x82180000}, /* MMDC0_MDCTL */
+
+ /* Mode register writes for CS0 */
+ {0x021B001C, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */
+ {0x021B001C, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */
+ {0x021B001C, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */
+ {0x021B001C, 0x15208030}, /* MMDC0_MDSCR, MR0 write, CS0 */
+ {0x021B001C, 0x04008040}, /* MMDC0_MDSCR, ZQ calibration command sent to device on CS0 */
+
+ /* Mode register writes for CS, commented out automatically if only one chip select used */
+ /* {0x021B001C, 0x0200803A}, */
+ /* {0x021B001C, 0x0000803B}, */
+ /* {0x021B001C, 0x00048039}, */
+ /* {0x021B001C, 0x15208038}, */
+ /* {0x021B001C, 0x04008048}, */
+
+ /* final DDR setup, before operation start: */
+ {0x021B0020, 0x00000800}, /* MMDC0_MDREF */
+ {0x021B0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */
+ {0x021B0004, 0x0002556D}, /* MMDC0_MDPDC now SDCTL power down enabled */
+ {0x021B0404, 0x00011006}, /* MMDC0_MAPSR ADOPT power down enabled */
+ {0x021B001C, 0x00000000}, /* MMDC0_MDSCR, clear this register (especially the */
+ /* configuration bit as initialization is complete) */
+};
+
+struct dram_timing_info bsh_dram_timing_128mb = {
+ .ddrc_cfg = ddr_ddrc_cfg_128mb,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_128mb),
+ .dram_size = SZ_128M,
+};
diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m_m2d.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m_m2d.c
new file mode 100644
index 00000000000..d0ba01258f4
--- /dev/null
+++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m_m2d.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "spl_mtypes.h"
+
+static const struct dram_cfg_param ddr_ddrc_cfg_256mb[] = {
+ /* IOMUX */
+
+ /* DDR IO TYPE: */
+ {0x020E04B4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
+ {0x020E04AC, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
+
+ /* CLOCK: */
+ {0x020E027C, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */
+
+ /* Control: */
+ {0x020E0250, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
+ {0x020E024C, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
+ {0x020E0490, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
+ {0x020E0288, 0x000C0030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
+ {0x020E0270, 0x00000000}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured */
+ /* using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+ {0x020E0260, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */
+ {0x020E0264, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */
+ {0x020E04A0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+
+ /* Data Strobes: */
+ {0x020E0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
+ {0x020E0280, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */
+ {0x020E0284, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */
+
+ /* Data: */
+ {0x020E04B0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
+ {0x020E0498, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
+ {0x020E04A4, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
+ {0x020E0244, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
+ {0x020E0248, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
+
+ /* ============================================================================= */
+ /* DDR Controller Registers */
+ /* ============================================================================= */
+ /* Manufacturer:WINBOND */
+ /* Device Part Number:W632GU6RB-11 */
+ /* Clock Freq.: 400MHz */
+ /* Density per CS in Gb: 2 */
+ /* Chip Selects used:1 */
+ /* Total DRAM density (Gb)2 */
+ /* Number of Banks:8 */
+ /* Row address: 14 */
+ /* Column address: 10 */
+ /* Data bus width16 */
+ /* ============================================================================= */
+ {0x021B001C, 0x00008000}, /* [MMDC_MDSCR] MMDC Core Special Command Register */
+
+ /* ====================================================== */
+ /* Calibrations: */
+ /* ====================================================== */
+ {0x021B0800, 0xA1390003}, /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic */
+ /* HW ZQ calibration. */
+
+ {0x021B080C, 0x00070005}, /* [MMDC_MPWLDECTRL0] MMDC PHY Write Leveling Delay Control */
+ /* Register 0 */
+ {0x021B083C, 0x414C0150}, /* [MMDC_MPDGCTRL0] MMDC PHY Read DQS Gating Control */
+ /* Register 0 */
+ {0x021B0848, 0x4040383E}, /* [MMDC_MPRDDLCTL] MMDC PHY Read delay-lines Configuration */
+ /* Register */
+ {0x021B0850, 0x40402E2A}, /* [MMDC_MPWRDLCTL] MMDC PHY Write delay-lines Configuration */
+ /* Register */
+
+ {0x021B081C, 0x33333333}, /* [MMDC_MPRDDQBY0DL] MMDC PHY Read DQ Byte0 Delay Register */
+ {0x021B0820, 0x33333333}, /* [MMDC_MPRDDQBY1DL] MMDC PHY Read DQ Byte1 Delay Register */
+
+ {0x021B082C, 0xf3333333}, /* [MMDC_MPWRDQBY0DL] MMDC PHY Write DQ Byte0 Delay Register */
+ {0x021B0830, 0xf3333333}, /* [MMDC_MPWRDQBY1DL] MMDC PHY Write DQ Byte1 Delay Register */
+
+ {0x021B08C0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */
+
+ /* Complete calibration by forced measurement: */
+ {0x021B08B8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */
+
+ /* ====================================================== */
+ /* MMDC init: */
+ /* ====================================================== */
+ {0x021B0004, 0x00020024}, /* MMDC0_MDPDC */
+ {0x021B0008, 0x1B333030}, /* MMDC0_MDOTC */
+ {0x021B000C, 0x3F4352D3}, /* MMDC0_MDCFG0 */
+ {0x021B0010, 0xB66D0A63}, /* MMDC0_MDCFG1 */
+ {0x021B0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */
+ {0x021B0018, 0x00201740}, /* MMDC0_MDMISC */
+ {0x021B002C, 0x000026D2}, /* MMDC0_MDRWD; recommend to maintain the default values */
+ {0x021B0030, 0x00431023}, /* MMDC0_MDOR */
+ {0x021B0040, 0x00000047}, /* CS0_END */
+ {0x021B0000, 0x83180000}, /* MMDC0_MDCTL */
+
+ /* Mode register writes for CS0 */
+ {0x021B001C, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */
+ {0x021B001C, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */
+ {0x021B001C, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */
+ {0x021B001C, 0x15208030}, /* MMDC0_MDSCR, MR0 write, CS0 */
+ {0x021B001C, 0x04008040}, /* MMDC0_MDSCR, ZQ calibration command sent to device on CS0 */
+
+ /* Mode register writes for CS, commented out automatically */
+ /* if only one chip select used */
+ /* {0x021B001C, 0x0200803A}, */
+ /* {0x021B001C, 0x0000803B}, */
+ /* {0x021B001C, 0x00048039}, */
+ /* {0x021B001C, 0x15208038}, */
+ /* {0x021B001C, 0x04008048}, */
+
+ /* final DDR setup, before operation start: */
+ {0x021B0020, 0x00000800}, /* MMDC0_MDREF */
+ {0x021B0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */
+ {0x021B0004, 0x00025564}, /* MMDC0_MDPDC now SDCTL power down enabled */
+ {0x021B0404, 0x00011006}, /* MMDC0_MAPSR ADOPT power down enabled */
+ {0x021B001C, 0x00000000}, /* MMDC0_MDSCR, clear this register (especially the */
+ /* configuration bit as initialization is complete) */
+};
+
+struct dram_timing_info dram_timing_256mb = {
+ .ddrc_cfg = ddr_ddrc_cfg_256mb,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_256mb),
+ .dram_size = SZ_256M,
+};
diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m_m2d.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m_m2d.c
new file mode 100644
index 00000000000..e767f9ed641
--- /dev/null
+++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m_m2d.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "spl_mtypes.h"
+
+static const struct dram_cfg_param ddr_ddrc_cfg_512mb[] = {
+ /* ============================================================================= */
+ /* IOMUX */
+ /* ============================================================================= */
+ /* DDR IO TYPE: */
+ {0x020E04B4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
+ {0x020E04AC, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
+
+ /* CLOCK: */
+ {0x020E027C, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */
+
+ /* Control: */
+ {0x020E0250, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
+ {0x020E024C, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
+ {0x020E0490, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
+ {0x020E0288, 0x000C0030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
+ {0x020E0270, 0x00000000}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 */
+ /* DSE can be configured using Group Control Register: */
+ /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+ {0x020E0260, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */
+ {0x020E0264, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */
+ {0x020E04A0, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+
+ /* Data Strobes: */
+ {0x020E0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
+ {0x020E0280, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */
+ {0x020E0284, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */
+
+ /* Data: */
+ {0x020E04B0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
+ {0x020E0498, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
+ {0x020E04A4, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
+ {0x020E0244, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
+ {0x020E0248, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
+
+ /* ============================================================================= */
+ /* DDR Controller Registers */
+ /* ============================================================================= */
+ /* Manufacturer 1:NANYA */
+ /* Device Part Number 1:NT5CC256M16ER-EKI */
+ /* Manufacturer 2:MICRON */
+ /* Device Part Number 2:MT41K256M16TW-107 */
+ /* Clock Freq.: 400MHz */
+ /* Density per CS in Gb: 4 */
+ /* Chip Selects used:1 */
+ /* Total DRAM density (Gb)4 */
+ /* Number of Banks:8 */
+ /* Row address: 15 */
+ /* Column address: 10 */
+ /* Data bus width16 */
+ /* ============================================================================= */
+ {0x021B001C, 0x00008000}, /* [MMDC_MDSCR] MMDC Core Special Command Register */
+
+ /* ====================================================== */
+ /* Calibrations: */
+ /* ====================================================== */
+ {0x021B0800, 0xA1390003}, /* DDR_PHY_P0_MPZQHWCTRL, */
+ /* enable both one-time & periodic HW ZQ calibration. */
+
+ {0x021B080C, 0x00070004}, /* [MMDC_MPWLDECTRL0] MMDC PHY Write Leveling */
+ /* Delay Control Register 0 */
+ {0x021B083C, 0x414C014C}, /* [MMDC_MPDGCTRL0] MMDC PHY Read DQS */
+ /* Gating Control Register 0 */
+ {0x021B0848, 0x40403A3E}, /* [MMDC_MPRDDLCTL] MMDC PHY Read delay-lines */
+ /* Configuration Register */
+ {0x021B0850, 0x40402E28}, /* [MMDC_MPWRDLCTL] MMDC PHY Write delay-lines */
+ /* Configuration Register */
+
+ {0x021B081C, 0x33333333}, /* [MMDC_MPRDDQBY0DL] MMDC PHY Read DQ Byte0 Delay Register */
+ {0x021B0820, 0x33333333}, /* [MMDC_MPRDDQBY1DL] MMDC PHY Read DQ Byte1 Delay Register */
+
+ {0x021B082C, 0xf3333333}, /* [MMDC_MPWRDQBY0DL] MMDC PHY Write DQ Byte0 Delay Register */
+ {0x021B0830, 0xf3333333}, /* [MMDC_MPWRDQBY1DL] MMDC PHY Write DQ Byte1 Delay Register */
+
+ {0x021B08C0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */
+
+ /* Complete calibration by forced measurement: */
+ {0x021B08B8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */
+
+ /* ====================================================== */
+ /* MMDC init: */
+ /* ====================================================== */
+ {0x021B0004, 0x0002002D}, /* MMDC0_MDPDC */
+ {0x021B0008, 0x1B333030}, /* MMDC0_MDOTC */
+ {0x021B000C, 0x616552F3}, /* MMDC0_MDCFG0 */
+ {0x021B0010, 0xB62C0A63}, /* MMDC0_MDCFG1 */
+ {0x021B0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */
+ {0x021B0018, 0x00201740}, /* MMDC0_MDMISC */
+ {0x021B002C, 0x000026D2}, /* MMDC0_MDRWD; recommend to maintain the default values */
+ {0x021B0030, 0x00651023}, /* MMDC0_MDOR */
+ {0x021B0040, 0x0000004F}, /* CS0_END */
+ {0x021B0000, 0x84180000}, /* MMDC0_MDCTL */
+
+ /* Mode register writes for CS0 */
+ {0x021B001C, 0x02008032}, /* MMDC0_MDSCR, MR2 write, CS0 */
+ {0x021B001C, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */
+ {0x021B001C, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */
+ {0x021B001C, 0x15208030}, /* MMDC0_MDSCR, MR0 write, CS0 */
+ {0x021B001C, 0x04008040}, /* MMDC0_MDSCR, ZQ calibration command sent */
+ /* to device on CS0 */
+
+ /* Mode register writes for CS, commented out automatically */
+ /* if only one chip select used */
+ /* {0x021B001C,0x0200803A}, */
+ /* {0x021B001C,0x0000803B}, */
+ /* {0x021B001C,0x00048039}, */
+ /* {0x021B001C,0x15208038}, */
+ /* {0x021B001C,0x04008048}, */
+
+ /* final DDR setup, before operation start: */
+ {0x021B0020, 0x00000800}, /* MMDC0_MDREF */
+ {0x021B0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */
+ {0x021B0004, 0x0002556D}, /* MMDC0_MDPDC now SDCTL power down enabled */
+ {0x021B0404, 0x00011006}, /* MMDC0_MAPSR ADOPT power down enabled */
+ {0x021B001C, 0x00000000}, /* MMDC0_MDSCR, clear this register */
+ /* (especially the configuration bit as initialization is complete) */
+};
+
+struct dram_timing_info bsh_dram_timing_512mb = {
+ .ddrc_cfg = ddr_ddrc_cfg_512mb,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_512mb),
+ .dram_size = SZ_512M,
+};
diff --git a/configs/imx6ulz_smm_m2d_defconfig b/configs/imx6ulz_smm_m2d_defconfig
new file mode 100644
index 00000000000..ab80f94ba9a
--- /dev/null
+++ b/configs/imx6ulz_smm_m2d_defconfig
@@ -0,0 +1,82 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_MX6ULL=y
+CONFIG_TARGET_MX6ULZ_SMM_M2=y
+CONFIG_BSH_M2D_MEMORY=y
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6ulz-bsh-smm-m2"
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_BSS_START_ADDR=0x84100000
+CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_MTD=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:4m(nandboot),1m(env),8m(kernel),1m(nanddtb),-(rootfs)"
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+CONFIG_NO_NET=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX6UL=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_SYS_I2C_MXC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x111400
+CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x291400
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="BSH"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x877fffc0
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_IMX_WATCHDOG=y
diff --git a/doc/board/bsh/imx6ulz_bsh_smm_m2.rst b/doc/board/bsh/imx6ulz_bsh_smm_m2.rst
index c61dbfe2ae7..0af41c09d20 100644
--- a/doc/board/bsh/imx6ulz_bsh_smm_m2.rst
+++ b/doc/board/bsh/imx6ulz_bsh_smm_m2.rst
@@ -1,6 +1,6 @@
.. SPDX-License-Identifier: GPL-2.0+
-How to Update U-Boot on imx6ulz_smm_m2 and imx6ulz_smm_m2b boards
+How to Update U-Boot on imx6ulz_smm_m2, imx6ulz_smm_m2b and imx6ulz_smm_m2d boards
==================================================================================
Required software on the host PC:
@@ -23,6 +23,14 @@ Build U-Boot for m2b:
$ make imx6ulz_smm_m2b_defconfig
$ make
+Build U-Boot for m2d:
+
+.. code-block:: bash
+
+ $ make mrproper
+ $ make imx6ulz_smm_m2d_defconfig
+ $ make
+
This generates the SPL and u-boot-dtb.img binaries.
Loading U-Boot via USB Serial Download Protocol
--
2.48.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/3] bsh: update readme with instructions to build M2B
2025-10-30 8:47 [PATCH v2 1/3] bsh: update readme with instructions to build M2B Andrea Calabrese
2025-10-30 8:47 ` [PATCH v2 2/3] bsh: imx6ulz_smm_m2: Update imx6ulz BSH SMM M2B board Andrea Calabrese
2025-10-30 8:47 ` [PATCH v2 3/3] bsh: imx6ulz_smm_m2: Add imx6ulz BSH SMM M2D board Andrea Calabrese
@ 2025-10-30 13:36 ` Tom Rini
2025-10-31 7:45 ` Andrea Calabrese
2 siblings, 1 reply; 5+ messages in thread
From: Tom Rini @ 2025-10-30 13:36 UTC (permalink / raw)
To: Andrea Calabrese; +Cc: u-boot, michael, dario.binacchi, festevam
[-- Attachment #1: Type: text/plain, Size: 1004 bytes --]
On Thu, Oct 30, 2025 at 09:47:08AM +0100, Andrea Calabrese wrote:
> readme was missing instructions to build M2B. Now added.
>
> Signed-off-by: Andrea Calabrese <andrea.calabrese@amarulasolutions.com>
[snip]
> diff --git a/doc/board/bsh/imx6ulz_bsh_smm_m2.rst b/doc/board/bsh/imx6ulz_bsh_smm_m2.rst
> new file mode 100644
> index 00000000000..c61dbfe2ae7
> --- /dev/null
> +++ b/doc/board/bsh/imx6ulz_bsh_smm_m2.rst
> @@ -0,0 +1,85 @@
> +.. SPDX-License-Identifier: GPL-2.0+
> +
> +How to Update U-Boot on imx6ulz_smm_m2 and imx6ulz_smm_m2b boards
> +==================================================================================
Please see doc/build/documentation.rst for how to build the
documentation as there's errors here that will trip CI. Headings (===)
need to be the exact length as the text. Everything else is probably
fine but I can't always spot spacing errors without building. I don't
know if Fabio wants to fix this part up when applying. Thanks!
--
Tom
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/3] bsh: update readme with instructions to build M2B
2025-10-30 13:36 ` [PATCH v2 1/3] bsh: update readme with instructions to build M2B Tom Rini
@ 2025-10-31 7:45 ` Andrea Calabrese
0 siblings, 0 replies; 5+ messages in thread
From: Andrea Calabrese @ 2025-10-31 7:45 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot, michael, dario.binacchi, festevam
You are right, I used a tool to verify everything was in order, but I
did it in the last commit... Will send a v3.
Il 30/10/25 14:36, Tom Rini ha scritto:
> On Thu, Oct 30, 2025 at 09:47:08AM +0100, Andrea Calabrese wrote:
>
>> readme was missing instructions to build M2B. Now added.
>>
>> Signed-off-by: Andrea Calabrese <andrea.calabrese@amarulasolutions.com>
> [snip]
>> diff --git a/doc/board/bsh/imx6ulz_bsh_smm_m2.rst b/doc/board/bsh/imx6ulz_bsh_smm_m2.rst
>> new file mode 100644
>> index 00000000000..c61dbfe2ae7
>> --- /dev/null
>> +++ b/doc/board/bsh/imx6ulz_bsh_smm_m2.rst
>> @@ -0,0 +1,85 @@
>> +.. SPDX-License-Identifier: GPL-2.0+
>> +
>> +How to Update U-Boot on imx6ulz_smm_m2 and imx6ulz_smm_m2b boards
>> +==================================================================================
> Please see doc/build/documentation.rst for how to build the
> documentation as there's errors here that will trip CI. Headings (===)
> need to be the exact length as the text. Everything else is probably
> fine but I can't always spot spacing errors without building. I don't
> know if Fabio wants to fix this part up when applying. Thanks!
>
--
Andrea Calabrese
Embedded Software Developer
M. +39 339 394 4747
andrea.calabrese@amarulasolutions.com
__________________________________
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2025-10-30 8:47 [PATCH v2 1/3] bsh: update readme with instructions to build M2B Andrea Calabrese
2025-10-30 8:47 ` [PATCH v2 2/3] bsh: imx6ulz_smm_m2: Update imx6ulz BSH SMM M2B board Andrea Calabrese
2025-10-30 8:47 ` [PATCH v2 3/3] bsh: imx6ulz_smm_m2: Add imx6ulz BSH SMM M2D board Andrea Calabrese
2025-10-30 13:36 ` [PATCH v2 1/3] bsh: update readme with instructions to build M2B Tom Rini
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