From mboxrd@z Thu Jan 1 00:00:00 1970 From: duckycool Date: Tue, 26 May 2009 09:21:44 -0700 (PDT) Subject: [U-Boot] Please help for Data TLB Error in MPC8544 In-Reply-To: References: <23653353.post@talk.nabble.com> <23672726.post@talk.nabble.com> Message-ID: <23726526.post@talk.nabble.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Dave, It still shows data tlb error tho. I found it occur error around the GET_GOT of start.s. The SRR0 and SRR1 show the error address of system.map is _start_cont. Suspect the DDR setting problem ?? But I thought all the DDR setting are from SPD. So, I didn't set any entry of DDR in TLB1. Any hint? Liu Dave-R63238 wrote: > >> >EELADR - 0XF4010000, it is INIT_RAM address, why the >> transaction with >> >address(0xF4010000) go to system bus? >> >It should keep in the cache due to cache lock, never out to >> system bus. >> >> I don't know why... and it just happened.... shall I allocate >> a entry of tlb for it?? or cover it in some space ? > > Not need. > >> A quick question is, there is a FPGA(actel pixis) in >> mpc8544ds board, and it seems related with system clock ??? >> There is no such FPGA in my board, is it the problem?? > > It is possible to be problem. > >> Shall I remove the pixis related code from board.h and >> board.c and try to configure system clock by myself ?? Still >> confusing..... > > Yes, remove the pixis related code. Configure the sys clk directly. > > Thanks, Dave > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > > -- View this message in context: http://www.nabble.com/Please-help-for-Data-TLB-Error-in-MPC8544-tp23653353p23726526.html Sent from the Uboot - Users mailing list archive at Nabble.com.