From mboxrd@z Thu Jan 1 00:00:00 1970 From: yangguang3501 Date: Fri, 3 Jul 2009 11:26:22 +0800 (CST) Subject: [U-Boot] Porting u-boot to new PPC440EP board Message-ID: <2628639.181881246591582091.JavaMail.coremail@bj126app63.126.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi, I use a new board designing based on PPC440EP evaluating board, called yosemite. I use u-boot version 1.3.1. I reduce the SDRAM and Flash size to 128M and 16M, I do the porting works as decribed in th maillist"new board SDRAM conf",which you posted in last year. http://lists.denx.de/pipermail/u-boot/2008-November/042924.html and now face the same problem when u-boot run to trap_init, and get the same error message. When I add blr instruction to the trap_init function, it return but hang befor main loop. Would you like tell me how did you solve the problem , or how can I completely porting u-boot to the new board. Best regards, Yangguang ##########Board configuration deference############ ##Yosemite Cofiguration## FLASH (CS0) 64MBYTE NOR Flash (s29GL512N) SDRAM bank 0- 128MB bank 1- 128MB ## My Board configuration## FLASH (CS0) 16MBYTE NOR Flash (s29GL128N) SDRAM bank 0- 128MB bank 1- NONE #########Error message when run to trap_init######### U-Boot 1.3.1 (Jul 3 2009 - 10:36:26) CPU: AMCC PowerPC 440EP Rev. C at 333.333 MHz (PLB=133, OPB=66, EBC=33 MHz) I2C boot EEPROM disabled Bootstrap Option E - Boot ROM Location EBC (16 bits) Internal PCI arbiter enabled, PCI async ext clock used 32 kB I-Cache 32 kB D-Cache Board: Yosemite - AMCC PPC440EP Evaluatio I2C: ready DRAM: 128 MB Top of RAM usable for U-Boot at: 08000000 Reserving 555k for U-Boot at: 07f75000 Reserving 264k for malloc() at: 07f33000 Reserving 144 Bytes for Board Info at: 07f32f70 Reserving 48 Bytes for Global Data at: 07f32f40 Stack Pointer at: 07f32f28 New Stack Pointer is: 07f32f28 in board_init_f, before relocate_code in board_init_r Now running in RAM - U-Boot at: 07f75000 in board_init_r, before board_early_init_r in board_init_r, after board_early_init_r in board_init_r, after relocate command table in board_init_r, before trap_init Bus Fault @ 0x07f7773c, fixup 0x00000000 Machine Check Exception. Caused by (from msr): regs 07f32e00 Data Read PLB Error Machine Check exception is imprecise NIP: 07F7773C XER: 20000000 LR: 07F7773C REGS: 07f32e00 TRAP: 0200 DEAR: 0000000 0 MSR: 00021000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00 GPR00: 07F77314 07F32EF0 0000051B 07F75000 07F7E1C8 00000000 00000000 07F7773C GPR08: 00000600 00002098 03F940AA 13DE4354 07F32CB8 00000000 07FB4500 07FF5000 GPR16: 00000400 00000000 00000000 00000000 00000000 00000000 00000000 70002000 GPR24: 07F75000 07F32F28 07F32F70 07F35000 07F32F40 07F32F40 07FB46A8 00000000 Call backtrace: 07F7E1C0 07F776B0 machine check ### ERROR ### Please RESET the board ### #########Error message when add blr to the trap_init function######### U-Boot 1.3.1 (Jul 3 2009 - 09:25:59) CPU: AMCC PowerPC 440EP Rev. C at 333.333 MHz (PLB=133, OPB=66, EBC=33 MHz) I2C boot EEPROM disabled Bootstrap Option E - Boot ROM Location EBC (16 bits) Internal PCI arbiter enabled, PCI async ext clock used 32 kB I-Cache 32 kB D-Cache Board: Yosemite - AMCC PPC440EP Evaluation Board, Rev. FF, PCI=66 MHz I2C: ready DRAM: 128 MB Top of RAM usable for U-Boot at: 08000000 Reserving 555k for U-Boot at: 07f75000 Reserving 264k for malloc() at: 0 Reserving 144 Bytes for Board Info at: 07f32f70 Reserving 48 Bytes for Global Data at: 07f32f40 Stack Pointer at: 07f32f28 New Stack Pointer is: 07f32f28 in board_init_f, before relocate_code in board_init_r Now running in RAM - U-Boot at: 07f75000 in board_init_r, before board_early_init_r in board_init_r, after board_early_init_r in board_init_r, after relocate command table in board_init_r, before trap_init in board_init_r, after trap_init FLASH: flash detect cfi fwc addr ff000000 cmd 0 0 8bit x 8 bit fwc addr ff000055 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr ff000010 is= ff 51 fwc addr ff000555 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr ff000010 is= ff 51 fwc addr ff000000 cmd 0 0000 16bit x 8 bit fwc addr ff0000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr ff000020 is= 0051 5151 fwc addr ff000aaa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr ff000020 is= 0051 5151 fwc addr ff000000 cmd 0 0000 16bit x 16 bit fwc addr ff0000aa cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr ff000020 is= 0051 0051 is= cmd 52(R) addr ff000022 is= 0052 0052 is= cmd 59(Y) addr ff000024 is= 0059 0059 ushort addr is at ff000050 info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x2 addr[2] = 0x0 addr[3] = 0x0 retval = 0x2 device interface is 2 found port 2 chip 2 port 16 bits chip 16 bits ushort addr is at ff000026 info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x2 addr[2] = 0x0 addr[3] = 0x0 retval = 0x2 fwc addr ff000000 cmd f0 00f0 16bit x 16 bit fwc addr ff000aaa cmd aa 00aa 16bit x 16 bit fwc addr ff000554 cmd 55 0055 16bit x 16 bit fwc addr ff000aaa cmd 90 0090 16bit x 16 bit fwc addr ff000000 cmd f0 00f0 16bit x 16 bit fwc addr ff0000aa cmd 98 0098 16bit x 16 bit ushort addr is at ff00002a info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x40 addr[2] = 0x0 addr[3] = 0x0 retval = 0x40 ff000020 : 00 51 00 52 00 59 00 02 00 00 00 40 00 00 00 00 .Q.R.Y..... at .... ff000030 : 00 00 00 00 00 00 00 27 00 36 00 00 00 00 00 07 .......'.6...... ff000040 : 00 07 00 0a 00 00 00 03 00 05 00 04 00 00 00 18 ................ ff000050 : 00 02 00 00 00 05 00 00 00 01 00 7f 00 00 00 00 ................ ff000060 : 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ff000070 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ff000080 : 00 50 00 52 00 49 00 31 00 33 00 10 00 02 00 01 .P.R.I.1.3...... ff000090 : 00 00 00 08 00 00 00 00 00 02 00 b5 00 c5 00 05 ................ manufacturer is 2 manufacturer id is 0x1 device id is 0x7e device id2 is 0x2101 cfi version is 0x3133 size_ratio 1 port 16 bits chip found 1 erase regions long addr is at ff00005a info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x7f addr[2] = 0x0 addr[3] = 0x0 addr[4] = 0x0 addr[5] = 0x0 addr[6] = 0x0 addr[7] = 0x2 erase_region_count = 128 erase_region_size = 131072 ushort addr is at ff000054 info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x5 addr[2] = 0x0 addr[3] = 0x0 retval = 0x5 fwc addr ff000000 cmd f0 00f0 16bit x 16 bit flash_protect ON: from 0xFFF80000 to 0xFFFBA9FF protect on 124 protect on 125 flash_protect ON: from 0xFFF60000 to 0xFFF7FFFF protect on 123 flash_protect ON: from 0xFFF40000 to 0xFFF41FFF protect on 122 16 MB *** Warning - bad CRC, using default environment PCI: Bus Dev VenId DevId Class Int