[U-Boot-Users] PPC405GPr reset troubles

[Stephen Williams <gfi8d1h02@sneakemail.com>]

This may be slightly off-topic, but the hardware is as right
as I can get it, so I'm looking for some sort of software problem.

I am having trouble with the "reset" command, and the /SysReset
in particular, in connection with the EBC clock settings. The
PSR (Pin Strapping Register) is spontaneously changing values
on the /SysReset. In particular, the external bus clock divisor
is changing from /4 to /2. I've added a dump of the PSR right
where U-Boot prints the CPU speeds, and I get the following:

U-Boot 1.0.2 (Mar  5 2004 - 17:03:00)

XXXX PSR=0xfdfc0ce0
CPU:   IBM PowerPC 405GPr Rev. B at 266.500 MHz (PLB=133, OPB=33, EBC=33 MHz)
        PCI sync clock at 33 MHz, internal PCI arbiter enabled
        16 kB I-Cache 16 kB D-Cache
[...etc...]
?> reset

U-Boot 1.0.2 (Mar  5 2004 - 17:03:00)

XXXX PSR=0xfdf80ce0
CPU:   IBM PowerPC 405GPr Rev. B at 266.500 MHz (PLB=133, OPB=33, EBC=66 MHz)
        PCI sync clock at 33 MHz, internal PCI arbiter enabled
        16 kB I-Cache 16 kB D-Cache


I see with an O'Scope that the EMCTxEN signal (which is the
difference between PSR values) is really low during the /SysReset,
and it is clearly stable low then. But the PSR is read-only?
Why is my PSR wrong?

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at XXXXXXXXXX           But I have promises to keep,
http://www.XXXXXXXXXX         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."