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[213.161.4.198]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356996cefdsm23132480f8f.24.2026.01.19.07.31.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jan 2026 07:31:05 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: u-boot@lists.denx.de, Andre Przywara Cc: Rudi Horn , linux-sunxi@lists.linux.dev Subject: Re: [PATCH v2] sunxi: dram: detect non-power-of-2 sized DRAM chips Date: Mon, 19 Jan 2026 16:31:03 +0100 Message-ID: <2813637.mvXUDI8C0e@jernej-laptop> In-Reply-To: <20260118235905.23752-1-andre.przywara@arm.com> References: <20260118235905.23752-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Dne ponedeljek, 19. januar 2026 ob 00:59:05 Srednjeevropski standardni =C4= =8Das je Andre Przywara napisal(a): > Some boards feature an "odd" DRAM size, where the total RAM is 1.5GB or > 3GB. Our existing DRAM size detection routines can only detect power-of-2 > sized configuration, and on those boards the DRAM size is overestimated, > so this typically breaks the boot quite early. >=20 > There doesn't seem to be an easy explicit way to detect those odd-sized > chips, but we can test whether the later part of the memory behaves like > memory, by verifying that a written pattern can be read back. > Experiments show that there is no aliasing effect here, as all locations > in the unimplemented range always return some fixed pattern, and cannot > be changed. >=20 > Also so far all those boards use a factor of 3 of some lower power-of-2 > number, or 3/4th of some higher number. The size detection routine > discovers the higher number, so we can check for some memory cells beyond > 75% of the detected size to be legit. >=20 > Add a routine the inverts all bits at a given location in memory, and > reads that back to prove that the new value was stored. > Then test the memory cell at exactly 3/4th of the detected size, and cap > the size of the memory to 75% when this test fails. For good measure > also make sure that memory just below the assumed memory end really > works. >=20 > This enables boards which ship with such odd memory sizes. >=20 > Signed-off-by: Andre Przywara > --- > Hi, >=20 > v2 just adds the "positive" check, so whether memory just below 3/4th is > accessible, when the test for above 3/4th failed. > Please test if you have a board with such "odd"-sized DRAM. >=20 > Cheers, > Andre This looks good to me now! Reviewed-by: Jernej Skrabec Best regards, Jernej >=20 > arch/arm/include/asm/arch-sunxi/dram.h | 1 + > arch/arm/mach-sunxi/dram_dw_helpers.c | 22 +++++++++++++++++++++- > arch/arm/mach-sunxi/dram_helpers.c | 12 ++++++++++++ > 3 files changed, 34 insertions(+), 1 deletion(-) >=20 > diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/as= m/arch-sunxi/dram.h > index 0eccb1e6c28..59e2e980bfa 100644 > --- a/arch/arm/include/asm/arch-sunxi/dram.h > +++ b/arch/arm/include/asm/arch-sunxi/dram.h > @@ -45,5 +45,6 @@ unsigned long sunxi_dram_init(void); > void mctl_await_completion(u32 *reg, u32 mask, u32 val); > bool mctl_mem_matches(u32 offset); > bool mctl_mem_matches_base(u32 offset, ulong base); > +bool mctl_check_memory(phys_addr_t addr); > =20 > #endif /* _SUNXI_DRAM_H */ > diff --git a/arch/arm/mach-sunxi/dram_dw_helpers.c b/arch/arm/mach-sunxi/= dram_dw_helpers.c > index 24767354935..d2af2d57fde 100644 > --- a/arch/arm/mach-sunxi/dram_dw_helpers.c > +++ b/arch/arm/mach-sunxi/dram_dw_helpers.c > @@ -143,8 +143,28 @@ void mctl_auto_detect_dram_size(const struct dram_pa= ra *para, > =20 > unsigned long mctl_calc_size(const struct dram_config *config) > { > + unsigned long size; > u8 width =3D config->bus_full_width ? 4 : 2; > =20 > /* 8 banks */ > - return (1ULL << (config->cols + config->rows + 3)) * width * config->ra= nks; > + size =3D (1ULL << (config->cols + config->rows + 3)) * width * > + config->ranks; > + > + /* > + * There are boards with non-power-of-2 sized DRAM chips, like 1.5GB > + * or 3GB. They are detected as the larger power-of-2 (2GB and 4GB), > + * so test the last quarter for being able to store values. > + */ > + if (!mctl_check_memory(CFG_SYS_SDRAM_BASE + size / 4 * 3)) { > + if (mctl_check_memory(CFG_SYS_SDRAM_BASE + size / 4 * 3 - 64)) { > + size =3D (size / 4) * 3; > + debug("capping memory at %ld MB\n", size >> 20); > + } else { > + printf("DRAM test failure at address 0x%lx\n", > + CFG_SYS_SDRAM_BASE + size / 4 * 3 - 64); > + return 0; > + } > + } > + > + return size; > } > diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dra= m_helpers.c > index 83dbe4ca98f..376b7d14f86 100644 > --- a/arch/arm/mach-sunxi/dram_helpers.c > +++ b/arch/arm/mach-sunxi/dram_helpers.c > @@ -62,3 +62,15 @@ bool mctl_mem_matches(u32 offset) > return mctl_mem_matches_base(offset, CFG_SYS_SDRAM_BASE); > } > #endif > + > +bool mctl_check_memory(phys_addr_t addr) > +{ > + uint32_t orig, val; > + > + orig =3D readl(addr); > + writel(~orig, addr); > + val =3D readl(addr); > + writel(orig, addr); > + > + return ~orig =3D=3D val; > +} >=20